Patches 1,2,4:

Reviewed-by: Marek Olšák <marek.ol...@amd.com>

I replied on 3 and 6. I'm not sure off hand about 5,7,8.

Marek

On Tue, Nov 10, 2015 at 5:10 AM, Dave Airlie <airl...@gmail.com> wrote:
> From: Dave Airlie <airl...@redhat.com>
>
> On some chips the GSVS itemsize needs to be aligned to a cacheline size.
>
> This only applies to some of the r600 family chips.
>
> Signed-off-by: Dave Airlie <airl...@redhat.com>
> ---
>  src/gallium/drivers/r600/r600_state.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
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