On Fri, Oct 30, 2015 at 6:02 PM, Connor Abbott wrote:
> Before, we simply assumed that reducing register pressure was the number
> one priority in the pre-RA scheduler, and set the latency of every
> instruction to 1 to get the scheduler to ignore it. But for the
> aggressive scheduler, this doesn
Before, we simply assumed that reducing register pressure was the number
one priority in the pre-RA scheduler, and set the latency of every
instruction to 1 to get the scheduler to ignore it. But for the
aggressive scheduler, this doesn't make much sense. It can also allow
the register allocator to
