Before, we simply assumed that reducing register pressure was the number
one priority in the pre-RA scheduler, and set the latency of every
instruction to 1 to get the scheduler to ignore it. But for the
aggressive scheduler, this doesn't make much sense. It can also allow
the register allocator to introduce additional false dependencies that
disallowing us from putting instructions in a better order, when we
could avoid the whole thing by putting them in that order in the first
place. The only issue that this causes is that we may fall back to the
register pressure scheduler, which is even worse for latencies, by
making the first schedule more aggressive, but soon we'll switching to
that strategy dynamically based on register pressure anyways, at which
point making the latencies only 1 makes no sense at all.
total instructions in shared programs: 7440130 -> 7447753 (0.10%)
instructions in affected programs: 32614 -> 40237 (23.37%)
helped: 4
HURT: 26
total cycles in shared programs: 56282914 -> 52733940 (-6.31%)
cycles in affected programs: 34510450 -> 30961476 (-10.28%)
helped: 23664
HURT: 3343
LOST: 257
GAINED: 35
Signed-off-by: Connor Abbott <cwabbo...@gmail.com>
---
src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 2698399..a611dd1 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -777,9 +777,7 @@ schedule_node::schedule_node(backend_instruction *inst,
/* We can't measure Gen6 timings directly but expect them to be much
* closer to Gen7 than Gen4.
*/
- if (!sched->post_reg_alloc)
- this->latency = 1;
- else if (devinfo->gen >= 6)
+ if (devinfo->gen >= 6)
set_latency_gen7(devinfo->is_haswell);
else
set_latency_gen4();
--
2.4.3
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