[Mesa-dev] [PATCH] mesa/state_tracker: explicitely handle case ir_intrinsic_begin_fragment_shader_ordering in visit_generic_intrinsic()

From: Kevin Rogovin --- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index 7b96947c60..48a7b030ce 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp

[Mesa-dev] [PATCH 2/2] i965: Add INTEL_fragment_shader_ordering support.

From: Kevin Rogovin Adds suppport for INTEL_fragment_shader_ordering. We achieve the fragment ordering by using the same instruction as for beginInvocationInterlockARB() which is by issuing a memory fence via sendc. Signed-off-by: Kevin Rogovin --- docs/relnotes/18.3.0.html

[Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

From: Kevin Rogovin INTEL_fragment_shader_ordering provides the ability for shaders to issue a call to gaurnantee memory write operation ordering of overlapping pixels or samples. In contrast to ARB_fragment_shader_interlock, INTEL_fragment_shader_ordering instead of defining a critical region

[Mesa-dev] [PATCH 1/2] mesa: Add GL/GLSL plumbing for INTEL_fragment_shader_ordering.

From: Kevin Rogovin This extension provides new GLSL built-in function beginFragmentShaderOrderingIntel() that guarantees (taking wording of GL_INTEL_fragment_shader_ordering extension) that any memory transactions issued by shader invocations from previous primitives mapped to

[Mesa-dev] [PATCH] docs/relnotes: Mark NV_fragment_shader_interlock support in i965

From: Kevin Rogovin --- docs/relnotes/18.3.0.html | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html index 594b0624a5..afcb044817 100644 --- a/docs/relnotes/18.3.0.html +++ b/docs/relnotes/18.3.0.html @@ -59,6 +59,7 @@ Note: some of the new

[Mesa-dev] [PATCH] docs/relnotes: Mark NV_fragment_shader_interlock support in i965

From: Kevin Rogovin --- docs/relnotes/18.3.0.html | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html index 594b0624a5..afcb044817 100644 --- a/docs/relnotes/18.3.0.html +++ b/docs/relnotes/18.3.0.html @@ -59,6 +59,7 @@ Note: some of the new

Re: [Mesa-dev] [PATCH] Add NV_fragment_shader_interlock support.

Thankyou for pushing; I will post the one liner for the release notes shortly. Best Regards, -Kevin Rogovin On Fri, 24 Aug 2018 at 3.44, Jason Ekstrand wrote: > Your first version has already landed; Ken pushed it: > > > https://cgit.freedesktop.org/mesa/mesa/c

[Mesa-dev] [PATCH v2] Add NV_fragment_shader_interlock support.

From: Kevin Rogovin The main purpose for having NV_fragment_shader_interlock extension is because that extension is also for GLES31 while the ARB extension is for GL only. v2: Add to review notes (requested by Emil Velikov) Reviewed-by: Plamena Manolova --- docs/relnotes/18.3.0.html

Re: [Mesa-dev] [PATCH] Add NV_fragment_shader_interlock support.

Hi, My request for an account was NAK'd by the i965 maintainer. As such, I will post a v2 with the update to release notes requested and I hope Plamena can push that for me. Best Regards, -Kevin Rogovin On Tue, Aug 21, 2018 at 12:39 PM Emil Velikov wrote: > Hi Kevin, > > On

Re: [Mesa-dev] [PATCH] Add NV_fragment_shader_interlock support.

nolova > > On Wed, Aug 15, 2018 at 2:29 PM, wrote: > >> From: Kevin Rogovin >> >> The main purpose for having NV_fragment_shader_interlock >> extension is because that extension is also for GLES31 while >> the ARB extension is for GL only.

Re: [Mesa-dev] [PATCH] Add NV_fragment_shader_interlock support.

at 2:29 PM, wrote: > >> From: Kevin Rogovin >> >> The main purpose for having NV_fragment_shader_interlock >> extension is because that extension is also for GLES31 while >> the ARB extension is for GL only. >> --- >> src/compiler/glsl/built

[Mesa-dev] [PATCH] Add NV_fragment_shader_interlock support.

From: Kevin Rogovin The main purpose for having NV_fragment_shader_interlock extension is because that extension is also for GLES31 while the ARB extension is for GL only. --- src/compiler/glsl/builtin_functions.cpp | 18 ++ src/compiler/glsl/glsl_parser.yy | 6

[Mesa-dev] [PATCH v4 0/3] i965: ASTC5x5 workaround

From: Kevin Rogovin This patch series implements a needed workaround for Gen9 for ASTC5x5 sampler reads. The crux of the work around is to make sure that the sampler does not read an ASTC5x5 texture and a surface with an auxilary buffer without having a texture cache invalidate and command

[Mesa-dev] [PATCH v4 2/3] i965: prevent using auxilary buffers when an astc5x5 texture is present

From: Kevin Rogovin If ASTC5x5 textures are present, resolve all textures that the sampler accesses so that auxilary buffer is unneeded when the astc5x5 workaround is needed and also program the sampler state to not use the auxilary buffer as well. Signed-off-by: Kevin Rogovin --- src/mesa

[Mesa-dev] [PATCH v4 3/3] i965: ASTC5x5 workaround logic for blorp

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/blorp/blorp.c | 16 src/intel/blorp/blorp.h | 6 ++ src/mesa/drivers/dri/i965/genX_blorp_exec.c | 9 + 3 files changed, 31 insertions(+) diff --git a/src/intel

[Mesa-dev] [PATCH v4 1/3] i965: define astx5x5 workaround infrastructure

From: Kevin Rogovin Gen9 GPU's suffer from a HW bug where the GPU will hang if the GPU accesses a texture with a an auxilary buffer and an ASTC5x5 texture without having a pipeline cs stall (and texture cache flush) between such accesses. This patch creates the infrastucture to track

[Mesa-dev] [PATCH v3 2/7] i965: restore diable_aux argument to intel_miptree_prepare_texture()

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_draw.c | 9 ++--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +++-- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/src

[Mesa-dev] [PATCH v3 6/7] i965: use ASTC5x5 workaround in brw_dispatch_compute_common()

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_compute.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_compute.c b/src/mesa/drivers/dri/i965/brw_compute.c index 5ce899b..ec96687 100644 --- a/src/mesa/drivers/dri

[Mesa-dev] [PATCH v3 3/7] i965: set ASTC5x5 workaround texture type tracking on texture validate

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/intel_tex_validate.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c index eaa60ba..2bf6c65

[Mesa-dev] [PATCH v3 0/7] i965: ASTC5x5 workaround

From: Kevin Rogovin This patch series implements a needed workaround for Gen9 for ASTC5x5 sampler reads. The crux of the work around is to make sure that the sampler does not read an ASTC5x5 texture and a surface with an auxilary buffer without having a texture cache invalidate and command

[Mesa-dev] [PATCH v3 5/7] i965: use ASTC5x5 workaround in brw_prepare_drawing()

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_draw.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 34f4de3..f891e91 100644 --- a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH v3 4/7] i965: prevent using auxilary buffers when an astc5x5 texture is present

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_draw.c | 20 ++-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 7 +-- 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c

[Mesa-dev] [PATCH v3 1/7] i965: define astx5x5 workaround infrastructure

From: Kevin Rogovin Gen9 GPU's suffer from a HW bug where the GPU will hang if the GPU accesses a texture with a an auxilary buffer and an ASTC5x5 texture without having a pipeline cs stall (and texture cache flush) between such accesses. This patch creates the infrastucture to track

[Mesa-dev] [PATCH v3 7/7] i965: ASTC5x5 workaround logic for blorp

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/genX_blorp_exec.c | 5 + src/mesa/drivers/dri/i965/intel_tex_image.c | 16 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src

[Mesa-dev] [PATCH v4 3/3] i965: if DEBUG_CHECK_OOB is up, check that noise padding for each bo used in batchbuffer is correct

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 22 +- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index

[Mesa-dev] [PATCH v4 1/3] intel/common:add debug flag for adding and checking padding on BO's

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/common/gen_debug.c | 1 + src/intel/common/gen_debug.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_debug.c index a978f2f581..27ddbd0d6b 100644 --- a/src/intel/common

[Mesa-dev] [PATCH v4 2/3] i965: add noise padding to buffer object and function to check if noise is correct

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_bufmgr.c | 101 - src/mesa/drivers/dri/i965/brw_bufmgr.h | 13 + 2 files changed, 113 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src

[Mesa-dev] [PATCH v4 0/3] GEM BO padding to find OOB buffer writes

From: Kevin Rogovin This patch series adds a new debug option to pad each GEM BO allocated by the brw_bufmgr with (weak) pseudo-random noise values which are then checked after each batchbuffer dispatch to the kernel. This can be quite valuable to find diffucult to track down heisenberg style

[Mesa-dev] [PATCH v3 1/3] intel/common:add debug flag for adding and checking padding on BO's

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/common/gen_debug.c | 1 + src/intel/common/gen_debug.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_debug.c index a978f2f581..2154b23756 100644 --- a/src/intel/common

[Mesa-dev] [PATCH v3 0/3] GEM BO padding to find OOB buffer writes

From: Kevin Rogovin This patch series adds a new debug option to pad each GEM BO allocated by the brw_bufmgr with (weak) pseudo-random noise values which are then checked after each batchbuffer dispatch to the kernel. This can be quite valuable to find diffucult to track down heisenberg style

[Mesa-dev] [PATCH v3 3/3] i965: if DEBUG_OUT_OF_BOUND_CHK is up, check that noise padding for each bo used in batchbuffer is correct

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 22 +- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index

[Mesa-dev] [PATCH v3 2/3] i965: add noise padding to buffer object and function to check if noise is correct

From: Kevin Rogovin Signed-off-by: Kevin Rogovin Reviewed-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_bufmgr.c | 115 - src/mesa/drivers/dri/i965/brw_bufmgr.h | 13 2 files changed, 127 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers

[Mesa-dev] [PATCH v3 3/3] i965: if DEBUG_OUT_OF_BOUND_CHK is up, check that noise padding for each bo used in batchbuffer is correct

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 22 +- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index

[Mesa-dev] [PATCH v3 2/3] i965: add noise padding to buffer object and function to check if noise is correct

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_bufmgr.c | 115 - src/mesa/drivers/dri/i965/brw_bufmgr.h | 13 2 files changed, 127 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src

[Mesa-dev] [PATCH v3 1/3] intel/common:add debug flag for adding and checking padding on BO's

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/common/gen_debug.c | 1 + src/intel/common/gen_debug.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_debug.c index a978f2f581..2154b23756 100644 --- a/src/intel/common

[Mesa-dev] [PATCH v3 0/3] GEM BO padding to find OOB buffer writes

From: Kevin Rogovin This patch series adds a new debug option to pad each GEM BO allocated by the brw_bufmgr with pseudo-(weak) random noise values which are then checked after each batchbuffer dispatch to the kernel. This can be quite valuable to find diffucult to track down heisenberg style

[Mesa-dev] [PATCH v2 2/5] i965: set ASTC5x5 workaround texture type tracking on texture validate

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/intel_tex_validate.c | 13 + 1 file changed, 13 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c index 2b7798c..812c0c7 100644

[Mesa-dev] [PATCH v2 1/5] i965: define astx5x5 workaround infrastructure

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/Makefile.sources| 1 + src/mesa/drivers/dri/i965/brw_context.c | 6 + src/mesa/drivers/dri/i965/brw_context.h | 24 ++ src/mesa/drivers/dri/i965/gen9_astc5x5_wa.c | 36

[Mesa-dev] [PATCH v2 4/5] i965: use ASTC5x5 workaround in brw_compute

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_compute.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_compute.c b/src/mesa/drivers/dri/i965/brw_compute.c index 9be7523..c8d90f5 100644 --- a/src/mesa/drivers/dri

[Mesa-dev] [PATCH v2 3/5] i965: use ASTC5x5 workaround in brw_draw

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_draw.c | 16 ++-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 + 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src

[Mesa-dev] [PATCH v2 5/5] i965: ASTC5x5 workaround logic for blorp

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/genX_blorp_exec.c | 5 + src/mesa/drivers/dri/i965/intel_tex_image.c | 16 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src

[Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround

From: Kevin Rogovin This patch series implements a needed workaround for Gen9 for ASTC5x5 sampler reads. The crux of the work around is to make sure that the sampler does not read an ASTC5x5 texture and a surface with an auxilary buffer without having a texture cache invalidate and command

[Mesa-dev] [PATCH v2 3/3] i965: if DEBUG_OUT_OF_BOUND_CHK is up, check that noise padding for each bo used in batchbuffer is correct

From: Kevin Rogovin v2: Comments indicating that brw_bo_padding_is_good() will do the required waiting for GPU commands to finish Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/src/mesa

[Mesa-dev] [PATCH v2 1/3] intel/common:add debug flag for adding and checking padding on BO's

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/common/gen_debug.c | 1 + src/intel/common/gen_debug.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_debug.c index a978f2f581..2154b23756 100644 --- a/src/intel/common

[Mesa-dev] [PATCH v2 2/3] i965: add noise padding to buffer object and function to check if noise is correct

From: Kevin Rogovin v2: Change from using rand() to using internal generating function (requested/suggested by Jason Ekstrand) Avoid having extra pointers in brw_bo struct via using the internal function and allocating buffer for pread at brw_bo_padding_is_good() (requested/suggested by

[Mesa-dev] [PATCH v2 0/3] GEM BO padding to find OOB buffer writes

From: Kevin Rogovin This patch series adds a new debug option to pad each GEM BO allocated by the brw_bufmgr with pseudo-(weak) random noise values which are then checked after each batchbuffer dispatch to the kernel. This can be quite valuable to find diffucult to track down heisenberg style

[Mesa-dev] [PATCH 2/3] i965: add noise padding to buffer object and function to check if noise is correct

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_bufmgr.c | 105 - src/mesa/drivers/dri/i965/brw_bufmgr.h | 8 +++ 2 files changed, 112 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src

[Mesa-dev] [PATCH 0/3] GEM BO padding to find OOB buffer writes

From: Kevin Rogovin This patch series adds a new debug option to pad each GEM BO allocated by the brw_bufmgr with pseudo-(weak) random noise values which are then checked after each batchbuffer dispatch to the kernel. This can be quite valuable to find diffucult to track down heisenberg style

[Mesa-dev] [PATCH 3/3] i965: if DEBUG_OUT_OF_BOUND_CHK is up, check that noise padding for each bo used in batchbuffer is correct

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index 91a6506a89

[Mesa-dev] [PATCH 1/3] intel/common:add debug flag for adding and checking padding on BO's

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/common/gen_debug.c | 1 + src/intel/common/gen_debug.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_debug.c index a978f2f581..2154b23756 100644 --- a/src/intel/common

[Mesa-dev] [PATCH 2/2] i965: compute scratch space size correctly for Gen9

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_program.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index 6aa4100..1ae0aa0 100644 --- a/src/mesa

[Mesa-dev] [PATCH 1/2] i965: Program MEDIA_VFE_STATE in a more readable fashion.

From: Kevin Rogovin This patch is purely for readability improvements when programming the MEDIA_VFE_STATE. Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/genX_state_upload.c | 19 +-- 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers

[Mesa-dev] [PATCH 0/2] i965: scratch space fixes (v2)

From: Kevin Rogovin This patch series offers a readability improvement for programming MEDIA_VFE_STATE and fixes a scratch space sizing bug for Gen9. Together with the ASTC5x5 fixes posted before, carchase on GLES works on my SKL GT4. v2: correctly state that first patch is just readability

[Mesa-dev] [PATCH 1/2] i965: correctly program MEDIA_VFE_STATE for compute shading

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/genX_state_upload.c | 19 +-- 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index

[Mesa-dev] [PATCH 0/2] i965: scratch space fixes

From: Kevin Rogovin This patch series fixes 2 issues for scratch space on compute shaders for GEN. Together with the ASTC5x5 fixes posted before, carchase on GLES works on my SKL GT4. Kevin Rogovin (2): i965: correctly program MEDIA_VFE_STATE for compute shading i965: compute scratch space

[Mesa-dev] [PATCH 2/2] i965: compute scratch space size correctly for Gen9

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_program.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index 6aa41009e7..7bfcad9a65 100644

[Mesa-dev] [PATCH 16/16] src/intel/tools: add BatchbufferLogger to meson build system

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- meson_options.txt | 6 src/intel/tools/meson.build | 71 + 2 files changed, 77 insertions(+) diff --git a/meson_options.txt b/meson_options.txt index 39b137cbea..f6690c5e8e 100644

[Mesa-dev] [PATCH 15/16] intel/tools: add command line GEN shader disassembler tool

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/Makefile.tools.am | 21 ++- src/intel/tools/.gitignore| 1 + src/intel/tools/gen_shader_disassembler.c | 213 ++ 3 files changed, 234 insertions(+), 1 deletion(-) create

[Mesa-dev] [PATCH 14/16] intel/tools/BatchbufferLogger (output-json): add json outputter

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/Makefile.tools.am| 6 +- src/intel/tools/.gitignore | 1 + .../tools/i965_batchbuffer_dump_show_json.cpp | 253 + 3 files changed, 259 insertions(+), 1

[Mesa-dev] [PATCH 12/16] intel/tools/BatchbufferLogger (txt-output): example txt dumper

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/Makefile.tools.am | 5 + src/intel/tools/.gitignore | 1 + src/intel/tools/i965_batchbuffer_dump_show.c | 135 +++ 3 files changed, 141 insertions(+) create mode

[Mesa-dev] [PATCH 09/16] intel/compiler: add print_offsets argument to brw_disassemble()

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/compiler/brw_compile_clip.c | 4 +++- src/intel/compiler/brw_compile_sf.c | 4 +++- src/intel/compiler/brw_disasm_info.c | 4 +++- src/intel/compiler/brw_eu.c | 5 +++-- src/intel

[Mesa-dev] [PATCH 08/16] intel/common: add new debug option print_offsets options for dumping assembly

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/common/gen_debug.c | 1 + src/intel/common/gen_debug.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_debug.c index a978f2f581..ecb6be0028 100644 --- a/src/intel/common

[Mesa-dev] [PATCH 13/16] intel/tools/BatchbufferLogger (output-xml): add outputter to XML

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/Makefile.tools.am| 6 +- src/intel/tools/.gitignore | 1 + src/intel/tools/i965_batchbuffer_dump_show_xml.cpp | 217 + 3 files changed, 223 insertions(+), 1

[Mesa-dev] [PATCH 11/16] intel/tools/BatchbufferLogger: install i965_batchbuffer non-driver interface headers

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/Makefile.tools.am | 12 +++ src/intel/tools/.gitignore| 1 + src/intel/tools/i965_batchbuffer_logger_sh.in | 108 ++ 3 files changed, 121 insertions(+) create mode

[Mesa-dev] [PATCH 06/16] intel/tools/disasm: gen_disasm_disassemble to take const void* instead of void*

From: Kevin Rogovin Reviewed-by: Matt Turner Signed-off-by: Kevin Rogovin --- src/intel/tools/disasm.c | 6 +++--- src/intel/tools/gen_disasm.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/intel/tools/disasm.c b/src/intel/tools/disasm.c index 5091579522

[Mesa-dev] [PATCH 03/16] intel/tools: BatchBufferLogger define output file format of tool

From: Kevin Rogovin Define the output format of the BatchbufferLogger. The output is a sequence of blocks where blocks can have member blocks or values. The top level blocks come from the application calling into the BatchBufferLogger when an GL/GLES API call is started and returns. Signed-off

[Mesa-dev] [PATCH 07/16] intel/tools/disasm: add gen_disasm_assembly_length function

From: Kevin Rogovin The length function is needed if one wishes to save GEN binary shaders to file. Signed-off-by: Kevin Rogovin --- src/intel/tools/disasm.c | 7 +++ src/intel/tools/gen_disasm.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/src/intel/tools/disasm.c b/src

[Mesa-dev] [PATCH 01/16] intel/tools: define BatchBufferLogger driver interface

From: Kevin Rogovin Define the driver interface for BatchbufferLogger. The interface assumes that for any -thread- there is only one batchbuffer to which commands are to be added. A driver needs to provide the information on what is the active batchbuffer on a calling thread and also a function

[Mesa-dev] [PATCH 02/16] intel/tools: define BatchbufferLogger application interface

From: Kevin Rogovin Define the application interface to BatchbufferLogger. The BatchbufferLogger needs from the application when a GL/GLES API call is issues and returns. It will use this information to correctly correlate batchbuffer additions to GL/GLES API calls. In addition, because the

[Mesa-dev] [PATCH 00/16] Batchbuffer Logger for Intel GPU (v3)

From: Kevin Rogovin This patch series defines and implements a BatchbufferLogger for Intel GEN. The main purpose of the BatchbufferLogger is to strongly correlate API calls to data added to a batchbuffer. In addition to this function, the BatchbufferLogger also tracks GPU state (respecting HW

[Mesa-dev] [PATCH 05/16] i965: Enable BatchbufferLogger in i965 driver

From: Kevin Rogovin The interface for BatchbufferLogger is that it is active only if it is LD_PRELOAD'ed. Thus, the i965 driver is to use dlsym to see if it is there, and if so fetch the object at intel_screen creation. Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_buf

[Mesa-dev] [PATCH 04/16] i965: assign BindingTableEntryCount of INTERFACE_DESCRIPTOR_DATA

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/genX_state_upload.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index 04a492539a..3643d79231 100644 --- a/src

[Mesa-dev] [PATCH 3/3] i965: if DEBUG_OUT_OF_BOUND_CHK is up, check that noise padding for each bo used in batchbuffer is correct

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index 91a6506..549ea3e 100644

[Mesa-dev] [PATCH 1/3] intel/common:add debug flag for adding and checking padding on BO's

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/common/gen_debug.c | 1 + src/intel/common/gen_debug.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_debug.c index a978f2f..2154b23 100644 --- a/src/intel/common

[Mesa-dev] [PATCH 2/3] i965: add noise padding to buffer object and function to check if noise is correct

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_bufmgr.c | 68 +- src/mesa/drivers/dri/i965/brw_bufmgr.h | 12 ++ 2 files changed, 79 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src

[Mesa-dev] [PATCH 0/3] GEM BO padding to find OOB buffer writes

From: Kevin Rogovin This patch series adds a new debug option to pad each GEM BO allocated by the brw_bufmgr with random noise values which are then checked after each batchbuffer dispatch to the kernel. This can be quite valuable to find diffucult to track down heisenberg style bugs. A

[Mesa-dev] [PATCH 3/5] i965: set ASTC5x5 workaround texture type tracking on texture validate

From: Kevin Rogovin One of the presteps in each draw (and compute) call is to validate the textures. This is the perfect place (since all texture units are looped through) to see if ASTC5x5 and/or textures with an auxilary surface are accessed by the GPU. Signed-off-by: Kevin Rogovin --- src

[Mesa-dev] [PATCH 1/5] i965: define astc5x5 workaround infrastructure

From: Kevin Rogovin Some GEN's have a bug in the sample where if the sampler accesses a texture with an auxialry surface and an ASTC5x5 texture without having the texture cache invalidated between such accesses, then the GPU will hang. This patch defines the infrastructure to implemen

[Mesa-dev] [PATCH 4/5] i965: use ASTC5x5 workaround in brw_draw

From: Kevin Rogovin Perform the ASTC5x5 workaround tasks for drawing; note that the function does not do anything and immediately returns if the bug is not present on the hardware. Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_draw.c | 6 ++ src/mesa/drivers

[Mesa-dev] [PATCH 5/5] i965: use ASTC5x5 workaround in brw_compute

From: Kevin Rogovin Perform the ASTC5x5 workaround tasks for compute; note that the function does not do anything and immediately returns if the bug is not present on the hardware. Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_compute.c | 6 ++ 1 file changed, 6

[Mesa-dev] [PATCH 0/5] i965: ASTC5x5 workaround

From: Kevin Rogovin This patch series implements a needed workaround for Gen9 for ASTC5x5 sampler reads. The crux of the work around is to make sure that the sampler does not read an ASTC5x5 texture and a surface with an auxilary buffer without having a texture cache invalidate between such

[Mesa-dev] [PATCH 2/5] i965: ASTC5x5 workaround logic for blorp

From: Kevin Rogovin Blorp will only read from an ASTC5x5 texture if it copies from such a surface, that can only if an application is fetching such pixels. Because an ASTC5x3 texture can never be a render target, we do not need to worry about blorp reading such surfaces on framebuffer blits, or

[Mesa-dev] [PATCH 16/18] intel/tools/BatchbufferLogger (output-xml): add outputter to XML

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/Makefile.tools.am| 6 +- src/intel/tools/.gitignore | 1 + src/intel/tools/i965_batchbuffer_dump_show_xml.cpp | 217 + 3 files changed, 223 insertions(+), 1

[Mesa-dev] [PATCH 18/18] intel/tools: add command line GEN shader disassembler tool

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/Makefile.tools.am | 21 ++- src/intel/tools/.gitignore| 1 + src/intel/tools/gen_shader_disassembler.c | 221 ++ 3 files changed, 242 insertions(+), 1 deletion(-) create

[Mesa-dev] [PATCH 17/18] intel/tools/BatchbufferLogger (output-json): add json outputter

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/Makefile.tools.am| 6 +- src/intel/tools/.gitignore | 1 + .../tools/i965_batchbuffer_dump_show_json.cpp | 253 + 3 files changed, 259 insertions(+), 1

[Mesa-dev] [PATCH 13/18] intel/tools/BatchbufferLogger: install i965_batchbuffer non-driver interface headers

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/Makefile.tools.am | 4 1 file changed, 4 insertions(+) diff --git a/src/intel/Makefile.tools.am b/src/intel/Makefile.tools.am index 9919b5f241..c308b816f9 100644 --- a/src/intel/Makefile.tools.am +++ b/src/intel

[Mesa-dev] [PATCH 15/18] intel/tools/BatchbufferLogger (txt-output): example txt dumper

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/Makefile.tools.am | 5 ++ src/intel/tools/.gitignore | 1 + src/intel/tools/i965_batchbuffer_dump_show.c | 129 +++ 3 files changed, 135 insertions(+) create mode

[Mesa-dev] [PATCH 08/18] intel/compiler:add function to give option to print offsets into assembly

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/compiler/brw_eu.c | 11 ++- src/intel/compiler/brw_eu.h | 3 +++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c index bc297a21b3..8969ae5bda 100644

[Mesa-dev] [PATCH 07/18] intel/compiler: fix for memmove argument on annotating error

From: Kevin Rogovin Without this fix, disassembling of GEN shaders with GPU commands that the disassembler does not know would result in errors being added to the annotator which would crash when more than one error was added. Signed-off-by: Kevin Rogovin --- src/intel/compiler

[Mesa-dev] [PATCH 09/18] intel/tools/disasm: gen_disasm_disassemble to take const void* instead of void*

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/tools/disasm.c | 6 +++--- src/intel/tools/gen_disasm.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/intel/tools/disasm.c b/src/intel/tools/disasm.c index 251acd313d..27f99e21f9 100644 --- a/src

[Mesa-dev] [PATCH 11/18] intel/tools/disasm: make sure that entire range is disassembled

From: Kevin Rogovin Without this patch, if a shader has errors, the disassembly of the shader often stops after the first opcode that has errors. Signed-off-by: Kevin Rogovin --- src/intel/tools/disasm.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src

[Mesa-dev] [PATCH 14/18] intel/tools/BatchbufferLogger : add shell script for batchbuffer logger

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/Makefile.tools.am | 8 ++ src/intel/tools/.gitignore| 1 + src/intel/tools/i965_batchbuffer_logger_sh.in | 108 ++ 3 files changed, 117 insertions(+) create mode

[Mesa-dev] [PATCH 10/18] intel/tools/disasm: add gen_disasm_assembly_length function

From: Kevin Rogovin The length function is needed if one wishes to save GEN binary shaders to file. Signed-off-by: Kevin Rogovin --- src/intel/tools/disasm.c | 7 +++ src/intel/tools/gen_disasm.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/src/intel/tools/disasm.c b/src

[Mesa-dev] [PATCH 00/18] Batchbuffer Logger for Intel GPU (v2)

From: Kevin Rogovin This patch series defines and implements a BatchbufferLogger for Intel GEN. The main purpose of the BatchbufferLogger is to strongly correlate API calls to data added to a batchbuffer. In addition to this function, the BatchbufferLogger also tracks GPU state (respecting HW

[Mesa-dev] [PATCH 06/18] intel/common/gen_decoder: make useable from C++ source

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/common/gen_decoder.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h index 8b00b6edc2..e3b2457dfd 100644 --- a/src/intel/common/gen_decoder.h +++ b/src

[Mesa-dev] [PATCH 01/18] intel/tools: define BatchBufferLogger driver interface

From: Kevin Rogovin Define the driver interface for BatchbufferLogger. The interface assumes that for any -thread- there is only one batchbuffer to which commands are to be added. A driver needs to provide the information on what is the active batchbuffer on a calling thread and also a function

[Mesa-dev] [PATCH 05/18] i965: Enable BatchbufferLogger in i965 driver

From: Kevin Rogovin The interface for BatchbufferLogger is that it is active only if it is LD_PRELOAD'ed. Thus, the i965 driver is to use dlsym to see if it is there, and if so fetch the object at intel_screen creation. Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_buf

[Mesa-dev] [PATCH 04/18] i965: assign BindingTableEntryCount of INTERFACE_DESCRIPTOR_DATA

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/genX_state_upload.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index 453b8e4add..1474d9a150 100644 --- a/src

[Mesa-dev] [PATCH 02/18] intel/tools: define BatchbufferLogger application interface

From: Kevin Rogovin Define the application interface to BatchbufferLogger. The BatchbufferLogger needs from the application when a GL/GLES API call is issues and returns. It will use this information to correctly correlate batchbuffer additions to GL/GLES API calls. In addition, because the

[Mesa-dev] [PATCH 03/18] intel/tools: BatchBufferLogger define output file format of tool

From: Kevin Rogovin Define the output format of the BatchbufferLogger. The output is a sequence of blocks where blocks can have member blocks or values. The top level blocks come from the application calling into the BatchBufferLogger when an GL/GLES API call is started and returns. Signed-off

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