From: Kevin Rogovin <kevin.rogo...@intel.com> This patch series implements a needed workaround for Gen9 for ASTC5x5 sampler reads. The crux of the work around is to make sure that the sampler does not read an ASTC5x5 texture and a surface with an auxilary buffer without having a texture cache invalidate between such accesses.
Kevin Rogovin (5): i965: define astc5x5 workaround infrastructure i965: ASTC5x5 workaround logic for blorp i965: set ASTC5x5 workaround texture type tracking on texture validate i965: use ASTC5x5 workaround in brw_draw i965: use ASTC5x5 workaround in brw_compute src/mesa/drivers/dri/i965/brw_compute.c | 6 +++ src/mesa/drivers/dri/i965/brw_context.c | 63 ++++++++++++++++++++++++ src/mesa/drivers/dri/i965/brw_context.h | 23 +++++++++ src/mesa/drivers/dri/i965/brw_draw.c | 6 +++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 ++ src/mesa/drivers/dri/i965/genX_blorp_exec.c | 5 ++ src/mesa/drivers/dri/i965/intel_batchbuffer.c | 1 + src/mesa/drivers/dri/i965/intel_tex_image.c | 16 ++++-- src/mesa/drivers/dri/i965/intel_tex_validate.c | 13 +++++ 9 files changed, 134 insertions(+), 4 deletions(-) -- 2.14.2 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
