Hi Emil,
On Monday, 17 June 2019 19:35:10 CEST Emil Velikov wrote:
> On 2019/06/06, mathias.froehl...@gmx.net wrote:
> > From: Mathias Fröhlich
> >
> > Align classic swrast with galliums software renderer with respect
> > to front buffer creation.
> > In case of front buffers swrast uses the __
On Mon, Jun 17, 2019 at 12:42 PM Boris Brezillon <
boris.brezil...@collabora.com> wrote:
> On Mon, 17 Jun 2019 10:53:47 -0500
> Jason Ekstrand wrote:
>
> > On Mon, Jun 17, 2019 at 5:49 AM Boris Brezillon <
> > boris.brezil...@collabora.com> wrote:
> >
> > > The V3D driver has an open-coded soluti
On Mon, Jun 17, 2019 at 12:03 PM Boris Brezillon <
boris.brezil...@collabora.com> wrote:
> On Mon, 17 Jun 2019 10:54:20 -0500
> Jason Ekstrand wrote:
>
> > Why do you need to call it in a loop?
>
> Well, I need to call it at least twice (first pass to lower TEX(RECT)
> into TXS(LOD)+TEX(2D) and t
https://bugs.freedesktop.org/show_bug.cgi?id=110884
--- Comment #9 from Caio Marcelo de Oliveira Filho ---
Marcos, could you test master again?
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https://bugs.freedesktop.org/show_bug.cgi?id=110884
--- Comment #8 from Caio Marcelo de Oliveira Filho ---
That MR landed.
Patch that fix the issue here is
commit 397d1a18ef78ddf46efda44d6783105f9fd87f7e
Author: Caio Marcelo de Oliveira Filho
Date: Wed Jun 12 15:32:30 2019 -0700
llvmpip
On 6/17/19 10:09 PM, Bas Nieuwenhuizen wrote:
On Mon, Jun 17, 2019 at 10:06 PM Samuel Pitoiset
wrote:
On 6/17/19 10:01 PM, Bas Nieuwenhuizen wrote:
On Mon, Jun 17, 2019 at 12:41 PM Samuel Pitoiset
wrote:
And some cleanups.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_fa
On Mon, Jun 17, 2019 at 10:06 PM Samuel Pitoiset
wrote:
>
>
> On 6/17/19 10:01 PM, Bas Nieuwenhuizen wrote:
> > On Mon, Jun 17, 2019 at 12:41 PM Samuel Pitoiset
> > wrote:
> >> And some cleanups.
> >>
> >> Signed-off-by: Samuel Pitoiset
> >> ---
> >> src/amd/vulkan/radv_meta_fast_clear.c | 228
On 6/17/19 10:01 PM, Bas Nieuwenhuizen wrote:
On Mon, Jun 17, 2019 at 12:41 PM Samuel Pitoiset
wrote:
And some cleanups.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_fast_clear.c | 228 +++---
1 file changed, 129 insertions(+), 99 deletions(-)
diff --gi
with that fixed, r-b
On Mon, Jun 17, 2019 at 12:51 PM Samuel Pitoiset
wrote:
>
>
> On 6/17/19 12:50 PM, Bas Nieuwenhuizen wrote:
> > On Mon, Jun 17, 2019 at 12:40 PM Samuel Pitoiset
> > wrote:
> >> Signed-off-by: Samuel Pitoiset
> >> ---
> >> src/amd/vulkan/radv_image.c | 8
> >> 1
r-b
On Mon, Jun 17, 2019 at 12:41 PM Samuel Pitoiset
wrote:
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_meta_fast_clear.c | 106 +-
> 1 file changed, 54 insertions(+), 52 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_meta_fast_clear.c
> b/src/amd/
On Mon, Jun 17, 2019 at 12:41 PM Samuel Pitoiset
wrote:
>
> And some cleanups.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_meta_fast_clear.c | 228 +++---
> 1 file changed, 129 insertions(+), 99 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_meta_fast_cl
On Mon, Jun 17, 2019 at 9:19 PM Marek Olšák wrote:
>
> On Sat, Jun 15, 2019 at 5:51 PM Bas Nieuwenhuizen
> wrote:
>>
>> I'm not quite sure why the dimension changes are needed for radeonsi,
>> but for both polarisd and vega the compressed texture CTS tests pass
>> on RADV.
>
>
> Addrlib no longe
Support got removed in the new addrlib update.
---
src/amd/vulkan/radv_formats.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index e61d793e7f2..e8470a1622e 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_
On Sat, Jun 15, 2019 at 5:51 PM Bas Nieuwenhuizen
wrote:
> I'm not quite sure why the dimension changes are needed for radeonsi,
> but for both polarisd and vega the compressed texture CTS tests pass
> on RADV.
>
Addrlib no longer supports linear compressed formats, so 64-bit or 128-bit
integer
Reviewed-by: Marek Olšák
Marek
On Mon, Jun 17, 2019 at 2:47 PM Haehnle, Nicolai
wrote:
> The following hunk needs to be added:
>
> > @@ -503,7 +521,9 @@ static bool resolve_symbol(const struct
> ac_rtld_upload_info *u,
> >unsigned part_idx, const Elf64_Sym *sym,
> >
https://bugs.freedesktop.org/show_bug.cgi?id=110673
--- Comment #5 from Boyuan Zhang ---
Hi Zhoulei,
I fixed the second issue you reported (cbr/vbr corruption for hevc encoding).
Please give a try using this patch:
https://lists.freedesktop.org/archives/mesa-dev/2019-June/220304.html
Thanks,
B
From: Boyuan Zhang
Set cu_qp_delta_enable_flag on when rate control is enabled, and it
off when no rate control is disabled (constant qp).
Signed-off-by: Boyuan Zhang
---
src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/
From: Boyuan Zhang
Set cu_qp_delta_enable_flag on when rate control is enabled, and it
off when no rate control is disabled (constant qp).
Signed-off-by: Boyuan Zhang
---
src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/
The following hunk needs to be added:
> @@ -503,7 +521,9 @@ static bool resolve_symbol(const struct
> ac_rtld_upload_info *u,
>unsigned part_idx, const Elf64_Sym *sym,
>const char *name, uint64_t *value)
> {
> - if (sym->st_shndx == S
Enable nir_opt_vectorize.
Signed-off-by: Alyssa Rosenzweig
---
src/gallium/drivers/panfrost/midgard/midgard_compile.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
b/src/gallium/drivers/panfrost/midgard/midgard_compi
From: Connor Abbott
This effectively does the opposite of nir_lower_alus_to_scalar, trying
to combine per-component ALU operations with the same sources but
different swizzles into one larger ALU operation. It uses a similar
model as CSE, where we do a depth-first approach and keep around a hash
On Mon, Jun 17, 2019 at 6:37 AM wrote:
>
> From: Mathias Fröhlich
>
>
> Emil,
>
> that one probably matches your original intent then.
>
> please review
> Thanks
>
> Mathias
>
>
> Do not offer a hardware drm backed egl device if no render node
> is available. The current implementation will fail
On Mon, 17 Jun 2019 10:53:47 -0500
Jason Ekstrand wrote:
> On Mon, Jun 17, 2019 at 5:49 AM Boris Brezillon <
> boris.brezil...@collabora.com> wrote:
>
> > The V3D driver has an open-coded solution for this, and we need the
> > same thing for Panfrost, so let's add a generic way to lower TXS(LO
> Note that I don't have write permissions to the mesa tree, so I'll need
> someone to apply the patch once it's considered ready to be merged.
I can apply v2 once it has the necessary R-b's (Jason's will do, of
course :) )
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On 2019/06/06, mathias.froehl...@gmx.net wrote:
> From: Mathias Fröhlich
>
> Align classic swrast with galliums software renderer with respect
> to front buffer creation.
> In case of front buffers swrast uses the __DRI_SWRAST_LOADER extensions
> getImage/putImage callbacks to keep the front buff
On 2019/06/17, mathias.froehl...@gmx.net wrote:
> From: Mathias Fröhlich
>
>
> Emil,
>
> that one probably matches your original intent then.
>
> please review
> Thanks
>
> Mathias
>
>
> Do not offer a hardware drm backed egl device if no render node
> is available. The current implementati
On Mon, 17 Jun 2019 07:05:24 -0700
Alyssa Rosenzweig wrote:
> > +/*
> > + * Note: the first call is here to lower RECT and TXP, the second
> > one
> > + * to lower the TXS(lod) instructions generated by the RECT
> > lowering
> > + * done in the first pass.
> > +
On Mon, 17 Jun 2019 11:00:22 -0500
Jason Ekstrand wrote:
> On Mon, Jun 17, 2019 at 5:21 AM Boris Brezillon <
> boris.brezil...@collabora.com> wrote:
>
> > get_texture_size() will create a txs instruction with ->sampler_dim set
> > to the original tex->sampler_dim. The condition to call lower_r
On Mon, 17 Jun 2019 10:54:20 -0500
Jason Ekstrand wrote:
> Why do you need to call it in a loop?
Well, I need to call it at least twice (first pass to lower TEX(RECT)
into TXS(LOD)+TEX(2D) and the second pass to lower TXS(LOD) into
TXS(0)>>LOD) and I thought doing that in a do {} while (progress
On Mon, Jun 17, 2019 at 5:21 AM Boris Brezillon <
boris.brezil...@collabora.com> wrote:
> get_texture_size() will create a txs instruction with ->sampler_dim set
> to the original tex->sampler_dim. The condition to call lower_rect()
> only checks the value of ->sampler_dim and whether lower_rect i
Reviewed-by: Jason Ekstrand
On Mon, Jun 17, 2019 at 5:21 AM Boris Brezillon <
boris.brezil...@collabora.com> wrote:
> The code considers that projector lowering was done even if it's not
> really the case. Change the project_src() prototype to return a bool
> encoding whether projector lowering
Why do you need to call it in a loop?
On Mon, Jun 17, 2019 at 5:21 AM Boris Brezillon <
boris.brezil...@collabora.com> wrote:
> Hello,
>
> I've recently been working on adding a new lowering option to the
> lower_tex() logic and found out that doing
>
> do progress = nir_lower_tex(); whil
On Mon, Jun 17, 2019 at 5:49 AM Boris Brezillon <
boris.brezil...@collabora.com> wrote:
> The V3D driver has an open-coded solution for this, and we need the
> same thing for Panfrost, so let's add a generic way to lower TXS(LOD)
> into max(TXS(0) >> LOD, 1).
>
> Signed-off-by: Boris Brezillon
>
On Mon, 17 Jun 2019 07:09:16 -0700
Alyssa Rosenzweig wrote:
> > No problem, I'll rebase once this work has landed.
>
> I thought it has?
Then it's all good (I'm based on mesa master from today, and just
fetched/rebased 2 minutes ago to make sure I had everything).
>
> > Hm, the list of allo
https://bugs.freedesktop.org/show_bug.cgi?id=110921
Gert Wollny changed:
What|Removed |Added
URL||https://gitlab.freedesktop.
Reviewed-by, thank you!
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> No problem, I'll rebase once this work has landed.
I thought it has?
> Hm, the list of allowed ops is likely to differ (doesn't make sense to
> allow txs instructions when building a midgard tex instruction) so I'm
> not sure it's a good idea to share this switch statement.
Well, I was maybe m
> +/*
> + * Note: the first call is here to lower RECT and TXP, the second one
> + * to lower the TXS(lod) instructions generated by the RECT lowering
> + * done in the first pass.
> + *
> + * FIXME: we should probably have a
> + *
> +
On Mon, 17 Jun 2019 06:56:11 -0700
Alyssa Rosenzweig wrote:
> This conflicts with texture bias/LOD work (in a functional sense, not
> a git sense).
No problem, I'll rebase once this work has landed.
> We can probably reuse the switch from the previous
> function rather than duplicating the op l
Reviewed-by: Alyssa Rosenzweig , thank
you!
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This conflicts with texture bias/LOD work (in a functional sense, not
a git sense). We can probably reuse the switch from the previous
function rather than duplicating the op list :)
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I'm not sure if there is a more idiomatic "NIR" way to express the body
of nir_lower_txs_lod, so let's wait to hear some feedback. In principle,
I think this is a great idea :)
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Reviewed-by, seems like a good idea to have the full set :)
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r-b
On Mon, Jun 17, 2019 at 12:41 PM Samuel Pitoiset
wrote:
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_meta_fast_clear.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/src/amd/vulkan/radv_meta_fast_clear.c
> b/src/amd/vulkan/radv_meta_fast_clear.c
> index 8fba2a
r-b
On Mon, Jun 17, 2019 at 12:41 PM Samuel Pitoiset
wrote:
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 41 ++-
> src/amd/vulkan/radv_meta.h| 3 +-
> src/amd/vulkan/radv_meta_clear.c | 8 --
> src/amd/vulkan/r
r-b
On Mon, Jun 17, 2019 at 12:41 PM Samuel Pitoiset
wrote:
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
> b/src/amd/vulkan/radv_cmd_buffer.c
>
r-b
On Mon, Jun 17, 2019 at 12:41 PM Samuel Pitoiset
wrote:
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 19 ---
> src/amd/vulkan/radv_meta_clear.c | 9 -
> src/amd/vulkan/radv_meta_fast_clear.c | 2 +-
> src/amd/vulkan/radv_p
r-b
On Mon, Jun 17, 2019 at 12:41 PM Samuel Pitoiset
wrote:
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 38 +++-
> src/amd/vulkan/radv_meta_clear.c | 2 +-
> src/amd/vulkan/radv_private.h| 12 +-
> 3 files changed, 39 in
On 6/17/19 12:50 PM, Bas Nieuwenhuizen wrote:
On Mon, Jun 17, 2019 at 12:40 PM Samuel Pitoiset
wrote:
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_image.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv
On Mon, Jun 17, 2019 at 12:40 PM Samuel Pitoiset
wrote:
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_image.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
> index 909145e1e75..d3bbc9e67
Right now the failure happens when building the midgard texture
instruction. Since we're about to add support for texop_txs (texture
size) which is does not involve the creation of a texture instruction,
let's add a instr->op check at the beginning of the emit_tex() function
so we can easily branch
This patch adds support for nir_texop_txs instructions which are needed
to support the OpenGL textureSize() function. This is also needed to
support RECT texture sampling which is currently lowered to 2D sampling +
a TXS() instruction by the nir_lower_tex() helper.
Signed-off-by: Boris Brezillon
The V3D driver has an open-coded solution for this, and we need the
same thing for Panfrost, so let's add a generic way to lower TXS(LOD)
into max(TXS(0) >> LOD, 1).
Signed-off-by: Boris Brezillon
---
src/compiler/nir/nir.h | 6
src/compiler/nir/nir_lower_tex.c | 49 +
We are about to add support for nir_texop_txs which requires adding a
sysval/uniform containing the texture size. Let's change the
emit_sysval_read() prototype to take a nir_instr object instead of
a nir_intrinsic_instr one so we can re-use this function when emitting
a sysval for a txs instruction
We're about to add more sysval types, and panfrost_emit_for_draw()
is big enough, so let's move the sysval upload logic in a separate
function.
We also add one sub-function per sysval type to keep the
panfrost_upload_sysvals() small/readable.
Signed-off-by: Boris Brezillon
---
src/gallium/drive
We already have nir_imm_ivec2() and nir_imm_ivec4(), let's add
nir_imm_ivec3() instead of open-coding the logic.
Signed-off-by: Boris Brezillon
---
src/compiler/nir/nir_builder.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/
Hello,
TXS is needed to support the OpenGL textureSize() function but not only.
TXS instructions are also used by nir_lower_tex() to lower a RECT
texture sampling into a 2D one, which I wanted to have working to test
gallium-hud on panfrost.
Note that I decided to add a new generic lowering step
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 41 ++-
src/amd/vulkan/radv_meta.h| 3 +-
src/amd/vulkan/radv_meta_clear.c | 8 --
src/amd/vulkan/radv_meta_fast_clear.c | 7 +++--
src/amd/vulkan/radv_meta_resolve.c| 24
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index a6b1f767d46..2ca73c5a631 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++
And some cleanups.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_fast_clear.c | 228 +++---
1 file changed, 129 insertions(+), 99 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c
b/src/amd/vulkan/radv_meta_fast_clear.c
index eba0477c405..1e7eb80
Hi,
This series is a prerequisite before enabling DCC for mipmapped color textures.
It basically allocates more metadata space and it adds mipmap support for color
decompressions on graphics and compute.
DCC for mipmaps is still disabled by default but I should be able to
enable it soon for GFX8.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 19 ---
src/amd/vulkan/radv_meta_clear.c | 9 -
src/amd/vulkan/radv_meta_fast_clear.c | 2 +-
src/amd/vulkan/radv_private.h | 12 +++-
4 files changed, 32 insertions(+), 10 de
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 38 +++-
src/amd/vulkan/radv_meta_clear.c | 2 +-
src/amd/vulkan/radv_private.h| 12 +-
3 files changed, 39 insertions(+), 13 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_image.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 909145e1e75..d3bbc9e674b 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_im
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_fast_clear.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c
b/src/amd/vulkan/radv_meta_fast_clear.c
index 8fba2aa4b5c..eba0477c405 100644
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_fast_clear.c | 106 +-
1 file changed, 54 insertions(+), 52 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c
b/src/amd/vulkan/radv_meta_fast_clear.c
index 1e7eb80618f..feeb0a1b7ed 100644
--- a/src
From: Mathias Fröhlich
Emil,
that one probably matches your original intent then.
please review
Thanks
Mathias
Do not offer a hardware drm backed egl device if no render node
is available. The current implementation will fail on this
egl device. On top it issues a warning that is actually m
On Thu, Jun 13, 2019, 3:42 PM Samuel Pitoiset
wrote:
> This allows us to disable the FMASK decompress pass when
> transitioning from CB writes to shader reads.
>
> This will likely be improved and enabled by default in the future.
>
> No CTS regressions on GFX8 but a few number of multisample CTS
get_texture_size() will create a txs instruction with ->sampler_dim set
to the original tex->sampler_dim. The condition to call lower_rect()
only checks the value of ->sampler_dim and whether lower_rect is
requested or not. This leads to an infinite loop when calling
nir_lower_tex() with the same o
Hello,
I've recently been working on adding a new lowering option to the
lower_tex() logic and found out that doing
do progress = nir_lower_tex(); while (progress);
is not working well (nir_lower_tex() keeps returning true and lowering
the same instructions over and over again).
The 2 p
The code considers that projector lowering was done even if it's not
really the case. Change the project_src() prototype to return a bool
encoding whether projector lowering happened or not and update the
progress var accordingly in nir_lower_tex_block().
This prevents an infinite loop when doing:
R-b
On Thu, Jun 13, 2019, 12:40 PM Samuel Pitoiset
wrote:
> This fixes a segfault when forcing DCC decompressions on compute
> because internal meta objects are not created since the on-demand
> stuff.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_meta_fast_clear.c | 8 +++
Can we fix the title?(inherit)
On Thu, Jun 13, 2019, 1:53 PM Samuel Pitoiset
wrote:
> Otherwise fast color/depth clears can't work because they depend
> on the framebuffer.
>
> This fixes the following CTS (when the small hint is disabled):
> - dEQP-VK.geometry.layered.1d_array.secondary_cmd_buf
R-b for the series
On Thu, Jun 13, 2019, 5:14 PM Samuel Pitoiset
wrote:
> Instead of re-computing in the driver. The 3d and cube flags
> are correctly set, so the same values should returned by
> ac_compute_surface().
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_image.c | 45
https://bugs.freedesktop.org/show_bug.cgi?id=110923
--- Comment #2 from Christian Forfang ---
Ah, I didn't realize the mirror I was looking looking at didn't have an
up-to-date radv. Sorry for the noise :)
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https://bugs.freedesktop.org/show_bug.cgi?id=110923
Samuel Pitoiset changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
On 6/16/19 3:55 PM, Matthias Lorenz wrote:
When NDEBUG is defined, the loop is a no-op, so wrap it in #ifndef
to avoid unused variable warnings in release builds.
Fixes: 32e1d85cb699 radv: assert on inline uniform blocks in
radv_CmdPushDescriptorSetKHR()
---
src/amd/vulkan/radv_cmd_buffer.c
When NDEBUG is defined, the loop is a no-op, so wrap it in #ifndef
to avoid unused variable warnings in release builds.
Fixes: 32e1d85cb699 radv: assert on inline uniform blocks in
radv_CmdPushDescriptorSetKHR()
---
src/amd/vulkan/radv_cmd_buffer.c | 2 ++
1 file changed, 2 insertions(+)
diff -
https://bugs.freedesktop.org/show_bug.cgi?id=110921
--- Comment #7 from Gert Wollny ---
This should fix it:
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1108
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