The only solid fill picture type we supported only had 8 bit color
channels. Add a new solid picture type that supports float channels.
Signed-off-by: Thomas Hellstrom
Reviewed-by: Brian Paul
---
src/gallium/state_trackers/xa/xa_composite.c | 106 ++-
src/gallium/state_trackers/
Remove unused and obsolete code for gradients and component-alpha
Support solid source- and mask pictures using a variable number
of samplers in the composite pipeline rather than the fixed number
we used before.
Tested using rendercheck for XA.
Signed-off-by: Thomas Hellstrom
Reviewed-by: Brian
Signed-off-by: Thomas Hellstrom
Reviewed-by: Brian Paul
---
src/gallium/state_trackers/xa/xa_tracker.c| 33 ++-
src/gallium/state_trackers/xa/xa_tracker.h.in | 5 +++
2 files changed, 29 insertions(+), 9 deletions(-)
diff --git a/src/gallium/state_trackers/xa/xa_tracker.c
Bump minor to signal support for new formats and higher precision
solid pictures.
Signed-off-by: Thomas Hellstrom
Reviewed-by: Brian Paul
---
configure.ac | 2 +-
src/gallium/state_trackers/xa/meson.build | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
dif
https://bugs.freedesktop.org/show_bug.cgi?id=108720
Bug ID: 108720
Summary: System crash vulkan cemu
Product: Mesa
Version: git
Hardware: Other
OS: All
Status: NEW
Severity: major
Priority: mediu
On Mon, Nov 12, 2018 at 3:07 PM Eric Anholt wrote:
>
> Matt Turner writes:
>
> > Prior to this patch sizeof(linear_header) was 20 bytes in a
> > non-debug build on 32-bit platforms. We do some pointer arithmetic to
> > calculate the next available location with
> >
> >ptr = (linear_size_chunk
Reviewed-by: Karol Herbst
On Tue, Nov 13, 2018 at 3:51 AM Jason Ekstrand wrote:
>
> On Mon, Nov 12, 2018 at 6:10 PM Karol Herbst wrote:
>>
>> it shouldn't make a difference. This pass lowers load_derefs into
>> whatever we want here. If we handle the system value explicitly
>> "sysval" gets set.
GREAT hint Tim!
Yes, of course.
/home/dieter> gcc --version
gcc (SUSE Linux) 8.2.1 20181025 [gcc-8-branch revision 265488]
So I have to ping SUSE to push the fix, too.
Thanks a lot.
Dieter
Am 12.11.2018 08:28, schrieb Timothy Arceri:
I'm guessing your using GCC 8.2.1 to compile Mesa? There w
On Mon, Nov 12, 2018 at 8:57 PM Timothy Arceri
wrote:
> For example the following type of thing is seen in TCS from
> a number of Vulkan and DXVK games:
>
> vec1 32 ssa_557 = deref_var &oPatch (shader_out float)
> vec1 32 ssa_558 = intrinsic load_deref (ssa_557) ()
> vec1
For example the following type of thing is seen in TCS from
a number of Vulkan and DXVK games:
vec1 32 ssa_557 = deref_var &oPatch (shader_out float)
vec1 32 ssa_558 = intrinsic load_deref (ssa_557) ()
vec1 32 ssa_559 = deref_var &oPatch@42 (shader_out float)
vec1 3
On Mon, Nov 12, 2018 at 6:10 PM Karol Herbst wrote:
> it shouldn't make a difference. This pass lowers load_derefs into
> whatever we want here. If we handle the system value explicitly
> "sysval" gets set. If not, we fetch the op through
> nir_intrinsic_from_system_value and do the load based on
Sorry for not getting back sooner on this one.
I'm leaning towards a NAK on this one. This is just under 300 new lines
of code to work around a possibly over strict piglit test. While the
test is not wrong an implementation is also not required to optimise
away these unused elements.
If this
On November 12, 2018 19:21:42 Timothy Arceri wrote:
For example the following type of thing is seen in TCS from
a number of Vulkan and DXVK games:
vec1 32 ssa_557 = deref_var &oPatch (shader_out float)
vec1 32 ssa_558 = intrinsic load_deref (ssa_557) ()
vec1 32 ssa_559 = deref_var &oPatch@4
Emil Velikov writes:
> On Tue, 30 Oct 2018 at 17:49, Eric Anholt wrote:
>>
>> Emil Velikov writes:
>>
>> > Hi Eric,
>> >
>> > On Thu, 25 Oct 2018 at 17:39, Eric Anholt wrote:
>> >>
>> >> This allows vc4 to initialize on the Adafruit PiTFT 3.5" touchscreen with
>> >> the new tinydrm driver I ju
For example the following type of thing is seen in TCS from
a number of Vulkan and DXVK games:
vec1 32 ssa_557 = deref_var &oPatch (shader_out float)
vec1 32 ssa_558 = intrinsic load_deref (ssa_557) ()
vec1 32 ssa_559 = deref_var &oPatch@42 (shader_out float)
vec1 3
Alyssa Rosenzweig writes:
>> I would love to see this up in src/compiler/nir.
>
> Is there a compelling reason to have it in NIR rather in Gallium, adding
> an extra layer of translation overhead / indirection when coming from
> Gallium blend state? (Mythical future Vulkan support, I guess?)
Exa
Hi Edmondo,
can you test the two attached patches? They re-enable and rework the thread
pinning.
Thanks,
Marek
On Mon, Nov 12, 2018 at 4:31 PM Edmondo Tommasina <
edmondo.tommas...@gmail.com> wrote:
> On Mon, Nov 12, 2018 at 6:43 PM Michel Dänzer wrote:
>
>> On 2018-11-08 6:23 a.m., Marek Olšá
From: Marek Olšák
This is used when glthread is disabled.
Mesa pretty much chases the app thread on the CPU.
The performance is the same as pinning the app thread.
---
src/mesa/state_tracker/st_context.h | 2 ++
src/mesa/state_tracker/st_draw.c| 32 +
2 files ch
From: Marek Olšák
radeonsi has 3 driver threads (glthread, gallium, winsys), other drivers
may have 2 (glthread, gallium), so it makes sense to pin them to a random
CCX and keep that irrespective of the app thread.
---
src/gallium/auxiliary/util/u_helpers.c | 63 --
src/g
it shouldn't make a difference. This pass lowers load_derefs into
whatever we want here. If we handle the system value explicitly
"sysval" gets set. If not, we fetch the op through
nir_intrinsic_from_system_value and do the load based on that. We just
take a different path, but fundamentally we do
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 5acd0922922..6495862e700 100644
--- a/src/me
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_compute.c | 131 +-
src/mesa/drivers/dri/i965/brw_context.h | 2 +
src/mesa/drivers/dri/i965/genX_state_upload.c | 102 ++
3 files changed, 105 insertions(+), 130 deletions(-)
diff --git a/sr
> I would love to see this up in src/compiler/nir.
Is there a compelling reason to have it in NIR rather in Gallium, adding
an extra layer of translation overhead / indirection when coming from
Gallium blend state? (Mythical future Vulkan support, I guess?)
> Also, we should probably convert vc4
On Thu, Nov 8, 2018 at 1:39 AM Timothy Arceri wrote:
> For example the following type of thing is seen in TCS from
> a number of Vulkan and DXVK games:
>
> vec1 32 ssa_557 = deref_var &oPatch (shader_out float)
> vec1 32 ssa_558 = intrinsic load_deref (ssa_557) ()
> vec1 3
Alyssa Rosenzweig writes:
> Some mobile GPUs lack fixed-function hardware for blending, instead
> emulating blending via internal shaders. In particular for us, vc4 lacks
> most of the fragment pipeline, implementing blending in the epilogue of
> the fragment shader. Newer Malis supported by Panf
I think we still want to skip the lowering of SYSTEM_VALUE_LOCAL_GROUP_SIZE
when that flag is set. I think this works, but we'll end up deleting one
load_local_group_size intrinsic and replacing it with another which is
pointless.
--Jason
On Mon, Nov 12, 2018 at 4:02 PM Plamena Manolova <
plamen
Matt Turner writes:
> Prior to this patch sizeof(linear_header) was 20 bytes in a
> non-debug build on 32-bit platforms. We do some pointer arithmetic to
> calculate the next available location with
>
>ptr = (linear_size_chunk *)((char *)&latest[1] + latest->offset);
>
> in linear_alloc_child
On Mon, Nov 12, 2018 at 10:46 PM Connor Abbott wrote:
>
> On Mon, Nov 12, 2018 at 9:34 PM Bas Nieuwenhuizen
> wrote:
> >
> > On Mon, Nov 12, 2018 at 5:55 PM Samuel Pitoiset
> > wrote:
> > >
> > > This allows to fast clear the depth part (or the stencil part)
> > > of a depth+stencil surface when
If the local work group size is variable it won't be available
at compile time so we can't lower it in nir_lower_system_values().
Signed-off-by: Plamena Manolova
---
src/compiler/nir/nir_lower_system_values.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff -
If the local work group size is variable it won't be available
at compile time so we can't lower it in nir_lower_system_values().
Signed-off-by: Plamena Manolova
---
src/compiler/nir/nir_lower_system_values.c | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff
These force the index to be used in the instruction so we don't need the
workaround.
Totals:
SGPRS: 1321642 -> 1321802 (0.01 %)
VGPRS: 943664 -> 943788 (0.01 %)
Spilled SGPRs: 28468 -> 28480 (0.04 %)
Spilled VGPRs: 88 -> 89 (1.14 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 80 -> 80 (0.0
On Mon, Nov 12, 2018 at 9:34 PM Bas Nieuwenhuizen
wrote:
>
> On Mon, Nov 12, 2018 at 5:55 PM Samuel Pitoiset
> wrote:
> >
> > This allows to fast clear the depth part (or the stencil part)
> > of a depth+stencil surface when HTILE is enabled. I didn't test
> > on GFX8, so it's disabled currently.
Kenneth Graunke writes:
> The way nir_lower_clip_vs() works with store_output intrinsics makes a
> ton of assumptions about the driver_location field.
>
> In i965, I'd rather do this lowering early and work with variables.
> ir3 and vc4 could probably do that as well, but I'm not sure exactly
> w
On Mon, Nov 12, 2018 at 6:43 PM Michel Dänzer wrote:
> On 2018-11-08 6:23 a.m., Marek Olšák wrote:
> > Thanks a lot man. I'll reconsider this depending on the results I
> receive.
> >
> > I may also just pin the Mesa threads and keep the app thread intact. It
> > should perform OK with glthread,
The debug code is all asserts, so protect it with the same thing that
controls assert.
---
src/util/ralloc.c | 18 --
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/src/util/ralloc.c b/src/util/ralloc.c
index 5d77f75ee85..745b4cf1226 100644
--- a/src/util/ralloc.c
+
Prior to this patch sizeof(linear_header) was 20 bytes in a
non-debug build on 32-bit platforms. We do some pointer arithmetic to
calculate the next available location with
ptr = (linear_size_chunk *)((char *)&latest[1] + latest->offset);
in linear_alloc_child(). The &latest[1] adds 20 bytes,
Yes, I have a better plan, but I don't know if it will work.
Marek
On Mon, Nov 12, 2018 at 4:19 PM Axel Davy wrote:
> Is there any replacement plan with a new feature ?
>
> Axel
>
> On 12/11/2018 21:45, Marek Olšák wrote:
> > From: Marek Olšák
> >
> > This implementation can have massive drawb
Thanks, pushed.
Marek
On Mon, Nov 12, 2018 at 4:14 PM Edmondo Tommasina <
edmondo.tommas...@gmail.com> wrote:
>
> Patch is:
> Reviewed-by: Edmondo Tommasina
>
>
> On Mon, Nov 12, 2018 at 9:45 PM Marek Olšák wrote:
>
>> From: Marek Olšák
>>
>> This implementation can have massive drawbacks.
>>
Is there any replacement plan with a new feature ?
Axel
On 12/11/2018 21:45, Marek Olšák wrote:
From: Marek Olšák
This implementation can have massive drawbacks.
Cc: 18.3
---
src/mesa/state_tracker/st_manager.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/src/mesa/state_tr
Patch is:
Reviewed-by: Edmondo Tommasina
On Mon, Nov 12, 2018 at 9:45 PM Marek Olšák wrote:
> From: Marek Olšák
>
> This implementation can have massive drawbacks.
>
> Cc: 18.3
> ---
> src/mesa/state_tracker/st_manager.c | 9 -
> 1 file changed, 9 deletions(-)
>
> diff --git a/src/m
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_pipeline.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index f999383018..a126c03607 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_
From: Marek Olšák
This implementation can have massive drawbacks.
Cc: 18.3
---
src/mesa/state_tracker/st_manager.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/src/mesa/state_tracker/st_manager.c
b/src/mesa/state_tracker/st_manager.c
index 690d5bc2313..076ad42646d 100644
--- a/
On Mon, Nov 12, 2018 at 5:55 PM Samuel Pitoiset
wrote:
>
> This allows to fast clear the depth part (or the stencil part)
> of a depth+stencil surface when HTILE is enabled. I didn't test
> on GFX8, so it's disabled currently.
>
> This gives a very nice boost, for example when clearing the depth
>
Am Mo., 12. Nov. 2018 um 19:17 Uhr schrieb Jonathan Marek :
>
> lowers ceil(x) as -floor(-x)
>
> Signed-off-by: Jonathan Marek
Reviewed-by: Christian Gmeiner
> ---
> src/compiler/nir/nir.h| 3 +++
> src/compiler/nir/nir_opt_algebraic.py | 1 +
> 2 files changed, 4 insertions(+)
Reviewed-by: Jason Ekstrand
On Mon, Nov 12, 2018 at 12:17 PM Jonathan Marek wrote:
> lowers ceil(x) as -floor(-x)
>
> Signed-off-by: Jonathan Marek
> ---
> src/compiler/nir/nir.h| 3 +++
> src/compiler/nir/nir_opt_algebraic.py | 1 +
> 2 files changed, 4 insertions(+)
>
> diff
On Mon, Nov 12, 2018 at 1:29 PM Christian Gmeiner <
christian.gmei...@gmail.com> wrote:
> Hi Jason
>
> Am Sa., 1. Sep. 2018 um 21:23 Uhr schrieb Jason Ekstrand <
> ja...@jlekstrand.net>:
> >
> > I don't think either of these work for negative numbers
> >
>
> I would like to land this patch - can y
In general, you're not supposed to mess around with the precision of fma...
What we do in the Intel drivers is to leave fma split, apply operations,
and then we have a special mul+add fusion pass we run at the end. Leaving
them split allows for exactly this kind of optimization without mixing up
t
Hi Jason
Am Sa., 1. Sep. 2018 um 21:23 Uhr schrieb Jason Ekstrand :
>
> I don't think either of these work for negative numbers
>
I would like to land this patch - can you provide some details why
this does not work for
negative numbers?
> On September 1, 2018 14:16:11 Christian Gmeiner
> wrote
Two parts:
1. for intructions that have a BOOL source, insert b2f to so that the
backend can identify the source as a BOOL and perform the conversion from
NIR_TRUE/NIR_FALSE
2. add missing type conversions (out_type is always GLSL_TYPE_FLOAT, so we
are missing some conversion instructions): float t
This works by moving the fadd up across the ffma operations, so that it
can eventually can be combined with a fmul. I'm not sure it works in all
cases, but it works in all the common cases.
Example:
matrix * vec4(coord, 1.0)
is compiled as:
fmul, ffma, ffma, fadd
and with this patch:
f
lowers ceil(x) as -floor(-x)
Signed-off-by: Jonathan Marek
---
src/compiler/nir/nir.h| 3 +++
src/compiler/nir/nir_opt_algebraic.py | 1 +
2 files changed, 4 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index dc3c729dee..f9b32a5daf 100644
--- a/src/
Quoting Eric Engestrom (2018-11-12 09:47:22)
> On Monday, 2018-11-12 16:56:32 +, Emil Velikov wrote:
> > On Mon, 12 Nov 2018 at 14:24, Eric Engestrom
> > wrote:
> > >
> > > These files are close to 4 years out of date; a lot's changed since.
> > > Let's just check in a recently-regenerated ve
On November 12, 2018 08:25:50 "Manolova, Plamena"
wrote:
Hi Jason,
Thank you so much for reviewing! In my initial series for
ARB_compute_variable_group_size
(https://patchwork.freedesktop.org/patch/228130) from which this is
extracted, I moved
lowering these variables to brw_nir_lower_cs_intri
https://bugs.freedesktop.org/show_bug.cgi?id=105328
--- Comment #8 from Emil Velikov ---
Matt has noticed that this is causing problems on Gentoo
https://bugs.gentoo.org/660594
Although it's related to building gst the problem is the same. The gst check
was introduced in 2017 with
https://cgit.f
On Monday, 2018-11-12 16:56:32 +, Emil Velikov wrote:
> On Mon, 12 Nov 2018 at 14:24, Eric Engestrom wrote:
> >
> > These files are close to 4 years out of date; a lot's changed since.
> > Let's just check in a recently-regenerated version.
> >
> Worth removing them from git and letting the bu
On 2018-11-08 6:23 a.m., Marek Olšák wrote:
> Thanks a lot man. I'll reconsider this depending on the results I receive.
>
> I may also just pin the Mesa threads and keep the app thread intact. It
> should perform OK with glthread, but not without glthread.
>
> Another option is to have the galli
Quoting Erik Faye-Lund (2018-11-12 04:51:47)
> On Fri, 2018-11-09 at 10:40 -0800, Dylan Baker wrote:
> > Which has the same behavior.
>
> Does it? I'm not so sure... IROUND_POS seems to round to nearest
> integer depending on the FPU rounding mode, _mesa_roundevenf rounds to
> the nearest *even* v
Quoting Eric Engestrom (2018-11-11 10:39:16)
> On Thursday, 2018-10-11 16:36:15 +0100, Eric Engestrom wrote:
> > Those empty variables in the !wayland case are useless and running that
> > meson.build with them breaks the build:
> >
> > [287/850] Generating wayland-drm-client-protocol.h with a c
On Mon, 12 Nov 2018 at 14:24, Eric Engestrom wrote:
>
> These files are close to 4 years out of date; a lot's changed since.
> Let's just check in a recently-regenerated version.
>
Worth removing them from git and letting the build regenerate them as needed?
Either way, the patch is
Acked-by: Emi
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_clear.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index a44baefd3a..47030549a5 100644
--- a/src/amd/vulkan/radv_meta_clear.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_clear.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 47030549a5..5beb4cd7be 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_met
This allows to fast clear the depth part (or the stencil part)
of a depth+stencil surface when HTILE is enabled. I didn't test
on GFX8, so it's disabled currently.
This gives a very nice boost, for example when clearing the depth
aspect of a 4096x4096 D32_SFLOAT_S8_UINT image (18x faster).
BEFORE
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_clear.c | 52 +++-
1 file changed, 24 insertions(+), 28 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index c8a7f80d55..43da0c8dfe 100644
--- a/src/amd/vulkan/r
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_clear.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 43da0c8dfe..a44baefd3a 100644
--- a/src/amd/vulkan/radv_meta_cle
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_clear.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 5beb4cd7be..b3128d021d 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b
This is fine with me, Reviewed-by: Dylan Baker
Quoting Eric Engestrom (2018-11-12 06:24:33)
> These files are close to 4 years out of date; a lot's changed since.
> Let's just check in a recently-regenerated version.
>
> Changes generated by running `ninja xmlpool-{pot,update-po,gmo}`.
>
> Cc:
Hello list,
The candidate for the Mesa 18.2.5 is now available. Currently we have:
- 25 queued
- 0 nominated (outstanding)
- and 2 rejected patch
The current queue consists of:
A patch for nine state tracker that fixes several crashes using nine's
thread_submit feature. There are other patche
Move them to IR3_SHADER_DEBUG so we can remove ir3's dependency on
fd_mesa_debug.
Signed-off-by: Rob Clark
---
src/gallium/drivers/freedreno/freedreno_screen.c | 3 +--
src/gallium/drivers/freedreno/freedreno_util.h | 2 +-
src/gallium/drivers/freedreno/ir3/ir3_cmdline.c | 6 +++---
src/ga
Signed-off-by: Rob Clark
---
.../drivers/freedreno/ir3/ir3_compiler_nir.c | 20 +--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index 5d647a6d8a2..445a
Signed-off-by: Rob Clark
---
src/gallium/drivers/freedreno/disasm.h| 19 ---
.../drivers/freedreno/ir3/ir3_compiler_nir.c | 2 +-
.../drivers/freedreno/ir3/ir3_shader.c| 3 ++-
3 files changed, 3 insertions(+), 21 deletions(-)
diff --git a/src/gallium/drivers/f
Signed-off-by: Rob Clark
---
src/gallium/drivers/freedreno/freedreno_util.h | 12
src/gallium/drivers/freedreno/ir3/ir3_nir.c| 4 ++--
2 files changed, 2 insertions(+), 14 deletions(-)
diff --git a/src/gallium/drivers/freedreno/freedreno_util.h
b/src/gallium/drivers/freedreno/
Split the parts that are gallium specific into ir3_gallium so the rest
can move to a common location outside of gallium.
Signed-off-by: Rob Clark
---
.../drivers/freedreno/Makefile.sources| 2 +
src/gallium/drivers/freedreno/a3xx/fd3_emit.h | 2 +-
src/gallium/drivers/freedreno/a4xx/
Only used by ir3, so move it into ir3 to be more self contained.
Signed-off-by: Rob Clark
---
src/gallium/drivers/freedreno/disasm.h| 21 ---
.../drivers/freedreno/freedreno_screen.c | 12 ---
.../drivers/freedreno/ir3/ir3_compiler.c | 13
.
Signed-off-by: Rob Clark
---
.../drivers/freedreno/ir3/ir3_cmdline.c | 33 +++
1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
index bf801953d00..39f6c12c6bc 100
Move (most of) the ir3 compiler to src/freedreno/ir3 so that it can be
re-used by some future vulkan driver. The parts that are gallium
specific have been refactored out and remain in the gallium driver.
Getting the move done now so that it can happen before further
refactoring to support a6xx sp
A bit annoying to have to copy into our own struct. But this is
something the compiler really needs to know, at least on earlier
generations where streamout is implemented in shader.
Signed-off-by: Rob Clark
---
src/gallium/drivers/freedreno/a5xx/fd5_emit.c | 2 +-
.../drivers/freedreno/a5xx/f
Prep work to move drm to a common location.
Slightly hacky, but the softpin debug flag is only temporary.
Signed-off-by: Rob Clark
---
src/gallium/drivers/freedreno/drm/msm_pipe.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/freedreno/dr
So I can drop env2u() helper from freedreno_util.h and get rid of one
small ir3 dependency on gallium/freedreno
Signed-off-by: Rob Clark
---
src/util/debug.c | 12
src/util/debug.h | 2 ++
2 files changed, 14 insertions(+)
diff --git a/src/util/debug.c b/src/util/debug.c
index 98b
Clean up some of the low-hanging-fruit usages of freedreno_util.h
Signed-off-by: Rob Clark
---
.../drivers/freedreno/ir3/disasm-a3xx.c| 7 ++-
src/gallium/drivers/freedreno/ir3/instr-a3xx.h | 3 +++
src/gallium/drivers/freedreno/ir3/ir3.c| 3 ++-
src/gallium/drivers/freedr
Just massive search/replace for the most part.
Step towards removing ir3 dependency on disasm.h which is shared by
a2xx. One step closer to being able to move ir3 out of gallium.
Signed-off-by: Rob Clark
---
.../drivers/freedreno/a2xx/disasm-a2xx.c | 10 ++---
.../drivers/freedreno/a2xx/f
Moves drm and the ir3 compiler to src/freedreno so it can be eventually
re-used by vulkan driver.
I mostly just wanted to get the splitup and move of ir3 out of the way
now before I embark on some ir3 refactoring to handle some of the
instructions that use a different encoding on a6xx+ vs earlier
So that we can re-use at least parts of it for vulkan driver, and so
that we can move ir3 to a common location (which uses fd_bo to allocate
storage for shaders)
Signed-off-by: Rob Clark
---
configure.ac | 2 +
src/Makefile.am | 4
On Mon, 12 Nov 2018 at 11:34, Gert Wollny wrote:
>
> From: Gert Wollny
>
> Transform feedback objects may hold a pointer to a shader program, and
> at least in Gallium, this must be a valid pointer until
> ctx->Driver.EndTransformFeedback in glEndTransformFeedback has been called
> - which is con
From: Gustavo Padovan
Following the support for fences on the virtio driver add support
for native fence on virgl. This was somewhat based on the freedeno one.
Signed-off-by: Gustavo Padovan
Signed-off-by: Robert Foss
---
Retransmission: Missed CC-ing mesa-dev
Linux virtgpu fences branch:
ht
Hi Jason,
Thank you so much for reviewing! In my initial series for
ARB_compute_variable_group_size
(https://patchwork.freedesktop.org/patch/228130) from which this is
extracted, I moved
lowering these variables to brw_nir_lower_cs_intrinsics and did what you're
suggesting i.e.
I used the load_loca
These files are close to 4 years out of date; a lot's changed since.
Let's just check in a recently-regenerated version.
Changes generated by running `ninja xmlpool-{pot,update-po,gmo}`.
Cc: Dylan Baker
Signed-off-by: Eric Engestrom
---
src/util/xmlpool/ca.po | 178
On Sun, 11 Nov 2018 at 18:39, Eric Engestrom wrote:
>
> On Thursday, 2018-10-11 16:36:15 +0100, Eric Engestrom wrote:
> > Those empty variables in the !wayland case are useless and running that
> > meson.build with them breaks the build:
> >
> > [287/850] Generating wayland-drm-client-protocol.h
On Wed, 31 Oct 2018 at 16:51, Emil Velikov wrote:
>
> On Wed, 31 Oct 2018 at 14:54, Eric Engestrom wrote:
> >
> > Cc: Emil Velikov
> > Signed-off-by: Eric Engestrom
>
> Acked-by: Emil Velikov
>
Should be made it clearer - the ack is for the whole series.
HTH
Emil
_
On Fri, Nov 9, 2018 at 3:19 PM Eric Engestrom
wrote:
> On Tuesday, 2018-09-11 15:42:06 +0300, asimiklit.w...@gmail.com wrote:
> > From: Andrii Simiklit
> >
> > 1. brw_blorp.c:1502:4: warning:
> > ‘num_layers’ may be used uninitialized in this function
> > 2. brw_blorp.c:1502:4: warning:
> >
On Fri, 2018-11-09 at 10:40 -0800, Dylan Baker wrote:
> Which has the same behavior.
Does it? I'm not so sure... IROUND_POS seems to round to nearest
integer depending on the FPU rounding mode, _mesa_roundevenf rounds to
the nearest *even* value regardless of the FPU rounding mode, no?
I'm not su
Reviewed-by: Toni Lönnberg
On Fri, Nov 09, 2018 at 04:49:10PM +, Lionel Landwerlin wrote:
> Use this value to limit reading the ring buffer.
>
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/tools/aubinator.c | 4 +++-
> src/intel/tools/aubinator_viewer.cpp | 3 ++-
> 2 files
From: Gert Wollny
Transform feedback objects may hold a pointer to a shader program, and
at least in Gallium, this must be a valid pointer until
ctx->Driver.EndTransformFeedback in glEndTransformFeedback has been called
- which is conform with the spec that any program that is part of a
current r
https://bugs.freedesktop.org/show_bug.cgi?id=108713
--- Comment #1 from Gert Wollny ---
I'll send a patch shortly.
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m
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index ee5373950f..1f22fda7c5 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src
On Fri, Nov 9, 2018 at 2:45 PM Eric Engestrom
wrote:
> On Tuesday, 2018-09-11 15:42:04 +0300, asimiklit.w...@gmail.com wrote:
> > From: Andrii Simiklit
> >
> > 1. tools/i965_disasm.c:58:4: warning:
> > ignoring return value of ‘fread’,
> > declared with attribute warn_unused_result
> >
https://bugs.freedesktop.org/show_bug.cgi?id=108713
Bug ID: 108713
Summary: Gallium: use after free with transform feedback
Product: Mesa
Version: git
Hardware: Other
OS: All
Status: NEW
Severity: normal
Reviewed-by: Bas Nieuwenhuizen
On Mon, Nov 12, 2018 at 9:44 AM Samuel Pitoiset
wrote:
>
> Ported from RadeonSI.
>
> v2: - use the current subpass instead of the whole fb
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 21 +
> src/amd/vulkan/si_c
Ported from RadeonSI.
v2: - use the current subpass instead of the whole fb
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 21 +
src/amd/vulkan/si_cmd_buffer.c | 3 ---
2 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/r
Not sure I agree this is a cleanup.
The code here is independent of hardware, while the initialization of
tess_offchip_block_dw_size in radv_device.c has the specific hardware
this applies to.
We add unnecessary asserts here and I'd argue the hardware bug should
be explained when tess_offchip_blo
Reviewed-by: Bas Nieuwenhuizen
On Thu, Nov 8, 2018 at 1:58 PM Samuel Pitoiset
wrote:
>
> Only needed when the pipeline actually uses tessellation. I don't
> think that changes anything, except improving readability.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_pipeline.c | 11
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