[Mesa-dev] [Bug 108263] glGetTexImage with PBO is not accelerated on Gallium

2018-10-07 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=108263 soredake changed: What|Removed |Added CC||fds...@krutt.org -- You are receiving this

Re: [Mesa-dev] [PATCH 0/3] sse4 patches

2018-10-07 Thread Kenneth Graunke
On Monday, September 24, 2018 4:19:36 AM PDT Tapani Pälli wrote: > Hi; > > Here's another try to inline sse41 code and get rid of gtt maps > in intel_miptree_map (revert 58fb613a519). To be able to safely > utilize sse41 we separate sse41 functionality as a library and > then choose run time if

Re: [Mesa-dev] [PATCH 08/11] freedreno: a2xx: split large draws on a20x

2018-10-07 Thread Ilia Mirkin
See my feedback from your earlier submission for how to make this work on more than triangles. Seems easy enough to just do it. https://patchwork.freedesktop.org/patch/250192/ On Mon, Oct 8, 2018 at 12:07 AM Jonathan Marek wrote: > > a20x can only draw 65535 vertices at once. this fix only applie

[Mesa-dev] [PATCH 09/11] freedreno: a2xx: set PA_SC_VIZ_QUERY register

2018-10-07 Thread Jonathan Marek
on a20x the GPU will hang if this register is zero Signed-off-by: Jonathan Marek --- src/gallium/drivers/freedreno/a2xx/fd2_emit.c | 4 1 file changed, 4 insertions(+) diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_emit.c b/src/gallium/drivers/freedreno/a2xx/fd2_emit.c index 90da6a21

[Mesa-dev] [PATCH 10/11] freedreno: a2xx: start max_reg at -1

2018-10-07 Thread Jonathan Marek
on a220 it makes a difference if the max register # is -1 or 0 Signed-off-by: Jonathan Marek --- src/gallium/drivers/freedreno/a2xx/ir-a2xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/freedreno/a2xx/ir-a2xx.c b/src/gallium/drivers/freedreno/a2xx

[Mesa-dev] [PATCH 07/11] freedreno: a2xx: a20x hw binning

2018-10-07 Thread Jonathan Marek
adds all the required logic for a20x hw binning to work Signed-off-by: Jonathan Marek --- src/gallium/drivers/freedreno/a2xx/fd2_draw.c | 95 src/gallium/drivers/freedreno/a2xx/fd2_emit.c | 10 +- src/gallium/drivers/freedreno/a2xx/fd2_emit.h | 3 +- src/gallium/drivers/free

[Mesa-dev] [PATCH 11/11] a2xx: Compute depth base in gmem correctly

2018-10-07 Thread Jonathan Marek
From: Marek Vasut This fixes "a2xx: Compute depth base in gmem consistently" by using the already present zsbuf and cbuf bases rather than incorrect hand crafted calculation. Without this patch, the following assertion triggers ie. with Qt5 on system with 480x272 display: appliation: ../../../

[Mesa-dev] [PATCH 02/11] freedreno: implement different pipe configuration for a20x

2018-10-07 Thread Jonathan Marek
this also adds a num_vsc_pipe which represents the number of pipes to use: this value is useful because more pipes has a higher cost (on a20x) Signed-off-by: Jonathan Marek --- .../drivers/freedreno/freedreno_gmem.c| 29 ++- .../drivers/freedreno/freedreno_gmem.h|

[Mesa-dev] [PATCH 08/11] freedreno: a2xx: split large draws on a20x

2018-10-07 Thread Jonathan Marek
a20x can only draw 65535 vertices at once. this fix only applies to triangles. Signed-off-by: Jonathan Marek --- src/gallium/drivers/freedreno/a2xx/fd2_draw.c | 30 +-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_draw.c b

[Mesa-dev] [PATCH 06/11] freedreno: a2xx: add fragcoord

2018-10-07 Thread Jonathan Marek
emulated fragcoord. a2xx has *some* hw support but it is not practical Signed-off-by: Jonathan Marek --- .../drivers/freedreno/a2xx/fd2_compiler.c| 16 1 file changed, 16 insertions(+) diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c b/src/gallium/drivers

[Mesa-dev] [PATCH 04/11] freedreno: a2xx: map tgsi ids to ir2 ids

2018-10-07 Thread Jonathan Marek
this is for a2xx specific semantics (vertex id) and a basic SSA form Signed-off-by: Jonathan Marek --- .../drivers/freedreno/a2xx/fd2_compiler.c | 54 +-- src/gallium/drivers/freedreno/a2xx/ir-a2xx.c | 45 ++-- src/gallium/drivers/freedreno/a2xx/ir-a2xx.h | 9 +

[Mesa-dev] [PATCH 05/11] freedreno: a2xx: implement a20x binning shader

2018-10-07 Thread Jonathan Marek
writes to position export are mapped to a temp reg, code inserted at the end of vertex shaders to export the position and compute the memory exports for hw binning on a20x. C64 is the offset in the binning data, C65/C66 are viewport parameters, C67+i/C68+i are binning view parameters. C3+i is the b

[Mesa-dev] [PATCH 03/11] freedreno: add a20x ids

2018-10-07 Thread Jonathan Marek
the two a20x GPUs tested are a200 in the imx51 and the imx53 (not a205). the 201 id is used for the imx51 (it only has 128kb gmem as opposed to the typical 256kb for a200) Signed-off-by: Jonathan Marek --- src/gallium/drivers/freedreno/freedreno_screen.c | 2 ++ 1 file changed, 2 insertions(+)

[Mesa-dev] [PATCH 01/11] freedreno: implement the USE_VISIBILITY case for a20x in fd_draw

2018-10-07 Thread Jonathan Marek
this introduces some tracking of the number of vertices drawn in the current batch: the draw command needs an offset to the start of the binning data Signed-off-by: Jonathan Marek --- .../drivers/freedreno/adreno_pm4.xml.h| 7 + .../drivers/freedreno/freedreno_batch.c | 1 +

[Mesa-dev] [PATCH] egl: Use correct shared libraries suffix on macOS.

2018-10-07 Thread Vinson Lee
Signed-off-by: Vinson Lee --- src/egl/egl-symbols-check | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/egl/egl-symbols-check b/src/egl/egl-symbols-check index 460e61a357c7..4200f9c07f3a 100755 --- a/src/egl/egl-symbols-check +++ b/src/egl/egl-symbols-check @@ -1,7 +

[Mesa-dev] [PATCH] nvc0: fix blitting red to srgb8_alpha

2018-10-07 Thread Ilia Mirkin
For some reason the 2d engine can't handle this. Red formats get special treatment there, so perhaps related. Fixes dEQP-GLES3 tests of the form: dEQP-GLES3.functional.fbo.blit.conversion.r{8,16f,32f}_to_srgb8_alpha8 Signed-off-by: Ilia Mirkin Cc: mesa-sta...@lists.freedesktop.org --- src/ga

[Mesa-dev] [PATCH] nv50,nvc0: guard against zero-size blits

2018-10-07 Thread Ilia Mirkin
The current state tracker can generate these sometimes. Fixing this is more involved, and due to some integer math we can generate divisions-by-zero. Signed-off-by: Ilia Mirkin Cc: mesa-sta...@lists.freedesktop.org --- src/gallium/drivers/nouveau/nv50/nv50_surface.c | 7 +++ src/gallium/driv

Re: [Mesa-dev] EGL_MESA_query_renderer

2018-10-07 Thread Veluri Mithun
Hi Nicolai, All these days I worked on packaging since I didn't find much time last month in my new academic schedule, I finished it if you wish you may download it here(https://flathub.org/apps/details/br.com.jeanhertel.adriconf). Currently, it can configure drivers in X11 server. I started to w

[Mesa-dev] [PATCH] nv50, nvc0: mark RGBX_UINT formats as renderable

2018-10-07 Thread Ilia Mirkin
This helps st/mesa avoid some (apparently) buggy fallbacks. Specifically the CopyTexSubImage callback tries to read texture A as RGBA_FLOAT and write back that data into the target format, which fails for integer formats which have no appropriate logic to do the conversion. Since integer formats d

[Mesa-dev] [PATCH 3/4] radeonsi: emit sample locations for 1xAA only when the hw bug is present

2018-10-07 Thread Marek Olšák
From: Marek Olšák --- src/gallium/drivers/radeonsi/si_state.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index af1b9f0acc8..d3c63406dd4 100644 --- a/src/gallium/drivers/radeonsi/si_s

[Mesa-dev] [PATCH 4/4] radeonsi: track context rolls better for the Vega scissor bug workaround

2018-10-07 Thread Marek Olšák
From: Marek Olšák We should get fewer context rolls with the SET_CONTEXT_REG optimization, but it would have been for nothing if the scissor state rolled the context anyway. Don't emit the scissor state if there is no context roll. --- src/gallium/drivers/radeonsi/si_pipe.h| 1 + src/ga

[Mesa-dev] [PATCH 1/4] radeonsi: use copy_buffer in buffer_do_flush_region directly

2018-10-07 Thread Marek Olšák
From: Marek Olšák --- src/gallium/drivers/radeonsi/si_buffer.c | 15 --- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c index a03a94453a4..c7260e06ccf 100644 --- a/src/gallium/drivers

[Mesa-dev] [PATCH 2/4] radeonsi: use compute shaders for clear_buffer & copy_buffer

2018-10-07 Thread Marek Olšák
From: Marek Olšák Fast color clears should be much faster. Also, fast color clears on evicted buffers should be 200x faster on GFX8 and older. --- src/gallium/drivers/radeonsi/Makefile.sources | 1 + src/gallium/drivers/radeonsi/meson.build | 1 + src/gallium/drivers/radeonsi/si_clear.c