From: Marek Vasut <ma...@denx.de>
This fixes "a2xx: Compute depth base in gmem consistently" by using
the already present zsbuf and cbuf bases rather than incorrect hand
crafted calculation.
Without this patch, the following assertion triggers ie. with Qt5
on system with 480x272 display:
appliation:
../../../../../git/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h:699:
A2XX_RB_DEPTH_INFO_DEPTH_BASE: Assertion `!(val & 0x3ff)' failed.
Signed-off-by: Marek Vasut <ma...@denx.de>
---
src/gallium/drivers/freedreno/a2xx/a2xx.xml.h | 4 ++--
src/gallium/drivers/freedreno/a2xx/fd2_gmem.c | 12 +++++++-----
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
b/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
index 4a2daca9ed..87c18918f5 100644
--- a/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
+++ b/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
@@ -682,7 +682,7 @@ static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val)
static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val)
{
assert(!(val & 0x3ff));
- return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) &
A2XX_RB_COLOR_INFO_BASE__MASK;
+ return ((val >> 12) << A2XX_RB_COLOR_INFO_BASE__SHIFT) &
A2XX_RB_COLOR_INFO_BASE__MASK;
}
#define REG_A2XX_RB_DEPTH_INFO 0x00002002
@@ -697,7 +697,7 @@ static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum
adreno_rb_depth_form
static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
{
assert(!(val & 0x3ff));
- return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) &
A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
+ return ((val >> 12) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) &
A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
}
#define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005
diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
index 7cf5e201fe..cf93d8539c 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
@@ -110,6 +110,7 @@ fd2_emit_tile_gmem2mem(struct fd_batch *batch, struct
fd_tile *tile)
{
struct fd_context *ctx = batch->ctx;
struct fd2_context *fd2_ctx = fd2_context(ctx);
+ struct fd_gmem_stateobj *gmem = &ctx->gmem;
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
@@ -172,10 +173,10 @@ fd2_emit_tile_gmem2mem(struct fd_batch *batch, struct
fd_tile *tile)
A2XX_RB_COPY_DEST_OFFSET_Y(tile->yoff));
if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
- emit_gmem2mem_surf(batch, tile->bin_w * tile->bin_h,
pfb->zsbuf);
+ emit_gmem2mem_surf(batch, gmem->zsbuf_base[0], pfb->zsbuf);
if (batch->resolve & FD_BUFFER_COLOR)
- emit_gmem2mem_surf(batch, 0, pfb->cbufs[0]);
+ emit_gmem2mem_surf(batch, gmem->cbuf_base[0], pfb->cbufs[0]);
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
@@ -235,6 +236,7 @@ fd2_emit_tile_mem2gmem(struct fd_batch *batch, struct
fd_tile *tile)
{
struct fd_context *ctx = batch->ctx;
struct fd2_context *fd2_ctx = fd2_context(ctx);
+ struct fd_gmem_stateobj *gmem = &ctx->gmem;
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
unsigned bin_w = tile->bin_w;
@@ -333,10 +335,10 @@ fd2_emit_tile_mem2gmem(struct fd_batch *batch, struct
fd_tile *tile)
OUT_RING(ring, 0x00000000);
if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH |
FD_BUFFER_STENCIL))
- emit_mem2gmem_surf(batch, bin_w * bin_h, pfb->zsbuf);
+ emit_mem2gmem_surf(batch, gmem->zsbuf_base[0], pfb->zsbuf);
if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR))
- emit_mem2gmem_surf(batch, 0, pfb->cbufs[0]);
+ emit_mem2gmem_surf(batch, gmem->cbuf_base[0], pfb->cbufs[0]);
/* TODO blob driver seems to toss in a CACHE_FLUSH after each
DRAW_INDX.. */
}
@@ -360,7 +362,7 @@ fd2_emit_tile_init(struct fd_batch *batch)
OUT_RING(ring, gmem->bin_w); /* RB_SURFACE_INFO */
OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(format)) |
A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(format)));
- reg = A2XX_RB_DEPTH_INFO_DEPTH_BASE(align(gmem->bin_w * gmem->bin_h,
4));
+ reg = A2XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]);
if (pfb->zsbuf)
reg |=
A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
OUT_RING(ring, reg); /* RB_DEPTH_INFO */
--
2.17.1
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