Patch sets additional formats renderable and enables the extension
when OpenGL ES 3.1 is supported.
Signed-off-by: Tapani Pälli
---
src/mesa/main/extensions_table.h | 1 +
src/mesa/main/fbobject.c | 20 +++-
src/mesa/main/glformats.c| 9 +
3 files change
https://bugs.freedesktop.org/show_bug.cgi?id=106836
Yogish Kulkarni changed:
What|Removed |Added
CC||kyle.brenne...@gmail.com
--- Comment
Tested-by: Dieter Nützel
with glmark2, UH, UV, Blender 2.79, FreeCAD, Krita 4.0.3 under KDE
Plasma5
on my Polaris 20 / RX580.
Dieter
Am 09.06.2018 05:17, schrieb Marek Olšák:
From: Marek Olšák
---
src/gallium/auxiliary/hud/hud_context.c | 5 -
1 file changed, 4 insertions(+), 1 delet
For this series:
Tested-by: Dieter Nützel
with glmark2, UH, UV, Blender 2.79, FreeCAD, Krita 4.0.3 under KDE
Plasma5
on my Polaris 20 / RX580.
Dieter
Am 09.06.2018 05:16, schrieb Marek Olšák:
From: Marek Olšák
We treat coherent and non-coherent buffers the same.
And move external_usage
Nevermind, I've spooled master back before Sonny Jiang's series you've
committed on Thursday, so
for this series:
Tested-by: Dieter Nützel
with glmark2, UH, UV, Blender 2.79, FreeCAD, Krita 4.0.3 under KDE
Plasma5
on my Polaris 20 / RX580.
Dieter
Am 11.06.2018 01:55, schrieb Dieter Nützel
Hello Marek,
5-9 and 12,13 do not apply clean on master.
repro for merge?
Dieter
Am 08.06.2018 05:25, schrieb Marek Olšák:
Ping
On Fri, Jun 1, 2018 at 1:21 AM, Marek Olšák
wrote:
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_state_binning.c | 14 +-
1 file changed, 5 i
On 10/06/18 18:42, Eric Engestrom wrote:
Coverity ID: 1436909
Fixes: 3352f2d746d3959b22ca4 "i965: Create multiple miptrees for planar YUV
images"
Signed-off-by: Eric Engestrom
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-
On 10/06/18 13:23, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-06-10 13:15:10)
Now that we're softpinning the address of our BOs in anv & i965, the
addresses selected start at the top of the addressing space. This is a
problem for the current implementation of aubinator which uses only a
Coverity ID: 1436909
Fixes: 3352f2d746d3959b22ca4 "i965: Create multiple miptrees for planar YUV
images"
Signed-off-by: Eric Engestrom
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/int
Quoting Lionel Landwerlin (2018-06-10 13:15:10)
> Now that we're softpinning the address of our BOs in anv & i965, the
> addresses selected start at the top of the addressing space. This is a
> problem for the current implementation of aubinator which uses only a
> 40bit mmapped address space.
>
>
Now that we're softpinning the address of our BOs in anv & i965, the
addresses selected start at the top of the addressing space. This is a
problem for the current implementation of aubinator which uses only a
40bit mmapped address space.
This change keeps track of all the memory writes from the a
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_batch_decoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/common/gen_batch_decoder.c
b/src/intel/common/gen_batch_decoder.c
index a8e709358cd..963adbec271 100644
--- a/src/intel/common/gen_batch_decoder
Technically only for Sandybridge and later core designs, but finally we
can claim support for allowing clients to create glBufferObjects from
their own memory.
---
docs/relnotes/18.2.0.html | 1 +
1 file changed, 1 insertion(+)
diff --git a/docs/relnotes/18.2.0.html b/docs/relnotes/18.2.0.html
in
All GEN GPU can bind to any piece of memory (thanks UMA), and so through
a special ioctl we can map a chunk of page-aligned client memory into
the GPU address space. However, not all GEN are equal. Some have
cache-coherency between the CPU and the GPU, whilst the others are
incoherent and rely on s
The primary benefit for this is that we get format conversion for
"free", along with detiling and cache flushing (most relevant for !llc).
Using the GPU does impose a bandwidth cost that is presumably better
used for rendering, hence we limit the use to readback into client
memory (not pbo) where w
Since v3.16 (though universal access was only enabled by default in v4.6),
the kernel has offered the ability to wrap any system memory (i.e. RAM
and not I/O mapped memory) into an object that can be used by the GPU. The
caveat is that this object is marked as cache coherent (so that the client
can
Recent kernels do exclude snoop access for i965g/i965gm as it does not
work as advertised. However to avoid depending on a recent kernel for
old hardware, mark the presence of the bug in gen_device_info.
See kernel commit df0700e53047662c167836bd6fdeea55d5d8dcfa
Author: Chris Wilson
Date: Wed S
Signed-off-by: Eric Engestrom
---
include/EGL/eglext.h | 86 +---
1 file changed, 81 insertions(+), 5 deletions(-)
diff --git a/include/EGL/eglext.h b/include/EGL/eglext.h
index 2f990cc54d6d8202176e..794bd532881befec8ed9 100644
--- a/include/EGL/eglext.h
+
Signed-off-by: Eric Engestrom
---
include/KHR/khrplatform.h | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/include/KHR/khrplatform.h b/include/KHR/khrplatform.h
index 93acb076a06be896e698..975bbffed6741b75e05d 100644
--- a/include/KHR/khrplatform.h
+++ b
An issue [1] was recently raised with the upstream eglplatform.h, as my
upstreaming of the "X11 on Apple" resulted in Apple platforms to always
try to include X11 headers.
The solution [2] was to also upstream our `MESA_EGL_NO_X11_HEADERS`
toggle, inverted as `USE_X11`.
This commit updates our co
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