Fix build error without DRI3.
CC drivers/dri2/platform_x11.lo
drivers/dri2/platform_x11.c:1010:1: error: no previous prototype for function
'dri2_format_for_depth' [-Werror,-Wmissing-prototypes]
dri2_format_for_depth(uint32_t depth)
^
Fixes: 473af0b541b2 ("egl/x11: deduplicate depth-to-f
Am Dienstag, den 22.05.2018, 18:27 -0700 schrieb Gurchetan Singh:
> Reviewed-by: Gurchetan Singh
Thanks for the review Gurchetan.
The patch was originally sent as RFC, because there seemed to be
regressions, but that is not the case, so could someone please push it,
because I don't have commit r
Hi Rob,
Sorry for late review. Had some really busy time.
On Fri, May 11, 2018 at 10:48 PM Robert Foss
wrote:
[snip]
> @@ -1230,20 +1256,26 @@ dri2_initialize_android(_EGLDriver *drv,
_EGLDisplay *disp)
> dri2_dpy->is_render_node = drmGetNodeTypeFromFd(dri2_dpy->fd) ==
DRM_NODE_RENDER;
>
https://bugs.freedesktop.org/show_bug.cgi?id=106646
--- Comment #2 from Jason Ekstrand ---
I'd really like to support this in anv but it isn't as trivial as it looks.
The only 32-bit image format supported by X11 is B8G8R8A8_UNORM which is not
one of the standard storage image formats. I think
https://bugs.freedesktop.org/show_bug.cgi?id=106646
Jason Ekstrand changed:
What|Removed |Added
Assignee|mesa-dev@lists.freedesktop. |ja...@jlekstrand.net
https://bugs.freedesktop.org/show_bug.cgi?id=106646
Tapani Pälli changed:
What|Removed |Added
CC||lem...@gmail.com
--- Comment #1 from Tap
https://bugs.freedesktop.org/show_bug.cgi?id=106646
Bug ID: 106646
Summary: Support VK_IMAGE_USAGE_STORAGE_BIT for WSI swapchain
surfaces
Product: Mesa
Version: git
Hardware: Other
OS: All
Status
https://bugs.freedesktop.org/show_bug.cgi?id=106644
Roland Scheidegger changed:
What|Removed |Added
CC||bcroc...@redhat.com
--- Comment #8
On 25/05/18 11:24, Bas Nieuwenhuizen wrote:
On Fri, May 25, 2018 at 2:25 AM, Timothy Arceri wrote:
From what I recall with my testing on radeonsi this wasn't really the ideal
thing to do. Especially when varyings arrays are accessed via and indirect
index, register use very quickly gets out o
There are a bunch of changes in patch 12 to this stuff. They should
probably be squashed in here.
On May 24, 2018 17:28:26 Laura Ekstrand wrote:
From: Jean Hertel
Toctree directives create automatically generated navigation sidebars.
This is the new relnotes sidebar.
---
docs/relnotes.rst
This is missing the 18.x versions
On May 24, 2018 17:28:26 Laura Ekstrand wrote:
From: Jean Hertel
Toctree directives create automatically generated navigation sidebars.
This is the new relnotes sidebar.
---
docs/relnotes.rst | 197 ++
1 fil
On Fri, May 25, 2018 at 2:25 AM, Timothy Arceri wrote:
>
> From what I recall with my testing on radeonsi this wasn't really the ideal
> thing to do. Especially when varyings arrays are accessed via and indirect
> index, register use very quickly gets out of control.
in radv we lower all indirect
Reviewed-by: Gurchetan Singh
On Wed, May 23, 2018 at 1:36 AM Tomeu Vizoso
wrote:
> Virgl could save a lot of work converting buffers in the host side
> between formats if Mesa supported a bunch of other formats when reading
> pixels.
>
> This commit adds cases to handle specific formats so th
Pushed. Thanks for the patch.
On 25/05/18 03:56, Jose Dapena Paz wrote:
When glUseProgram is used, references to the included shaders are
added in ctx->Shader.ReferencedProgram. But those references are not
decreased when the shader data is deallocated. Thus, those shaders
are leaked.
Explicite
A few of the commits are quite large and awaiting list approval. I suggest
that you take a look at the code here:
https://gitlab.freedesktop.org/ldeks/mesa/tree/website1_75,
and the new website here: https://mesa-test.freedesktop.org/index.html
Laura
On Thu, May 24, 2018 at 5:27 PM, Laura Ekstra
Goodbye old css file. You belong in 1999 from whence you came.
---
docs/mesa.css | 63 ---
1 file changed, 63 deletions(-)
delete mode 100644 docs/mesa.css
diff --git a/docs/mesa.css b/docs/mesa.css
deleted file mode 100644
index 7ab8152b0
This just involves some quick fixes to formatting of the affected pages.
---
docs/autoconf.rst| 1 +
docs/conf.py | 2 +-
docs/dispatch.rst| 72 ++--
docs/egl.rst | 2 ++
docs/releasing.rst | 14 +-
ReStructured Text toctrees are used to automatically generate the
sidebar. But all top-level headings get added to it by default. In
order to workaround this, you must create one and only one
top-level heading for each page.
---
docs/download.rst | 2 +-
docs/faq.rst | 2 +-
docs/index.
This is a huge page. The edits I've done here take full advantage of
reStructured text and Sphinx's awesome built-in style for explaining
commands and variables. Enjoy!
---
docs/envvars.rst | 604 ++-
1 file changed, 425 insertions(+), 179 dele
From: Jean Hertel
This is the new main sidebar.
---
docs/index.rst | 90 ++
1 file changed, 90 insertions(+)
diff --git a/docs/index.rst b/docs/index.rst
index e11b1e4ecc..f2ab63fb63 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -1,3
Toctree directives create automatically generated navigation sidebars.
This is the new deprecated systems sidebar.
---
docs/systems.rst | 6 ++
1 file changed, 6 insertions(+)
diff --git a/docs/systems.rst b/docs/systems.rst
index 707abeeed9..b05aff0621 100644
--- a/docs/systems.rst
+++ b/doc
Use Beautiful Soup to fix bad html, then use pandoc for converting to
rst.
---
docs/rstConverter.py | 23 +++
1 file changed, 23 insertions(+)
create mode 100755 docs/rstConverter.py
diff --git a/docs/rstConverter.py b/docs/rstConverter.py
new file mode 100755
index 0
This does two things. 1. It pulls a Docker image which is a Linux
system with Sphinx and the Read the Docs Sphinx theme already installed.
2. It uses sphinx-build to build html from our rst pages.
---
.gitlab-ci.yml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/.gitlab-ci
From: Jean Hertel
This tells Sphinx how to build our website from reStructured Text.
Signed-off-by: Jean Hertel
---
docs/conf.py | 162 +++
1 file changed, 162 insertions(+)
create mode 100644 docs/conf.py
diff --git a/docs/conf.py b/do
It's time to move the Mesa-3d.org website into the 21st century. We have
chosen to move to Sphinx and resStructured text for a number of reasons:
1. Syntax highlighting for code snippets.
2. Snazzy highlighting for variables and function names.
3. Consistency with the Gallium drivers, which h
From: Jean Hertel
Toctree directives create automatically generated navigation sidebars.
This is the new relnotes sidebar.
---
docs/relnotes.rst | 197 ++
1 file changed, 197 insertions(+)
diff --git a/docs/relnotes.rst b/docs/relnotes.rst
ind
The old navigation bar, may it rest in peace, causes major problems when
running the rstConverter.py script. It's also unneeded.
Let's get rid of it now.
---
docs/contents.html | 108 -
1 file changed, 108 deletions(-)
delete mode 100644 docs/c
For now, all this does is copy our current webpage into a public folder.
Daniel Stone has the server configured to check this public folder and
host the index.html as mesa-test.freedesktop.org. When this patch series
is approved, Daniel will change it to point at mesa-3d.org.
---
.gitlab-ci.yml |
From what I recall with my testing on radeonsi this wasn't really the
ideal thing to do. Especially when varyings arrays are accessed via and
indirect index, register use very quickly gets out of control.
On 23/05/18 22:31, Samuel Pitoiset wrote:
Do not lower FS inputs because this moves al
On 23/05/18 03:16, Ian Romanick wrote:
On 05/11/2018 09:49 PM, Timothy Arceri wrote:
Mesa seems to be the only implementation that doesn't allow builtins
to be explicitly declared. The GLSL 1.30 spec seems to imply that
buitins may be explicitly declared.
There was a clarification added to the
On Thu, May 24, 2018 at 6:23 AM, Robert Foss wrote:
> Hey,
>
> I don't think I've received any feedback on this version yet.
> If anyone has some time to spare, it would be nice to get it merged.
>
> Just to be clear about the libdrm branch linked in the cover letter,
> it is not required. Only fo
Entire patchset: 1-7 (What I meant to say in the first place)
Reviewed-by: Bruce Cherniak
> On May 24, 2018, at 11:13 AM, Cherniak, Bruce
> wrote:
>
> Patchset (1/7)
> Reviewed-by: Bruce Cherniak
>
>> On May 23, 2018, at 2:58 PM, Alok Hota wrote:
>>
>> SCATTERPS previously assumed it wa
https://bugs.freedesktop.org/show_bug.cgi?id=106644
--- Comment #7 from erhar...@mailbox.org ---
Created attachment 139749
--> https://bugs.freedesktop.org/attachment.cgi?id=139749&action=edit
coredump lp_test_printf
--
You are receiving this mail because:
You are the QA Contact for the bug.
Y
https://bugs.freedesktop.org/show_bug.cgi?id=106644
--- Comment #6 from erhar...@mailbox.org ---
Created attachment 139748
--> https://bugs.freedesktop.org/attachment.cgi?id=139748&action=edit
coredump lp_test_conv
--
You are receiving this mail because:
You are the QA Contact for the bug.
You
https://bugs.freedesktop.org/show_bug.cgi?id=106644
--- Comment #5 from erhar...@mailbox.org ---
Created attachment 139747
--> https://bugs.freedesktop.org/attachment.cgi?id=139747&action=edit
coredump lp_test_format
--
You are receiving this mail because:
You are the assignee for the bug.
You
https://bugs.freedesktop.org/show_bug.cgi?id=106644
--- Comment #4 from erhar...@mailbox.org ---
Created attachment 139746
--> https://bugs.freedesktop.org/attachment.cgi?id=139746&action=edit
coredump lp_test_blend
--
You are receiving this mail because:
You are the assignee for the bug.
You
https://bugs.freedesktop.org/show_bug.cgi?id=106644
--- Comment #3 from erhar...@mailbox.org ---
Created attachment 139745
--> https://bugs.freedesktop.org/attachment.cgi?id=139745&action=edit
coredump lp_test_arit
--
You are receiving this mail because:
You are the QA Contact for the bug.
You
https://bugs.freedesktop.org/show_bug.cgi?id=106644
erhar...@mailbox.org changed:
What|Removed |Added
Attachment #139742|0 |1
is obsolete|
https://bugs.freedesktop.org/show_bug.cgi?id=106644
--- Comment #1 from erhar...@mailbox.org ---
Created attachment 139743
--> https://bugs.freedesktop.org/attachment.cgi?id=139743&action=edit
test-suite.log
--
You are receiving this mail because:
You are the QA Contact for the bug.
You are th
https://bugs.freedesktop.org/show_bug.cgi?id=106644
Bug ID: 106644
Summary: [llvmpipe] Mesa 18.1.0 fails lp_test_format,
lp_test_arit, lp_test_blend, lp_test_printf,
lp_test_conv tests
Product: Mesa
Version: unspe
On Thu, 2018-05-24 at 13:08 -0500, Aaron Watry wrote:
> On Tue, May 22, 2018 at 6:43 PM, Jan Vesely wrote:
> > r332881 added an extra parameter to the emit function.
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106619
> > Signed-off-by: Jan Vesely
> > ---
> > .../state_trackers/clo
On Thu, May 24, 2018 at 4:32 PM, Ian Romanick wrote:
> On 05/23/2018 01:58 PM, Marek Olšák wrote:
> > Hi,
> >
> > This advances GL compatibility support a little bit. Geometry and
> > tessellation shaders should work if you don't combine them with
> > non-GLSL stages. All GLSL legacy variables sh
From: Francisco Jerez
Co-authored-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.cpp | 54 ++-
1 file changed, 43 insertions(+), 11 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index c821a11..1c022de 100644
--
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_visitor.cpp | 116 ++
1 file changed, 60 insertions(+), 56 deletions(-)
diff --git a/src/intel/compiler/brw_fs_visitor.cpp
b/src/intel/compiler/brw_fs_visitor.cpp
index 06b46d3..545
---
src/intel/compiler/brw_fs.cpp | 83 ++---
src/intel/compiler/brw_fs_generator.cpp | 2 +-
2 files changed, 57 insertions(+), 28 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 7e532af..c821a11 100644
--- a/sr
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_nir.cpp | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 50227df..43d8f00 100644
--- a/src/intel/compile
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_builder.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/intel/compiler/brw_fs_builder.h
b/src/intel/compiler/brw_fs_builder.h
index 4203c8c..7bee2aa 100644
--- a/src/intel/compiler/b
---
src/intel/blorp/blorp_genX_exec.h | 14 ++
src/intel/vulkan/genX_pipeline.c | 20 ++--
src/mesa/drivers/dri/i965/genX_state_upload.c | 16
3 files changed, 48 insertions(+), 2 deletions(-)
diff --git a/src/intel/blorp/blorp
---
src/intel/compiler/brw_fs.cpp | 25 ++---
1 file changed, 6 insertions(+), 19 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 1f87f06..7e532af 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -3
We can just emit the MOV in the two places where we use this.
---
src/intel/compiler/brw_eu_defines.h | 1 -
src/intel/compiler/brw_fs.cpp | 8 +---
src/intel/compiler/brw_fs_generator.cpp | 28
src/intel/compiler/brw_fs_visitor.cpp | 4 +++-
src
There's no reason for us to emit it a pile of times and then have a
whole pass to clean it up. Just emit it once like we really want.
---
src/intel/compiler/brw_fs.cpp | 39 ---
src/intel/compiler/brw_fs_visitor.cpp | 27 ++--
2 files ch
---
src/intel/blorp/blorp_genX_exec.h | 3 +++
src/intel/compiler/brw_compiler.h | 7 +++
src/intel/compiler/brw_fs_visitor.cpp | 1 +
src/intel/vulkan/genX_pipeline.c | 2 +-
src/mesa/drivers/dri/i965/gen4_blorp_exec.h | 1 +
src/mesa/drivers/dri
From: Francisco Jerez
v2 (Jason Ekstrand):
- Disallow gl_SampleId in SIMD32 on gen7
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.cpp | 31 ++-
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/comp
From: Francisco Jerez
This generalizes the unlit centroid workaround so it's less code and now
supports SIMD32.
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_visitor.cpp | 22 --
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/src/intel/compiler/b
From: Francisco Jerez
While we're here, we change to using horiz_offset() instead of abusing
half().
v2 (Jason Ekstrand):
- Use horiz_offset() instead of half()
---
src/intel/compiler/brw_fs_visitor.cpp | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --gi
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.cpp | 10 +-
src/intel/compiler/brw_fs.h | 13 +
src/intel/compiler/brw_fs_visitor.cpp | 12 +---
3 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/src/in
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.cpp | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index f583900..ae59716 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/sr
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.cpp | 124 +++---
1 file changed, 57 insertions(+), 67 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 2373a93..f583900 100644
--- a
From: Francisco Jerez
And handle 32-wide payload register reads in fetch_payload_reg().
v2 (Jason Ekstrand);
- Fix some whitespace and brace placement
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.cpp| 14 +++---
src/intel/compiler/brw_fs.h | 42 +
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.cpp | 28 +++-
1 file changed, 7 insertions(+), 21 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 5ef3cd4..e1232d6 100644
--- a/src/intel/compi
On g4x through Sandy Bridge, src1 (the coordinates) of the PLN
instruction is required to be an even register number. When it's odd
(which can happen with SIMD32), we have to emit a LINE+MAC combination
instead. Unfortunately, we can't just fall through to the gen4 case
because the input register
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.cpp | 2 +-
src/intel/compiler/brw_fs_generator.cpp | 5 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 9a93d47..5a3
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/blorp/blorp.c | 2 +-
src/intel/compiler/brw_compiler.h | 1 +
src/intel/compiler/brw_fs.cpp | 2 +-
src/intel/vulkan/anv_pipeline.c | 2 +-
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src
We want consistent behavior in the meaning of the flag_subreg field
between SNB and IVB+.
v2 (Jason Ekstrand):
- Add some extra commentary
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_generator.cpp | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/inte
From: Francisco Jerez
---
src/intel/compiler/brw_shader.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_shader.cpp
b/src/intel/compiler/brw_shader.cpp
index 141b64e..61211ef 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/
From: Francisco Jerez
This reworks INTERPOLATE_AT_PER_SLOT_OFFSET to work more like an ALU
operation and less like a send. This is less code over-all and, as a
side-effect, it now properly handles execution groups and lowering so
SIMD32 support just falls out.
Reviewed-by: Jason Ekstrand
---
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_generator.cpp | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_generator.cpp
index f9d0b46..4bcf2e5
Commit 0d905597f fixed an issue with the placement of the zip and unzip
instructions. However, as a side-effect, it reversed the order in which
we were emitting the split instructions so that they went from high
group to low instead of low to high. This is fine for most things like
texture instru
---
src/intel/compiler/brw_compiler.h | 53 +--
src/intel/compiler/brw_fs.cpp | 35 +++
src/intel/compiler/brw_fs_visitor.cpp | 2 +-
3 files changed, 43 insertions(+), 47 deletions(-)
diff --git a/src/intel/compiler/brw_compiler.h
Prior to gen8, the flag reg and subreg numbers are in different
locations on 3src instructions than on smaller instructions. In order
for brw_set_default_flag_reg to work properly, we need to copy the value
out of the 2src location and write it into the 3src location as part of
brw_alu3.
Cc: mesa
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.cpp | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 9d90d11..6a1fca3 100644
--- a/src/intel/compiler/brw_fs.
From: Francisco Jerez
This prevents a crash in some arb_enhanced_layouts tests that would be
caused by the next commit.
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_visitor.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs_visitor.
From: Francisco Jerez
---
src/intel/compiler/brw_fs.cpp | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 5804591..9d90d11 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/c
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_eu_emit.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 294bea0..fc39d94 100644
--- a/src/intel/compiler/brw_eu_emit.c
+
From: Francisco Jerez
Current discard handling requires dedicating the second flag register to
discard. However, control-flow in SIMD32 requires both flag registers
so it's incompatible with the current discard handling. Just don't
support SIMD32+discard for now.
Reviewed-by: Jason Ekstrand
-
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_generator.cpp | 52 +
1 file changed, 34 insertions(+), 18 deletions(-)
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_generator.cpp
index 4bcf2e5.
The pixel shader dispatch table is kind-of a confusing mess. This adds
some helpers for dealing with it and for easily extracting the correct
data from wm_prog_data.
---
src/intel/blorp/blorp_genX_exec.h | 65
src/intel/compiler/brw_compiler.h | 85 +++
From: Francisco Jerez
The hardware's control flow logic is 16-wide so we're out of luck
here. We could, in theory, support SIMD32 if we know the control-flow
is uniform but we don't have that information at this point.
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_nir.cpp | 8
Doing instruction header setup in the generator is aweful for a number
of reasons. For one, we can't schedule the header setup at all. For
another, it means lots of implied writes which the instruction scheduler
and other passes can't properly read about. The second isn't a huge
problem for FB w
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_eu.h | 20 ++--
src/intel/compiler/brw_eu_emit.c | 24 +---
2 files changed, 23 insertions(+), 21 deletions(-)
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 94 ---
1 file changed, 57 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 4f44b99..6d430f6 100644
--- a/src/mesa/drivers/dr
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.cpp | 4 ++--
src/intel/compiler/brw_fs.h| 2 --
src/intel/compiler/brw_fs_generator.cpp| 3 +--
src/intel/compiler/brw_shader.cpp | 2 +-
src/intel/compiler/brw_vec4.cpp
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 600d901..069959e 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/int
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 069959e..3e9ccc4 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/int
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_generator.cpp | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_generator.cpp
index f49ab44..467a39
The FB write opcode on gen4-5 does implied copies from g0 and g1 to the
message payload. With this commit, we start tracking that as part of
the IR by having the FB write read from g0-1.
---
src/intel/compiler/brw_fs.cpp | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
dif
Now that we have the implied header in src[0] for tracking purposes, we
may as well use it in the generator. This makes things a tiny bit more
general.
---
src/intel/compiler/brw_fs_generator.cpp | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/src/intel/compile
It doesn't matter since we don't ever run replicated write shaders
through the optimizer but it's good to be complete.
---
src/intel/compiler/brw_shader.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/compiler/brw_shader.cpp
b/src/intel/compiler/brw_shader.cpp
index 6e81db9..45b
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.cpp | 1 +
src/intel/compiler/brw_fs_generator.cpp | 6 +-
src/intel/compiler/brw_fs_visitor.cpp | 2 ++
src/intel/compiler/brw_ir_fs.h | 1 +
4 files changed, 5 insertions(+), 5 deletions(-
From: Francisco Jerez
v2 (Jason Ekstrand):
- Break the refactor into its own patch
Reviewed-by: Jason Ekstrand
Reviewed-by: Kenneth Graunke
---
src/intel/compiler/brw_fs_nir.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/s
This patch series adds back-end compiler support for SIMD32 fragment
shaders. Support is added and everything works but it's currently hidden
behind INTEL_DEBUG=do32. We know that it improves performance in some
cases but we do not yet have a good enough heuristic to start turning it on
by defaul
From: Francisco Jerez
The only reason it was it's own opcode was so that we could detect it
and adjust the source register based on the payload setup. Now that
we're using the ATTR file for FS inputs, there's no point in having a
magic opcode for this.
v2 (Jason Ekstrand):
- Break the bit whic
This is better than compression control because it naturally extends to
SIMD32.
v2:
- Push/pop instruction state around adjusted codegen (Ken)
Reviewed-by: Kenneth Graunke
---
src/intel/compiler/brw_fs_generator.cpp | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/s
From: Francisco Jerez
Reviewed-by: Jason Ekstrand
Reviewed-by: Kenneth Graunke
---
src/intel/compiler/brw_eu.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 120a74f..2655cdb 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/
From: Francisco Jerez
This replaces the special magic opcodes which implicitly read inputs
with explicit use of the ATTR file.
v2 (Jason Ekstrand):
- Break into multiple patches
- Change the units of the FS ATTR to be in logical scalars
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw
The fall-back does not work correctly in SIMD16 mode and the register
allocator should ensure that we never hit this case anyway.
---
src/intel/compiler/brw_fs_generator.cpp | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/sr
On Fri, May 11, 2018 at 11:57 AM, Prateek Chanda wrote:
> Dear Sir/Madam
>
>
>
> I am writing this letter as I am planning for my application for a project
> work on Piglit for OpenMAX under X.org Evoc. I have already spoken to my
> mentor and have discussed with him the application procedure.
>
On 05/24/2018 11:10 PM, Samuel Pitoiset wrote:
On 05/24/2018 11:00 PM, Tom Stellard wrote:
On 05/24/2018 01:55 PM, Samuel Pitoiset wrote:
It's recommended by the instruction combining pass, and
RadeonSI also runs it.
This pass used to segfault with one shader of F12017 but it
has been fixe
On 05/24/2018 11:00 PM, Tom Stellard wrote:
On 05/24/2018 01:55 PM, Samuel Pitoiset wrote:
It's recommended by the instruction combining pass, and
RadeonSI also runs it.
This pass used to segfault with one shader of F12017 but it
has been fixed somewhere in LLVM 7.
Do you know which patch
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Thu, May 24, 2018 at 1:09 PM, Samuel Pitoiset
wrote:
> The graphics pipeline can be NULL.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_debug.c | 13 -
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --g
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