[Mesa-dev] [PATCH] i965/fs: Reset the register file to VGRF in lower_integer_multiplication

18fde36ced4279f2577097a1a7d31b55f2f5f141 changed the way temporary registers were allocated in lower_integer_multiplication so that we allocate regs_written(inst) space and keep the stride of the original destination register. This was to ensure that any MUL which originally followed the CHV/BXT i

[Mesa-dev] [PATCH 17/17] anv/cmd_buffer: Move gen7 index buffer state to graphics state

--- src/intel/vulkan/anv_private.h | 12 ++-- src/intel/vulkan/gen7_cmd_buffer.c | 14 +++--- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 70c83d9..57b0051 100644 --- a/src/intel/vulkan/an

[Mesa-dev] [PATCH 16/17] anv/cmd_buffer: Move num_workgroups to compute state

While we're here, make it an anv_address. --- src/intel/vulkan/anv_private.h | 4 ++-- src/intel/vulkan/genX_cmd_buffer.c | 17 ++--- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 5ceec6b..70c8

[Mesa-dev] [PATCH 14/17] anv/cmd_buffer: Use a temporary variable for dynamic state

We were already doing this for some packets to keep the lines shorter. We may as well just do it for all of them. --- src/intel/vulkan/gen7_cmd_buffer.c | 19 +-- src/intel/vulkan/gen8_cmd_buffer.c | 32 +++- 2 files changed, 24 insertions(+), 27 deletio

[Mesa-dev] [PATCH 15/17] anv/cmd_buffer: Move dynamic state to graphics state

--- src/intel/vulkan/anv_cmd_buffer.c | 42 +++--- src/intel/vulkan/anv_private.h | 3 ++- src/intel/vulkan/gen7_cmd_buffer.c | 6 +++--- src/intel/vulkan/gen8_cmd_buffer.c | 12 ++- 4 files changed, 33 insertions(+), 30 deletions(-) diff --git a/src

[Mesa-dev] [PATCH 01/17] anv/pipeline: Don't assert on more than 32 samplers

This prevents an assert when running one unreleased Vulkan game. --- src/intel/vulkan/genX_pipeline.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 0ae9ead..b6a537b 100644 --- a/src/intel/vulkan/

[Mesa-dev] [PATCH 02/17] anv/cmd_state: Drop the scratch_size field

This is a legacy left-over from the mechanism we used to use to handle scratch. The new (and better) mechanism doesn't use this. --- src/intel/vulkan/anv_private.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index b7bde4b..2d3

[Mesa-dev] [PATCH 00/17] anv: Rework state tracking to better separate

This series is intended to address a bug filed in September: https://bugs.freedesktop.org/show_bug.cgi?id=102897 Unfortunately, the fix is either a lot of patches or very messy. This series (as is common for me) takes the lots of patches approach. The general idea is to break out a large chunk

[Mesa-dev] [PATCH 12/17] anv/cmd_buffer: Move dirty bits into anv_cmd_*_state

--- src/intel/vulkan/anv_cmd_buffer.c | 24 +++ src/intel/vulkan/anv_private.h | 6 -- src/intel/vulkan/gen7_cmd_buffer.c | 28 +- src/intel/vulkan/gen8_cmd_buffer.c | 40 +++--- src/intel/vulkan/genX_blorp_exec.

[Mesa-dev] [PATCH 05/17] anv/cmd_buffer: Use some pre-existing pipeline temporaries

There are several places where we'd already saved the pipeline off to a temporary variable but, due to an artifact of history, weren't actually using that temporary everywhere. No functional change. --- src/intel/vulkan/gen8_cmd_buffer.c | 3 +-- src/intel/vulkan/genX_cmd_buffer.c | 9 -

[Mesa-dev] [PATCH 13/17] anv/cmd_buffer: Move vb_dirty bits into anv_cmd_graphics_state

Vertex buffers are entirely a graphics pipeline thing. --- src/intel/vulkan/anv_cmd_buffer.c | 4 ++-- src/intel/vulkan/anv_private.h | 2 +- src/intel/vulkan/genX_blorp_exec.c | 2 +- src/intel/vulkan/genX_cmd_buffer.c | 6 +++--- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git

[Mesa-dev] [PATCH 06/17] anv/cmd_buffer: Add substructs to anv_cmd_state for graphics and compute

Initially, these just contain the pipeline in a base struct. --- src/intel/vulkan/anv_cmd_buffer.c | 12 +- src/intel/vulkan/anv_private.h | 41 -- src/intel/vulkan/gen7_cmd_buffer.c | 2 +- src/intel/vulkan/gen8_cmd_buffer.c | 6 ++--- src/intel/vulk

[Mesa-dev] [PATCH 09/17] anv/cmd_buffer: Add a helper for binding descriptor sets

This lets us unify some code between push descriptors and regular descriptors. It doesn't do much for us yet but it will. --- src/intel/vulkan/anv_cmd_buffer.c | 70 +++ 1 file changed, 42 insertions(+), 28 deletions(-) diff --git a/src/intel/vulkan/anv_cmd_bu

[Mesa-dev] [PATCH 03/17] anv/cmd_buffer: Get rid of the meta query workaround

Meta has been gone for a long time. --- src/intel/vulkan/anv_cmd_buffer.c | 1 - src/intel/vulkan/anv_private.h| 1 - src/intel/vulkan/genX_query.c | 14 -- 3 files changed, 16 deletions(-) diff --git a/src/intel/vulkan/anv_cmd_buffer.c b/src/intel/vulkan/anv_cmd_buffer.c i

[Mesa-dev] [PATCH 04/17] anv/cmd_buffer: Rework anv_cmd_state_reset

This splits anv_cmd_state_reset into separate init and finish functions. This lets us share init code with cmd_buffer_create. This potentially fixes subtle bugs where we may have missed some bit of state that needs to get initialized on command buffer creation. --- src/intel/vulkan/anv_cmd_buffer

[Mesa-dev] [PATCH 10/17] anv/cmd_buffer: Use anv_descriptor_for_binding for samplers

--- src/intel/vulkan/genX_cmd_buffer.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 9d6f753..994c996 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c

[Mesa-dev] [PATCH 08/17] anv/cmd_buffer: Refactor ensure_push_descriptor_set

It's now a function which returns the push descriptor set. Since we set the error on the command buffer, returning the error is a little redundant. Returning the descriptor set (or NULL on error) is more convenient. --- src/intel/vulkan/anv_cmd_buffer.c | 24 +--- 1 file chan

[Mesa-dev] [PATCH 11/17] anv: Separate compute and graphics descriptor sets

The Vulkan spec says: "pipelineBindPoint is a VkPipelineBindPoint indicating whether the descriptors will be used by graphics pipelines or compute pipelines. There is a separate set of bind points for each of graphics and compute, so binding one does not disturb the other." Up unt

[Mesa-dev] [PATCH 07/17] anv: Remove semicolons from vk_error[f] definitions

With the semicolons, they can't be used in a function argument without throwing syntax errors. --- src/intel/vulkan/anv_private.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 9860778..e8d0d27 100644 --

[Mesa-dev] [PATCH] Revert "anv/pipeline: Don't assert on more than 32 samplers"

This reverts commit 5fe67607d261b2f85c8f89914fe9bfef4eaf7561. --- src/intel/vulkan/genX_pipeline.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index b6a537b..0ae9ead 100644 --- a/src/intel/vulkan/gen

Re: [Mesa-dev] [PATCH 22/22] mesa: Add GL_UNSIGNED_INT_2_10_10_10_REV OES read type for BGRX1010102.

Reviewed-by: Marek Olšák Marek On Fri, Dec 15, 2017 at 11:05 PM, Mario Kleiner wrote: > As Marek noted, the GL_RGBA + GL_UNSIGNED_INT_2_10_10_10_REV type > combo is also good for readback of BGRX1010102 framebuffers, not > only for BGRA1010102 framebuffers for use with glReadPixels() > under GL

[Mesa-dev] [PATCH 3/8] anv: Make the clear state buffer 64 bytes aligned.

On Gen10+, if we use the clear state address field in the surface state instead of the clear color directly, there's a restriction that the address must point to the lower part of a 64 byte cache-line. Signed-off-by: Rafael Antognolli --- src/intel/vulkan/anv_private.h | 12 +++- 1 file

[Mesa-dev] [PATCH 4/8] intel/blorp: Add suport for fast clear address.

On gen10+, if surface->clear_color_addr is present, use it directly intead of copying it to the surface state. Signed-off-by: Rafael Antognolli --- src/intel/blorp/blorp_genX_exec.h | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/intel/blorp/blorp_genX_exec.h

[Mesa-dev] [PATCH 8/8] i965/surface_state: Silence warning.

This warning showed up after aux_bo started being used inside if (use_clear_address) {... But use_clear_address depends on aux_surf being not null, in which case aux_bo would also be set. Make the compiler happy anyway. Signed-off-by: Rafael Antognolli --- src/mesa/drivers/dri/i965/brw_wm_surf

[Mesa-dev] [PATCH 7/8] i965/surface_state: Emit the clear color address instead of value.

On Gen10, when emitting the surface state, use the value stored in the clear color entry buffer by using a clear color address in the surface state. Signed-off-by: Rafael Antognolli --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 16 1 file changed, 16 insertions(+) diff

[Mesa-dev] [PATCH 2/8] intel/isl: Add support to emit clear value address.

gen10 can emit the clear color by setting it on a buffer somewhere, and then adding only the address to the surface state. This commit add support for that on isl_surf_fill_state, and if that is requested, skip setting the clear value itself. Signed-off-by: Rafael Antognolli --- src/intel/isl/i

[Mesa-dev] [PATCH 6/8] i965/blorp: Update the fast clear color entry buffer.

On Gen10, whenever the fast clear color changes, update it on the clear color entry buffer. This allow us to use it directly when emitting the surface state. Signed-off-by: Rafael Antognolli --- src/mesa/drivers/dri/i965/brw_blorp.c | 26 ++ 1 file changed, 26 insertions(

[Mesa-dev] [PATCH 5/8] i965/miptree: Add space to store the clear value in the aux surface.

Similarly to vulkan where we store the clear value in the aux surface, we can do the same in GL. Signed-off-by: Rafael Antognolli --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 25 + 1 file changed, 25 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipma

[Mesa-dev] [PATCH 1/8] intel/genxml: Use a single field for clear color address on gen10.

genxml does not support having two address fields with different names but same position in the state struct. Both "Clear Color Address" and "Clear Depth Address Low" mean the same thing, only for different surface types. To workaround this genxml limitation, rename "Clear Color Address" to "Clear

[Mesa-dev] [PATCH 17/22] st/dri2: Add format translations for BGR[A/X]1010102 formats.

Signed-off-by: Mario Kleiner Reviewed-by: Marek Olšák --- src/gallium/state_trackers/dri/dri2.c | 28 1 file changed, 28 insertions(+) diff --git a/src/gallium/state_trackers/dri/dri2.c b/src/gallium/state_trackers/dri/dri2.c index d5ae9cb..f7fd08d 100644 --- a/src

[Mesa-dev] [PATCH 21/22] st/dri: Add option to control exposure of 10 bpc color configs.

Some clients may not like rgb10 fbconfigs and visuals. Support driconf option 'allow_rgb10_configs' on gallium to allow per application enable/disable. The option defaults to enabled. Signed-off-by: Mario Kleiner Reviewed-by: Marek Olšák --- src/gallium/auxiliary/pipe-loader/driinfo_gallium.h

[Mesa-dev] [PATCH 22/22] mesa: Add GL_UNSIGNED_INT_2_10_10_10_REV OES read type for BGRX1010102.

As Marek noted, the GL_RGBA + GL_UNSIGNED_INT_2_10_10_10_REV type combo is also good for readback of BGRX1010102 framebuffers, not only for BGRA1010102 framebuffers for use with glReadPixels() under GLES, so add it for the GL_IMPLEMENTATION_COLOR_READ_TYPE_OES query. Successfully tested on gallium

[Mesa-dev] [PATCH 20/22] st/dri: Add support for BGR[A/X]1010102 formats.

Exposes RGBA 10 10 10 2 and 10 10 10 0 visuals and fbconfigs for rendering. Signed-off-by: Mario Kleiner Reviewed-by: Marek Olšák --- src/gallium/state_trackers/dri/dri_screen.c | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/gallium/state_trackers/dri/dr

[Mesa-dev] [PATCH 16/22] st/mesa: Handle BGR[A/X]1010102 formats.

Signed-off-by: Mario Kleiner Reviewed-by: Marek Olšák --- src/mesa/state_tracker/st_cb_fbo.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/state_tracker/st_cb_fbo.c b/src/mesa/state_tracker/st_cb_fbo.c index e2303b4..a982f87 100644 --- a/src/mesa/state_tracker/st_cb_fbo.c +

[Mesa-dev] [PATCH 19/22] st/dri: Support texture_from_pixmap for BGR[A/X]1010102 formats.

Signed-off-by: Mario Kleiner Reviewed-by: Marek Olšák --- src/gallium/state_trackers/dri/dri_drawable.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/gallium/state_trackers/dri/dri_drawable.c b/src/gallium/state_trackers/dri/dri_drawable.c index 92ce9d2..a5999be 100644 --- a/src/ga

[Mesa-dev] [PATCH 13/22] egl/wayland: Add Wayland drm support for RGB10 winsys buffers.

Successfully tested under Weston 3.0. Photometer confirms 10 rgb bits from rendering to display. Signed-off-by: Mario Kleiner Reviewed-by: Marek Olšák --- src/egl/drivers/dri2/platform_wayland.c | 37 --- src/egl/wayland/wayland-drm/wayland-drm.c | 6 + 2 file

[Mesa-dev] [PATCH 18/22] st/dri2: Add buffer handling for BGR[A/X]1010102 formats.

Signed-off-by: Mario Kleiner Reviewed-by: Marek Olšák --- src/gallium/state_trackers/dri/dri2.c | 13 + 1 file changed, 13 insertions(+) diff --git a/src/gallium/state_trackers/dri/dri2.c b/src/gallium/state_trackers/dri/dri2.c index f7fd08d..e3b9377 100644 --- a/src/gallium/state_

[Mesa-dev] [PATCH 15/22] egl/wayland: Add Wayland shm swrast support for RGB10 winsys buffers.

Signed-off-by: Mario Kleiner Reviewed-by: Marek Olšák --- src/egl/drivers/dri2/platform_wayland.c | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/egl/drivers/dri2/platform_wayland.c b/src/egl/drivers/dri2/platform_wayland.c index 7451027..4a0b8c2 100644

[Mesa-dev] [PATCH 14/22] egl/wayland: Add Wayland dmabuf support for RGB10 winsys buffers. (v2)

Successfully tested under Weston 3.0. Photometer confirms 10 rgb bits from rendering to display. v2: Rebased onto master for dri2_teardown_wayland(). Signed-off-by: Mario Kleiner Reviewed-by: Marek Olšák --- src/egl/drivers/dri2/egl_dri2.h | 2 ++ src/egl/drivers/dri2/platform_wayland

[Mesa-dev] [PATCH 10/22] egl/x11: Match depth 30 RGB visuals to 32-bit RGBA EGLConfigs.

Similar to the matching of 24 bit RGB visuals to 32-bit RGBA EGLConfigs, so X11 compositors won't alpha-blend any config with a destination alpha buffer during compositing. Additionally this fixes failure to select ARGB2101010 configs via eglChooseConfig() with EGL_ALPHA_BITS 2 on a depth 30 X-Scr

[Mesa-dev] [PATCH 09/22] mesa: Add GL_RGBA + GL_UNSIGNED_INT_2_10_10_10_REV for OES read type.

This format + type combo is good for BGRA1010102 framebuffers for use with glReadPixels() under GLES, so add it for the GL_IMPLEMENTATION_COLOR_READ_TYPE_OES query. Allows successful testing of 10 bpc / depth 30 rendering with dEQP test case dEQP-EGL.functional.wide_color.window_1010102_colorspace

[Mesa-dev] [PATCH 08/22] i965/screen: Honor 'allow_rgb10_configs' option. (v2)

Allows to prevent exposing RGB10 configs and visuals to clients. v2: Rename expose_rgb10_configs to allow_rgb10_configs, as suggested by Emil. Signed-off-by: Mario Kleiner Reviewed-by: Tapani Pälli --- src/mesa/drivers/dri/i965/intel_screen.c | 19 +++ 1 file changed, 19 in

[Mesa-dev] [PATCH 12/22] egl/x11: Handle depth 30 drawables for EGL_KHR_image_pixmap.

Enables eglCreateImageKHR() with target set to EGL_NATIVE_PIXMAP_KHR to handle color depth 30 X11 drawables. Note that in theory the drawable depth 32 case in the current implementation is ambiguous: A depth 32 drawable could be of format ARGB or ARGB2101010, therefore an assignment of __DRI_I

[Mesa-dev] [PATCH 11/22] egl/x11: Handle depth 30 drawables under software rasterizer.

For fixing eglCreateWindowSurface() under swrast, as tested with LIBGL_ALWAYS_SOFTWARE=1. Suggested-by: Eric Engestrom Signed-off-by: Mario Kleiner Reviewed-by: Tapani Pälli Reviewed-by: Marek Olšák --- src/egl/drivers/dri2/platform_x11.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sr

[Mesa-dev] [PATCH 07/22] dri/common: Add option to allow exposure of 10 bpc color configs. (v2)

Some clients may not like RGB10X2 and RGB10A2 fbconfigs and visuals. Add a new driconf option 'allow_rgb10_configs' to allow per application enable/disable. The option defaults to enabled. v2: Rename expose_rgb10_configs to allow_rgb10_configs, as suggested by Emil. Add comment to option pars

[Mesa-dev] [PATCH 05/22] i965/screen: Add XRGB2101010 and ARGB2101010 support for DRI3.

Allow DRI3/Present buffer sharing for 10 bpc buffers. Otherwise composited desktops under DRI3 will only display black client areas for redirected windows. Signed-off-by: Mario Kleiner Reviewed-by: Tapani Pälli --- src/mesa/drivers/dri/i965/intel_screen.c | 6 ++ 1 file changed, 6 insertion

[Mesa-dev] [PATCH 02/22] i965: Support accelerated blit for depth 30 formats. (v2)

Extend intel_miptree_blit() to handle at least ARGB2101010 -> XRGB2101010, ARGB2101010 -> ARGB2101010, and XRGB2101010 -> XRGB2101010 via the BLT engine, but not XRGB2101010 -> ARGB2101010 yet. This works as tested under Compiz, KDE-5, Gnome-Shell. v2: Restrict BLT fast path to exclude XRGB210101

[Mesa-dev] [PATCH 01/22] i965: Support xrgb/argb2101010 formats for glx_texture_from_pixmap.

Makes compositing under X11/GLX work. Signed-off-by: Mario Kleiner Reviewed-by: Tapani Pälli --- src/mesa/drivers/dri/i965/intel_tex_image.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 03/22] dri: Add 10 bpc formats as available formats. (v2)

Used to support ARGB2101010 and XRGB2101010 winsys framebuffers / drawables, but added other 10 bpc fourcc's as well for consistency with definitions in wayland_drm.h, gbm.h, and drm_fourcc.h. v2: Align new defines with tabs instead of spaces, for consistency with remainder of that block of de

[Mesa-dev] [PATCH 04/22] loader/dri3: Add XRGB2101010 and ARGB2101010 support.

To allow DRI3/Present buffer sharing for 10 bpc buffers. Signed-off-by: Mario Kleiner Reviewed-by: Tapani Pälli Reviewed-by: Marek Olšák --- src/loader/loader_dri3_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/loader/loader_dri3_helper.c b/src/loader/loader_dri3_helper.c i

[Mesa-dev] Mesa 30 bit color depth patches, rev 4.

This is mostly the same as the last series rev 3, with the following changes: 1. Rebased onto current master, some trivial merge conflict resolved. 2. R-b's of Tapani and Marek tacked onto all patches. Only the new patch 22/22 is new and unreviewed. 3. Following Tapani's suggestion i moved ol

[Mesa-dev] [PATCH 06/22] i965/screen: Add basic support for rendering 10 bpc/depth 30 framebuffers. (v3)

Expose formats which are supported at least back to Gen 5 Ironlake, possibly further. Allow creation of 10 bpc winsys buffers for drawables. glxinfo now lists new RGBA 10 10 10 2/0 formats. v2: Move the BGRA/BGRX1010102 formats before the RGBA/RGBX 32 bit formats, as the code comments req

Re: [Mesa-dev] [PATCH 2/2] RFC i965: Share the GTT between non-robust contexts

Quoting Jason Ekstrand (2017-12-15 17:38:10) > On Fri, Dec 15, 2017 at 8:27 AM, Chris Wilson > wrote: > > Quoting Jason Ekstrand (2017-12-15 16:21:42) > > On Fri, Dec 15, 2017 at 5:42 AM, Chris Wilson > wrote: > > > >     Every client (everyone instance that opens /dev/dri/c

Re: [Mesa-dev] [PATCH] travis: use LLVM 5.0 for Meson Vulkan

Quoting Gert Wollny (2017-12-15 11:30:07) > Am Freitag, den 15.12.2017, 18:49 +0100 schrieb Gert Wollny: > > Am Freitag, den 15.12.2017, 17:17 +0100 schrieb Juan A. Suarez > > Romero: > > > Travis CI has moved to LLVM 5.0, and meson is detecting > > > automatically > > > the available version. > >

Re: [Mesa-dev] [PATCH] drirc: add option to disable ARB_draw_indirect

On 15.12.2017 12:37, Rob Clark wrote: On Fri, Dec 15, 2017 at 4:41 AM, Nicolai Hähnle wrote: On 15.12.2017 00:56, Rob Clark wrote: On Wed, Dec 6, 2017 at 3:31 PM, Ian Romanick wrote: On 12/05/2017 08:25 AM, Ilia Mirkin wrote: On Tue, Dec 5, 2017 at 8:18 AM, Emil Velikov wrote: Hi Rob,

Re: [Mesa-dev] [PATCH] travis: use LLVM 5.0 for Meson Vulkan

Am Freitag, den 15.12.2017, 18:49 +0100 schrieb Gert Wollny: > Am Freitag, den 15.12.2017, 17:17 +0100 schrieb Juan A. Suarez > Romero: > > Travis CI has moved to LLVM 5.0, and meson is detecting > > automatically > > the available version. > > Considering that LLVM 5.0 is obviously not properly m

Re: [Mesa-dev] [PATCH] travis: use LLVM 5.0 for Meson Vulkan

Quoting Emil Velikov (2017-12-15 09:35:03) > > Not to mention that distributions (Debian for example) allow multiple > versions to coexist, naming the binary - llvm-config-$version. > Just to add information, meson will try (with 0.44.0): llvm-config, reversed(llvm-config-${3.5-5.0}), reversed(l

Re: [Mesa-dev] [PATCH] travis: use LLVM 5.0 for Meson Vulkan

Quoting Emil Velikov (2017-12-15 09:35:03) > On 15 December 2017 at 16:49, Eric Engestrom > wrote: > > On Friday, 2017-12-15 17:17:55 +0100, Juan A. Suarez Romero wrote: > >> Travis CI has moved to LLVM 5.0, and meson is detecting automatically > >> the available version. > >> > >> So just let's

[Mesa-dev] [PATCH v3 4/4] meson: set opencl flags for r600

Signed-off-by: Dylan Baker --- src/gallium/drivers/r600/meson.build | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/r600/meson.build b/src/gallium/drivers/r600/meson.build index 2132dbb33ad..5899518a2e8 100644 --- a/src/gallium/drivers/r600/meson.bu

[Mesa-dev] [PATCH v3 1/4] meson: Build SWR driver

This enables the SWR driver, but doesn't actually hook it up to any of the targets yet. I felt like this patch was big and complicated enough without adding that. v2: - Fix typo 'delemeited' -> 'delimited' (Eric E) - Fix type 'errror' -> 'error' (Eric E) - Use variables to hold files inste

[Mesa-dev] [PATCH v3 2/4] meson: Turn on swr for relevant targets

Currently that's dri, libgl-xlib, and osmesa. v2: - put drivers on a separate line from normal dependencies (Eric E) cc: George Kyriazis cc: Tim Rowley cc: Bruce Cherniak Signed-off-by: Dylan Baker Reviewed-by: Eric Engestrom --- George, Tim, and Bruce, I don't know if you guys have any ti

[Mesa-dev] [PATCH v3 3/4] meson: build clover

This has only been compile tested. v2: - Have a single option for opencl (Eric E) - fix typo "tgis" -> "tgsi" (Curro) - Don't add "lib" to pipe loader libraries, which matches the autotools behavior v3: - Remove trailing whitespace - Make PIPE_SEARCH_DIR an absolute path cc: Cur

Re: [Mesa-dev] [PATCH v2 3/4] meson: build clover

Quoting Jan Vesely (2017-12-14 11:58:03) > > I use a symlink from install target to build dir to make it work on > autotools build. > My point was that meson defines PIPE_SEARCH_DIR to be relative path > '-DPIPE_SEARCH_DIR="lib64/gallium-pipe"' > even if I configure meson using --prefix=$HOME/.loc

Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround

On Thu, Dec 14, 2017 at 07:39:46PM +0200, kevin.rogo...@intel.com wrote: > From: Kevin Rogovin > > This patch series implements a needed workaround for Gen9 for ASTC5x5 > sampler reads. The crux of the work around is to make sure that the > sampler does not read an ASTC5x5 texture and a surface w

Re: [Mesa-dev] [PATCH 22/22] st/dri: Add option to control exposure of 10 bpc color configs.

Hi, about to push out a revision 4 of the series, which has all the r-b's of Tapani and Marek tacked on, rebased onto current master, and remaining suggestions by Tapani and Marek implemented and tested. That one should be totally ready to push if you are happy with it. Just one last test to

Re: [Mesa-dev] [PATCH] radv: remove useless radv_cmask_info::base_address_reg

Reviewed-by: Bas Nieuwenhuizen On Fri, Dec 15, 2017 at 6:54 PM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_private.h | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h > index 2e1362c446

[Mesa-dev] [PATCH] radv: remove useless radv_cmask_info::base_address_reg

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_private.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 2e1362c446..1017266efd 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1256,7

Re: [Mesa-dev] [PATCH] travis: use LLVM 5.0 for Meson Vulkan

Am Freitag, den 15.12.2017, 17:17 +0100 schrieb Juan A. Suarez Romero: > Travis CI has moved to LLVM 5.0, and meson is detecting automatically > the available version. Considering that LLVM 5.0 is obviously not properly made available in the travis-ci environment, I've reported the problem with tr

Re: [Mesa-dev] [PATCH 2/2] RFC i965: Share the GTT between non-robust contexts

On Fri, Dec 15, 2017 at 8:27 AM, Chris Wilson wrote: > Quoting Jason Ekstrand (2017-12-15 16:21:42) > > On Fri, Dec 15, 2017 at 5:42 AM, Chris Wilson > wrote: > > > > Every client (everyone instance that opens /dev/dri/card0 or the > render > > nodes), receives a unique per-process GTT (

Re: [Mesa-dev] [PATCH] travis: use LLVM 5.0 for Meson Vulkan

On 15 December 2017 at 16:49, Eric Engestrom wrote: > On Friday, 2017-12-15 17:17:55 +0100, Juan A. Suarez Romero wrote: >> Travis CI has moved to LLVM 5.0, and meson is detecting automatically >> the available version. >> >> So just let's change to LLVM 5.0 for this case. > > I thought we were us

Re: [Mesa-dev] [PATCH] travis: use LLVM 5.0 for Meson Vulkan

On Friday, 2017-12-15 17:17:55 +0100, Juan A. Suarez Romero wrote: > Travis CI has moved to LLVM 5.0, and meson is detecting automatically > the available version. > > So just let's change to LLVM 5.0 for this case. I thought we were using 3.9 on purpose, to test our minimum required llvm version

Re: [Mesa-dev] [PATCH 00/20] swr: update rasterizer

Reviewed-by: Bruce Cherniak > On Dec 14, 2017, at 3:34 PM, Tim Rowley wrote: > > Highlights include simd16 work, thread pool initialization rework, > and code cleanup. > > Tim Rowley (20): > swr/rast: Remove unneeded copy of gather mask > swr/rast: Binner fixes for viewport index offset han

Re: [Mesa-dev] [PATCH 2/2] RFC i965: Share the GTT between non-robust contexts

Quoting Jason Ekstrand (2017-12-15 16:21:42) > On Fri, Dec 15, 2017 at 5:42 AM, Chris Wilson > wrote: > > Every client (everyone instance that opens /dev/dri/card0 or the render > nodes), receives a unique per-process GTT (where supported by the > hardware, unfortunately that means o

[Mesa-dev] [PATCH] swr: Account for VBO index_bias in offsets

Account for info.index_bias when calculating buffers offsets. Fixes the follow piglit tests: arb_draw_elements_base_vertex-drawelements-user_varrays arb_draw_elements_base_vertex-negative-index-user_varrays --- src/gallium/drivers/swr/swr_state.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 d

Re: [Mesa-dev] [PATCH 2/2] RFC i965: Share the GTT between non-robust contexts

On Fri, Dec 15, 2017 at 5:42 AM, Chris Wilson wrote: > Every client (everyone instance that opens /dev/dri/card0 or the render > nodes), receives a unique per-process GTT (where supported by the > hardware, unfortunately that means only Broadwell and later). Every > context created by each client

[Mesa-dev] [PATCH] travis: use LLVM 5.0 for Meson Vulkan

Travis CI has moved to LLVM 5.0, and meson is detecting automatically the available version. So just let's change to LLVM 5.0 for this case. --- .travis.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.travis.yml b/.travis.yml index 211df3ec1ef..20432361176 100644 ---

Re: [Mesa-dev] [PATCH 2/2] RFC i965: Share the GTT between non-robust contexts

Quoting Jason Ekstrand (2017-12-15 15:40:51) > What does this actually gain us? Multiple contexts aren't common. UE4 is one that I know of that uses multiple contexts to separate rendering from presentation, afaik. The API is precursor to try and define a lighterweight context object for future e

Re: [Mesa-dev] [PATCH] anv: fix bug when VK_REMAINING_ARRAY_LAYERS is used in vkCmdClearAttachments()

Ugh... The problem here is that we may not know the framebuffer in CmdCearAttachments if it's in a secondary command buffer. I'm not actually sure what to do in that case. I guess we could store the number of later somewhere and teach blorp how to do an indirect draw. Really, I think it make

Re: [Mesa-dev] [PATCH] loader/dri3: Try to make sure we only process our own NotifyMSC events

Ping (sorry I forgot to mark this as v2 in the subject) On 2017-11-23 10:26 AM, Michel Dänzer wrote: > From: Michel Dänzer > > We were using a sequence counter value to wait for a specific NotifyMSC > event. However, we can receive events from other clients as well, which > may already be usin

Re: [Mesa-dev] [PATCH 2/2] RFC i965: Share the GTT between non-robust contexts

What does this actually gain us? Multiple contexts aren't common. On December 15, 2017 05:43:09 Chris Wilson wrote: Every client (everyone instance that opens /dev/dri/card0 or the render nodes), receives a unique per-process GTT (where supported by the hardware, unfortunately that means onl

Re: [Mesa-dev] [PATCH] Revert "radv: do not load unused gl_LocalInvocationID/gl_WorkGroupID components"

Tested-by: Alex Smith On 15 December 2017 at 15:01, Samuel Pitoiset wrote: > This reverts commit 2294d35b243dee15af15895e876a63b7d22e48cc. > > We can't do this without adjusting the input SGPRs/VGPRs logic. > For now, just revert it. I will send a proper solution later. > > It fixes a rendering

[Mesa-dev] [PATCH] Revert "radv: do not load unused gl_LocalInvocationID/gl_WorkGroupID components"

This reverts commit 2294d35b243dee15af15895e876a63b7d22e48cc. We can't do this without adjusting the input SGPRs/VGPRs logic. For now, just revert it. I will send a proper solution later. It fixes a rendering issue in F1 2017 that CTS didn't catch up. Signed-off-by: Samuel Pitoiset --- src/amd

[Mesa-dev] [PATCH 1/2] amd/common: add ac_get_cb_shader_mask() helper

Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_shader_util.c | 35 + src/amd/common/ac_shader_util.h | 3 +++ src/amd/vulkan/radv_pipeline.c | 34 +--- src/gallium/drivers/radeonsi/si_state_shaders

[Mesa-dev] [PATCH 2/2] amd/common: add ac_vgt_gs_mode() helper

Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_shader_util.c | 27 + src/amd/common/ac_shader_util.h | 6 + src/amd/vulkan/radv_pipeline.c | 32 + src/gallium/drivers/radeonsi/si_state_shaders.

[Mesa-dev] [PATCH 2/2] RFC i965: Share the GTT between non-robust contexts

Every client (everyone instance that opens /dev/dri/card0 or the render nodes), receives a unique per-process GTT (where supported by the hardware, unfortunately that means only Broadwell and later). Every context created by each client, in turns receives its own unique ppGTT. This is overkill in t

[Mesa-dev] [PATCH 1/2] i965: Always try to create a logical context

Always enable use of HW logical contexts to preserve GPU state between batches when the kernel supports such constructs, continuing to enforce the required support for gen6+. At runtime, this effectively removes the BRW_NEW_CONTEXT flag (and the upload of invariant state) from the start of every b

[Mesa-dev] travis-ci: meson build expects LLVM 5.0, but travis profile provides 3.9

Currently, the first build fails with meson encountered an error in file meson.build, line 976, column 2: Could not generate link_args for config-tool. llvm-config: error: libLLVM-5.0.so is missing https://travis-ci.org/gerddie/mesa/jobs/316902885 Best, Gert

Re: [Mesa-dev] [PATCH] drirc: add option to disable ARB_draw_indirect

On Fri, Dec 15, 2017 at 4:41 AM, Nicolai Hähnle wrote: > On 15.12.2017 00:56, Rob Clark wrote: >> >> On Wed, Dec 6, 2017 at 3:31 PM, Ian Romanick wrote: >>> >>> On 12/05/2017 08:25 AM, Ilia Mirkin wrote: On Tue, Dec 5, 2017 at 8:18 AM, Emil Velikov wrote: > > Hi Rob, >

[Mesa-dev] [PATCH] anv: fix bug when VK_REMAINING_ARRAY_LAYERS is used in vkCmdClearAttachments()

Blorp was not supporting the use of the constant VK_REMAINING_ARRAY_LAYERS (whose value is ~0) in the VkClearRect structure. If we receive it, we need to calculate the layer count as the image layers count minus the base array layer. Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/

Re: [Mesa-dev] [PATCH] util: scons: wire up the sha1 test

Ugh! How did we miss this? This is: Reviewed-by: Andres Gomez On Thu, 2017-12-14 at 19:10 +, Emil Velikov wrote: > From: Emil Velikov > > Cc: > Fixes: 513d7ffa23d ("util: Add a SHA1 unit test program") > Signed-off-by: Emil Velikov > --- > We want this and the original commit for stable

Re: [Mesa-dev] [RFC libdrm 0/5] Move alloc_handle_t from gralloc impls.

+Kalyan Kondapally On Wed, 2017-12-13 at 15:02 -0800, Gurchetan Singh wrote: > Hi Robert, > > Thanks for looking into this! We need to decide if we want: > > (1) A common struct that implementations can subclass, i.e: > > struct blah_gralloc_handle { > alloc_handle_t alloc_handle; > in

Re: [Mesa-dev] [PATCH 3/3] radeonsi: don't call force_dcc_off for buffers

On 2017-12-12 10:47 PM, Marek Olšák wrote: > From: Marek Olšák > > This was undefined yet harmless behavior in LLVM. > Not anymore - it causes a hang now. > > Cc: 17.3 Not sure about backporting this to the 17.3 branch, since that doesn't support LLVM 6. OTOH might be nice to add some bugzilla

Re: [Mesa-dev] [PATCH] drirc: add option to disable ARB_draw_indirect

On 15.12.2017 00:56, Rob Clark wrote: On Wed, Dec 6, 2017 at 3:31 PM, Ian Romanick wrote: On 12/05/2017 08:25 AM, Ilia Mirkin wrote: On Tue, Dec 5, 2017 at 8:18 AM, Emil Velikov wrote: Hi Rob, On 5 December 2017 at 12:54, Rob Clark wrote: This is a bit sad/annoying. But with current GPU