On my list
On Jan 5, 2017 7:51 PM, "Ben Widawsky" wrote:
> On 17-01-02 18:37:17, Ben Widawsky wrote:
>
>> v2: Put the commit message as a comment (Topi)
>>
>> Cc: Topi Pohjolainen
>> Cc: Ville Syrjälä
>> Cc: Jason Ekstrand
>> Signed-off-by: Ben Widawsky
>> Acked-by: Daniel Stone
>> ---
>> s
On 17-01-02 18:37:17, Ben Widawsky wrote:
v2: Put the commit message as a comment (Topi)
Cc: Topi Pohjolainen
Cc: Ville Syrjälä
Cc: Jason Ekstrand
Signed-off-by: Ben Widawsky
Acked-by: Daniel Stone
---
src/mesa/drivers/dri/i965/intel_screen.c | 5 -
1 file changed, 4 insertions(+), 1 del
On 12/23/2016 08:15 AM, Samuel Pitoiset wrote:
> This series makes use of the scheduling control code in order to improve the
> instruction pipelining on Maxwell GPUs.
Tested this on Jetson TX1. The performance improvement on glmark2 was
only marginal, with terrain going from 7 to 10 fps at pstate
With minor nits that patch 5 applies to Transpose16_16 (not Transform_16_16);
and patch 6 changes the function declaration 2nd-line whitespace of
OutputMerger4x2 and OutputMerger8x2 (we can fix this in a follow-on checking to
core)
Reviewed-by: Bruce Cherniak
> On Jan 5, 2017, at 5:19 PM, Ti
From: Rainer Hochecker
This allows eglCreateImageKHR to access P010 surfaces created by vaapi
Signed-off-by: Rainer Hochecker
---
include/GL/internal/dri_interface.h | 4
src/egl/drivers/dri2/egl_dri2.c | 10 ++
src/mesa/drivers/dri/common/dri_util.c | 4
sr
Updated mesa patch after changes in fourcc
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On 17-01-05 17:55:15, Topi Pohjolainen Topi Pohjolainen wrote:
On Wed, Jan 04, 2017 at 06:36:05PM -0800, Ben Widawsky wrote:
On 17-01-04 10:41:58, Topi Pohjolainen Topi Pohjolainen wrote:
> On Mon, Jan 02, 2017 at 06:37:22PM -0800, Ben Widawsky wrote:
> > v2: Try to keep the assert as recommende
Build mesa 3056 completed
Commit caf18a8434 by Roland Scheidegger on 1/5/2017 11:46 PM:
gallivm: (trivial) fix typo bug with small AoS format unpacking\n\nFix typo using wrong (uninitialized) build context introduced by\n4634cb5921b985f04f2daf00cda2d28036143bd3
Am 06.01.2017 um 00:00 schrieb Marek Olšák:
> On Thu, Jan 5, 2017 at 10:06 PM, Roland Scheidegger
> wrote:
>> Am 05.01.2017 um 21:50 schrieb Samuel Pitoiset:
>>>
>>>
>>> On 01/05/2017 09:44 PM, Marek Olšák wrote:
On Thu, Jan 5, 2017 at 9:00 PM, Roland Scheidegger
wrote:
> Am 05.01.
Marking operations as redundant if they are equal to the base
range is fine when the tree structure is something like this:
max
/ \
max b
/ \
3max
/ \
3 a
But the opt falls apart with a tree like this:
max
/ \
max
Fix incorrect swizzling in SIMD16 Transform_16_16 breaking the
two-channel 16-bpc formats like R16G16_FLOAT.
---
src/gallium/drivers/swr/rasterizer/core/utils.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/utils.h
b/src/gallium/dr
Fix routines for 8-bit and 16-bit formats used by optimized tile store.
---
.../drivers/swr/rasterizer/common/simd16intrin.h | 8 +-
.../drivers/swr/rasterizer/common/simdintrin.h | 36 +
.../drivers/swr/rasterizer/core/format_types.h | 86 ++
3 files changed
Signed-off-by: Eric Engestrom
---
src/mesa/drivers/dri/common/drirc | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/common/drirc
b/src/mesa/drivers/dri/common/drirc
index af84ee82e8..97297b7a1c 100644
--- a/src/mesa/drivers/dri/common/dri
Honor the colorHottileEnable mask when accessing colorBuffer pointers.
---
src/gallium/drivers/swr/rasterizer/core/backend.cpp | 20 ++--
src/gallium/drivers/swr/rasterizer/core/backend.h | 18 --
2 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/sr
Fixed Transpose_16 methods of following formats:
Transpose8_8_8_8
Transpose8_8
Transpose32_32
Transpose16_16_16_16
Transpose16_16_16
Transpose16_16
---
.../drivers/swr/rasterizer/common/simd16intrin.h | 93 -
.../drivers/swr/rasterizer/common/simdintrin.h | 18 +-
src/gallium/driv
---
src/gallium/drivers/swr/rasterizer/core/backend.cpp | 12 ++--
src/gallium/drivers/swr/rasterizer/core/backend.h | 6 +++---
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/backend.cpp
b/src/gallium/drivers/swr/rasterizer/core/
Mostly avx512/simd16 fixes.
Tim Rowley (6):
swr: [rasterizer core] whitespace adjustments
swr: [rasterizer core] fix SIMD16 transpose functions
swr: [rasterizer core] fix SIMD16 PackTraits pack() and unpack()
swr: [rasterizer core] fix SIMD16 output merger
swr: [rasterizer core] fix SIMD
---
src/gallium/drivers/swr/rasterizer/core/clip.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/clip.h
b/src/gallium/drivers/swr/rasterizer/core/clip.h
index fcb2ecb..085e4a9 100644
--- a/src/gallium/drivers/swr/rasterizer/core/clip
Build mesa 3055 failed
Commit 4634cb5921 by Roland Scheidegger on 12/21/2016 3:56 AM:
gallivm: implement aos unpack (to unorm8) for small unorm formats\n\nUsing bit replication. This path now resembles something which might make\nsense. (The logic was mostly co
On Thu, Jan 5, 2017 at 10:06 PM, Roland Scheidegger wrote:
> Am 05.01.2017 um 21:50 schrieb Samuel Pitoiset:
>>
>>
>> On 01/05/2017 09:44 PM, Marek Olšák wrote:
>>> On Thu, Jan 5, 2017 at 9:00 PM, Roland Scheidegger
>>> wrote:
Am 05.01.2017 um 20:43 schrieb Samuel Pitoiset:
>
>
>
https://bugs.freedesktop.org/show_bug.cgi?id=98242
--- Comment #8 from Kenneth Graunke ---
Here's an updated version of that patch which passes the "line_expression"
tests in addition to the "line_and_file_expression" tests. I haven't tested it
further, and am not advocating one way or another..
On 17-01-05 12:16:45, Chad Versace wrote:
This patch has a regressing side-effect: it disables CCS for all single-sample
miptrees created by glRenderbufferStorage(). After stepping through some Piglit
tests, I believe the problem is that line 161 below always returns false for
such miptrees becau
On Thursday, January 5, 2017 11:29:40 AM PST Kenneth Graunke wrote:
> Just check the screen feature bitfield.
>
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/brw_conditional_render.c | 2 +-
> src/mesa/drivers/dri/i965/brw_context.h| 1 -
> src/mesa/drivers/dri/i
On Thu 05 Jan 2017, Tapani Pälli wrote:
> Currently we do this only in the fallback code (when tiled memcpy
> version failed) but it needs to be done always so that we have
> correct read and write buffer in place. No regressions seen in CI.
>
> Fixes:
> dEQP-EGL.functional.buffer_age.*
>
>
On Wed, Jan 4, 2017 at 9:31 PM, Timothy Arceri wrote:
> There was a bit to take in here but it seems ok to me. I've made a
> bunch of trivial suggestions/comments below otherwise:
>
> Reviewed-by: Timothy Arceri
>
> On Mon, 2016-12-12 at 19:39 -0800, Jason Ekstrand wrote:
> > ---
> > src/compil
---
src/egl/generate/eglFunctionList.py | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/egl/generate/eglFunctionList.py
b/src/egl/generate/eglFunctionList.py
index b19b5f7..80cb834 100644
--- a/src/egl/generate/eglFunctionList.py
+++ b/src/egl/generate/eglFunctionLis
Reviewed-by: Timothy Arceri
On Thu, 2017-01-05 at 12:05 -0800, Kenneth Graunke wrote:
> A while ago, we stopped using Luca's GLSL IR lower_jumps pass in
> favor
> of nir_lower_returns(). Marek's commit
> d3cb79e043338b0e55a3fba8df652f3
> put it in do_common_optimization, which resulted in us cal
On 01/05/2017 10:06 PM, Roland Scheidegger wrote:
Am 05.01.2017 um 21:50 schrieb Samuel Pitoiset:
On 01/05/2017 09:44 PM, Marek Olšák wrote:
On Thu, Jan 5, 2017 at 9:00 PM, Roland Scheidegger
wrote:
Am 05.01.2017 um 20:43 schrieb Samuel Pitoiset:
On 01/05/2017 06:49 PM, Roland Scheideg
Am 05.01.2017 um 21:50 schrieb Samuel Pitoiset:
>
>
> On 01/05/2017 09:44 PM, Marek Olšák wrote:
>> On Thu, Jan 5, 2017 at 9:00 PM, Roland Scheidegger
>> wrote:
>>> Am 05.01.2017 um 20:43 schrieb Samuel Pitoiset:
On 01/05/2017 06:49 PM, Roland Scheidegger wrote:
> Meh, I'm not
On Thu, Jan 5, 2017 at 12:39 PM, Jason Ekstrand
wrote:
> On Thu, Jan 5, 2017 at 2:18 AM, Samuel Iglesias Gonsálvez <
> sigles...@igalia.com> wrote:
>
>> We need to pick two 32-bit values per component to perform the right
>> shuffle operation.
>>
>> v2 (Jason):
>> - Add assert to check matching b
On Thu, Jan 5, 2017 at 2:18 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:
> From: "Juan A. Suarez Romero"
>
> So far, input_reads was a bitmap tracking which vertex input locations
> were being used.
>
> In OpenGL, an attribute bigger than a vec4 (like a dvec3 or dvec4)
> consumes
On 01/05/2017 09:44 PM, Marek Olšák wrote:
On Thu, Jan 5, 2017 at 9:00 PM, Roland Scheidegger wrote:
Am 05.01.2017 um 20:43 schrieb Samuel Pitoiset:
On 01/05/2017 06:49 PM, Roland Scheidegger wrote:
Meh, I'm not really a big fan of such hacks. GPUs have support for NaNs
since ages, and wh
Christian König wrote:
Am 04.01.2017 um 18:13 schrieb Nayan Deshmukh:
dri3 allows us to send handle of a texture directly to X
so this patch allows a state tracker to directly send its
texture to X to be used as back buffer and avoids extra
copying
v2: use clip width/height to display a portion
With the image_ms_array line removed (I don't believe we support that),
20-22 are
Reviewed-by: Jason Ekstrand
On Thu, Jan 5, 2017 at 12:44 PM, Jason Ekstrand
wrote:
> You're doing more here than enabling float64...
>
> On Thu, Jan 5, 2017 at 2:18 AM, Samuel Iglesias Gonsálvez <
> sigles...@iga
On Thu, Jan 5, 2017 at 9:00 PM, Roland Scheidegger wrote:
> Am 05.01.2017 um 20:43 schrieb Samuel Pitoiset:
>>
>>
>> On 01/05/2017 06:49 PM, Roland Scheidegger wrote:
>>> Meh, I'm not really a big fan of such hacks. GPUs have support for NaNs
>>> since ages, and while glsl is lenient the point sta
You're doing more here than enabling float64...
On Thu, Jan 5, 2017 at 2:18 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:
> Signed-off-by: Samuel Iglesias Gonsálvez
> ---
> src/intel/vulkan/anv_pipeline.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --gi
Reviewed-by: Jason Ekstrand
On Thu, Jan 5, 2017 at 2:18 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:
> We use *64*_PASSTHRU formats to upload vertex attributes of 64 bits
> to avoid conversions. From the BDW PRM, Volume 2d, page 586
> (VERTEX_ELEMENT_STATE):
>
> "When Source
On Thu, Jan 5, 2017 at 2:18 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:
> v2 (Jason):
> - Refactor nir_get_nir_type_for_glsl_type() to avoid using unneeded
> helpers (Jason)
>
> Signed-off-by: Samuel Iglesias Gonsálvez
> ---
> src/compiler/nir/nir.h | 27
On Thu, Jan 5, 2017 at 2:18 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:
> We need to pick two 32-bit values per component to perform the right
> shuffle operation.
>
> v2 (Jason):
> - Add assert to check matching bit sizes (Jason)
> - Simplify the code to pick components (Jason)
>
https://bugs.freedesktop.org/show_bug.cgi?id=99179
--- Comment #9 from APoliTech ---
Not realy. Because i teste on over 4 PC's with over 4 Ubuntu base destros
with different versions. And its the same problem. I beleave that in the
new version of mesa they change some packages names and when i am
On Thu, Jan 5, 2017 at 6:56 AM, Juan A. Suarez Romero
wrote:
> On Thu, 2017-01-05 at 06:41 -0800, Jason Ekstrand wrote:
>
> On Jan 5, 2017 3:11 AM, "Juan A. Suarez Romero"
> wrote:
>
> On Wed, 2017-01-04 at 07:06 -0800, Jason Ekstrand wrote:
>
> On Jan 4, 2017 5:46 AM, "Juan A. Suarez Romero"
>
https://bugs.freedesktop.org/show_bug.cgi?id=99214
Tim Rowley changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
https://bugs.freedesktop.org/show_bug.cgi?id=97102
Bruce Cherniak changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
This patch has a regressing side-effect: it disables CCS for all single-sample
miptrees created by glRenderbufferStorage(). After stepping through some Piglit
tests, I believe the problem is that line 161 below always returns false for
such miptrees because mt->is_scanout is true. I don't understan
On Thursday, January 5, 2017 2:19:15 PM PST Tapani Pälli wrote:
> Currently we do this only in the fallback code (when tiled memcpy
> version failed) but it needs to be done always so that we have
> correct read and write buffer in place. No regressions seen in CI.
>
> Fixes:
> dEQP-EGL.func
A while ago, we stopped using Luca's GLSL IR lower_jumps pass in favor
of nir_lower_returns(). Marek's commit d3cb79e043338b0e55a3fba8df652f3
put it in do_common_optimization, which resulted in us calling it again.
Dropping the EmitNoMainReturn setting makes us skip that pass again.
Apparently t
Am 05.01.2017 um 20:43 schrieb Samuel Pitoiset:
>
>
> On 01/05/2017 06:49 PM, Roland Scheidegger wrote:
>> Meh, I'm not really a big fan of such hacks. GPUs have support for NaNs
>> since ages, and while glsl is lenient the point stands that returning a
>> NaN is a more correct result, so doing e
On 01/05/2017 06:40 PM, Ilia Mirkin wrote:
On Thu, Jan 5, 2017 at 12:22 PM, Samuel Pitoiset
wrote:
Would be nice to test on Maxwell as well.
No ES 3.1 there (yet), so no tests. I probably should have just forced
it. Will do.
Will be there soon. :)
More comments inline.
Thanks.
On
On 01/05/2017 08:32 PM, Kenneth Graunke wrote:
On Thursday, January 5, 2017 5:47:37 PM PST Samuel Pitoiset wrote:
As explained by Nicolai, it seems like D3D always compute the
absolute value while GLSL says that the result of inversesqrt()
is undefined if x <= 0. Using the absolute value looks
On 01/05/2017 06:49 PM, Roland Scheidegger wrote:
Meh, I'm not really a big fan of such hacks. GPUs have support for NaNs
since ages, and while glsl is lenient the point stands that returning a
NaN is a more correct result, so doing extra work to get a wrong result
doesn't look all that great t
On 01/05/2017 06:37 PM, Marek Olšák wrote:
Shouldn't we also use abs for SQRT? For example, this adds abs for
both RSQ and SQRT:
https://cgit.freedesktop.org/~mareko/mesa/commit/?id=5e0fb661a8e6ac5f7b2245dd31595155128e0664
Yes, it makes more sense to do it for both even if we don't have any
On Thursday, January 5, 2017 5:47:37 PM PST Samuel Pitoiset wrote:
> As explained by Nicolai, it seems like D3D always compute the
> absolute value while GLSL says that the result of inversesqrt()
> is undefined if x <= 0. Using the absolute value looks like safer
> especially when the game has bee
Just check the screen feature bitfield.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_conditional_render.c | 2 +-
src/mesa/drivers/dri/i965/brw_context.h| 1 -
src/mesa/drivers/dri/i965/intel_extensions.c | 5 -
3 files changed, 1 insertion(+), 7 deletio
Predication needs cmd parser only on gen7. For newer platforms, it
should be available without it.
Signed-off-by: Rafael Antognolli
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/intel_screen.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Hi Rafael,
Your patch 1 looked
On Tuesday, December 13, 2016 2:50:58 PM PST Rafael Antognolli wrote:
> Enable the use of a transform feedback overflow query with
> glBeginConditionalRender. The render commands will only execute if the
> query is true (i.e. if there was an overflow).
>
> Use ARB_conditional_render_inverted to ch
On Tuesday, December 13, 2016 2:50:57 PM PST Rafael Antognolli wrote:
> Enable getting the results of a transform feedback overflow query with a
> buffer object.
>
> Signed-off-by: Rafael Antognolli
> ---
> src/mesa/drivers/dri/i965/hsw_queryobj.c | 108
> +++
> 1 fi
Reviewed-by: Bruce Cherniak
> On Jan 5, 2017, at 11:18 AM, Tim Rowley wrote:
>
> ---
> .../drivers/swr/rasterizer/common/formats.cpp | 104 ++---
> .../drivers/swr/rasterizer/common/formats.h| 4 +
> .../drivers/swr/rasterizer/core/format_traits.h| 88 +
Meh, I'm not really a big fan of such hacks. GPUs have support for NaNs
since ages, and while glsl is lenient the point stands that returning a
NaN is a more correct result, so doing extra work to get a wrong result
doesn't look all that great to me.
FWIW dx10 requires NaNs as results (for both sqr
This should allow us to resolve copy propagation faster,
as we don't need multiple runs of the pass when we have situations like:
foo = bar;
baz = foo;
---
src/compiler/glsl/opt_copy_propagation.cpp | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/compiler/glsl/opt_co
Map from ir_variable to acp_entry instead of from lhs to rhs.
Add a field in the acp_entry for the acp_entry of the ir_variable
that is meant to be a replacement for this ir_variable.
Insert both acp_entries in the table mapped to their own ir_variable.
This way we can use only one hash table, and
On Thu, Jan 5, 2017 at 12:22 PM, Samuel Pitoiset
wrote:
> Would be nice to test on Maxwell as well.
No ES 3.1 there (yet), so no tests. I probably should have just forced
it. Will do.
>
> More comments inline.
>
> Thanks.
>
>
> On 01/02/2017 07:01 AM, Ilia Mirkin wrote:
>> diff --git a/src/galli
Shouldn't we also use abs for SQRT? For example, this adds abs for
both RSQ and SQRT:
https://cgit.freedesktop.org/~mareko/mesa/commit/?id=5e0fb661a8e6ac5f7b2245dd31595155128e0664
Marek
On Thu, Jan 5, 2017 at 5:47 PM, Samuel Pitoiset
wrote:
> As explained by Nicolai, it seems like D3D always co
Would be nice to test on Maxwell as well.
More comments inline.
Thanks.
On 01/02/2017 07:01 AM, Ilia Mirkin wrote:
We don't need to support all the color buffers for advanced blend, just
cb0. For Fermi, we use the special binding slots so that we don't
overlap with user textures, while Kepler+
---
.../drivers/swr/rasterizer/common/formats.cpp | 104 ++---
.../drivers/swr/rasterizer/common/formats.h| 4 +
.../drivers/swr/rasterizer/core/format_traits.h| 88 +
src/gallium/drivers/swr/rasterizer/core/utils.h| 64 +
.../dr
Hi,
On 05.01.2017 01:55, Kenneth Graunke wrote:
On Wednesday, January 4, 2017 3:16:41 PM PST Eero Tamminen wrote:
Are there yet other use-cases for Vulkan tessellation besides Sacha
Willems' three tests here:
https://github.com/SaschaWillems/Vulkan
?
Does it matter? It's required for
On Thu, Jan 5, 2017 at 11:30 AM, Nicolai Hähnle wrote:
> On 05.01.2017 17:02, Ilia Mirkin wrote:
>>
>> On Thu, Jan 5, 2017 at 10:48 AM, Nicolai Hähnle
>> wrote:
>>>
>>> On 02.01.2017 21:41, Marek Olšák wrote:
On Mon, Jan 2, 2017 at 7:01 AM, Ilia Mirkin
wrote:
>
>
As explained by Nicolai, it seems like D3D always compute the
absolute value while GLSL says that the result of inversesqrt()
is undefined if x <= 0. Using the absolute value looks like safer
especially when the game has been ported from D3D to GL.
This gets rid of the NaN values in the "Spec Ops:
On Jan 5, 2017 10:20, "Samuel Iglesias Gonsálvez"
wrote:
We need to pick two 32-bit values per component to perform the right
shuffle operation.
v2 (Jason):
- Add assert to check matching bit sizes (Jason)
- Simplify the code to pick components (Jason)
Signed-off-by: Samuel Iglesias Gonsálvez
On 05.01.2017 17:02, Ilia Mirkin wrote:
On Thu, Jan 5, 2017 at 10:48 AM, Nicolai Hähnle wrote:
On 02.01.2017 21:41, Marek Olšák wrote:
On Mon, Jan 2, 2017 at 7:01 AM, Ilia Mirkin wrote:
Signed-off-by: Ilia Mirkin
---
src/gallium/auxiliary/tgsi/tgsi_info.c | 2 +-
src/gallium/docs/so
Mesa 13.0.3 is now available.
This series we have - multiple fixes for i965 and radeonsi. The ANV driver has
extra smoke testing fixes and memory leaks have been resolved.
Chad Versace (2):
i965/mt: Disable aux surfaces after making miptree shareable
egl: Fix crashes in eglCreate*Sur
On 01.01.2017 01:04, Marek Olšák wrote:
From: Marek Olšák
It's redundant with the source modifier.
This could have been split up, but oh well. Aside from Ilia's comment,
patches 4&5 are
Reviewed-by: Nicolai Hähnle
---
src/gallium/auxiliary/draw/draw_pipe_aaline.c | 2 +-
src/gall
On Thu, Jan 5, 2017 at 10:48 AM, Nicolai Hähnle wrote:
> On 02.01.2017 21:41, Marek Olšák wrote:
>>
>> On Mon, Jan 2, 2017 at 7:01 AM, Ilia Mirkin wrote:
>>>
>>> Signed-off-by: Ilia Mirkin
>>> ---
>>> src/gallium/auxiliary/tgsi/tgsi_info.c | 2 +-
>>> src/gallium/docs/source/tgsi.rst
On Wed, Jan 04, 2017 at 05:36:22PM -0800, Ben Widawsky wrote:
> On 17-01-04 09:51:20, Topi Pohjolainen Topi Pohjolainen wrote:
> > On Mon, Jan 02, 2017 at 06:37:13PM -0800, Ben Widawsky wrote:
> > > v2: Leave "image+mod" (Topi)
> > >
> > > Signed-off-by: Ben Widawsky
> > > Acked-by: Daniel Stone
On Wed, Jan 04, 2017 at 06:17:31PM -0800, Ben Widawsky wrote:
> On 17-01-04 10:57:40, Topi Pohjolainen Topi Pohjolainen wrote:
> > On Wed, Jan 04, 2017 at 10:26:50AM +0200, Pohjolainen, Topi wrote:
> > > On Mon, Jan 02, 2017 at 06:37:15PM -0800, Ben Widawsky wrote:
> > > > Allows us to continue uti
On Wed, Jan 04, 2017 at 05:58:46PM -0800, Ben Widawsky wrote:
> On 17-01-04 10:00:59, Topi Pohjolainen Topi Pohjolainen wrote:
> > On Mon, Jan 02, 2017 at 06:37:18PM -0800, Ben Widawsky wrote:
> > > In the foreseeable future it doesn't seem to make sense to have multiple
> > > resolve flags. What d
On Wed, Jan 04, 2017 at 06:36:05PM -0800, Ben Widawsky wrote:
> On 17-01-04 10:41:58, Topi Pohjolainen Topi Pohjolainen wrote:
> > On Mon, Jan 02, 2017 at 06:37:22PM -0800, Ben Widawsky wrote:
> > > v2: Try to keep the assert as recommended by Topi. This requires
> > > modifying the num_samples che
Reviewed-by: Nicolai Hähnle
On 02.01.2017 07:01, Ilia Mirkin wrote:
This implements support for emitting FBFETCH ops, using the existing
lowering pass for advanced blend logic, and disabling hw blend when
advanced blending is enabled.
Signed-off-by: Ilia Mirkin
---
src/mesa/state_tracker/st_
On 02.01.2017 07:01, Ilia Mirkin wrote:
This is so that we can differentiate between flushing any framebuffer
reading caches from regular sampler caches.
Signed-off-by: Ilia Mirkin
---
This felt too simple and silly to create an extra callback for, especially
since the implementations that rel
On 02.01.2017 21:41, Marek Olšák wrote:
On Mon, Jan 2, 2017 at 7:01 AM, Ilia Mirkin wrote:
Signed-off-by: Ilia Mirkin
---
src/gallium/auxiliary/tgsi/tgsi_info.c | 2 +-
src/gallium/docs/source/tgsi.rst | 11 +++
src/gallium/include/pipe/p_shader_tokens.h | 2 +-
3 file
Am 05.01.2017 um 15:30 schrieb Nayan Deshmukh:
This fixes the mistake introduced in commit
b6737a8bcd03ea68952799144c0c6e6e6679bee9
Signed-off-by: Nayan Deshmukh
Reviewed-by: Christian König .
---
src/gallium/state_trackers/va/context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
That Deus Ex number is impressive. For the series:
Reviewed-by: Nicolai Hähnle
On 02.01.2017 23:54, Marek Olšák wrote:
From: Marek Olšák
Draw calls no longer flush SDMA IBs. r600_need_dma_space is
responsible for synchronizing execution between both IBs.
Initial buffer clears and fast clear
On 01/05/2017 05:21 AM, Christian König wrote:
Am 04.01.2017 um 18:13 schrieb Nayan Deshmukh:
dri3 allows us to send handle of a texture directly to X
so this patch allows a state tracker to directly send its
texture to X to be used as back buffer and avoids extra
copying
v2: use clip width/h
On 01.01.2017 01:05, Marek Olšák wrote:
From: Marek Olšák
useful for radeonsi performance counters
---
src/gallium/auxiliary/hud/hud_context.c | 40 -
1 file changed, 30 insertions(+), 10 deletions(-)
diff --git a/src/gallium/auxiliary/hud/hud_context.c
b/src/
On Thu, 2017-01-05 at 06:41 -0800, Jason Ekstrand wrote:
> On Jan 5, 2017 3:11 AM, "Juan A. Suarez Romero"
> wrote:
> On Wed, 2017-01-04 at 07:06 -0800, Jason Ekstrand wrote:
> > On Jan 4, 2017 5:46 AM, "Juan A. Suarez Romero" > m> wrote:
> > On Tue, 2017-01-03 at 14:41 -0800, Jason Ekstrand wrot
On Jan 5, 2017 3:11 AM, "Juan A. Suarez Romero" wrote:
On Wed, 2017-01-04 at 07:06 -0800, Jason Ekstrand wrote:
On Jan 4, 2017 5:46 AM, "Juan A. Suarez Romero" wrote:
On Tue, 2017-01-03 at 14:41 -0800, Jason Ekstrand wrote:
I made a few pretty trivial comments. With those addressed,
Reviewe
This fixes the mistake introduced in commit
b6737a8bcd03ea68952799144c0c6e6e6679bee9
Signed-off-by: Nayan Deshmukh
---
src/gallium/state_trackers/va/context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/state_trackers/va/context.c
b/src/gallium/state_trackers
This fixes a bunch of arb_fragment_program piglit tests.
Thanks.
Reviewed-by: Samuel Pitoiset
On 01/05/2017 01:48 PM, Marek Olšák wrote:
From: Marek Olšák
Broken by:
st/mesa: get Version from gl_program rather than gl_shader_program
---
src/mesa/state_tracker/st_atom_texture.c | 4 +++-
Am 04.01.2017 um 18:57 schrieb Marek Olšák:
On Wed, Jan 4, 2017 at 6:40 PM, Alex Deucher wrote:
On Wed, Jan 4, 2017 at 5:47 AM, Marek Olšák wrote:
From: Marek Olšák
The context may be used by texture_get_handle.
The the omx state tracker need this as well?
The omx state tracker doesn't us
Signed-off-by: Samuel Iglesias Gonsálvez
---
docs/features.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/features.txt b/docs/features.txt
index f4a67df..18327af 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -107,7 +107,7 @@ GL 3.3, GLSL 3.30 --- all
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
src/mesa/drivers/dri/i965/intel_screen.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_ext
This is the same we do in the GL driver: the hardware provides gl_Layer
in the VUE header, so when the fragment shader reads it we can't skip it.
---
With this patch we now successfully read gl_Layer in fragment shaders. Layered
rendering still does not work though, probably because we still need
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/intel_extensions.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 22651de..f402f7f 100644
--- a/src/me
From: "Juan A. Suarez Romero"
When splitting a CMP/MOV instruction with NULL dest, DF sources, and
conditional modifier; we can't use directly the flag registers, as they will
have the wrong results in IVB/VLV after the scalarization.
Rather, we need to store the result in a temporary register,
From: "Juan A. Suarez Romero"
In the generator we must generate slightly different code for
Ivybridge/Valleview, because of the way the stride works in
this hardware.
---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 26 +---
1 file changed, 23 insertions(+), 3 deletions
Add a new setup_imm_df() that alows the insertion of the instructions
before another one. This will be used in the lowering passes for DF
instructions.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_vec4.h | 2 ++
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 21
From: "Juan A. Suarez Romero"
When lowering double_to_single() we added a final mov() that puts 32-bit
values from one register in the second half of destination.
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 5 +
src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp | 3 ++
From: "Juan A. Suarez Romero"
When spliting double_to_single() in Ivybridge/Valleyview, the second
part should use a temporal register, and then move the values to the
second half of the original destiny, so we get all the results in the
same register.
---
src/mesa/drivers/dri/i965/brw_vec4.cpp
From: "Juan A. Suarez Romero"
Take in account the offset value when getting the var from register.
This is required when dealing with an operation that writes half of the
register (like one d2x in IVB/VLV, which uses exec_size == 4).
Note that for live analysis variables we need to stick to per
From: "Juan A. Suarez Romero"
Keep the original type when dealing with null registers. Specially
because we do no want to introduce an implicit conversion between
types that could affect the conditional flags.
This affects specially when the original type is DF, and we are working
on Ivybridge/V
The hardware applies the same channel enable signals to both halves of
the compressed instruction which will be just wrong under non-uniform
control flow. Fix this by splitting those instructions to SIMD4.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 9
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