On Mon, 2016-07-11 at 12:19 -0700, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> >
> > From: Iago Toral Quiroga
> >
> > In fp64 we can produce code like this:
> >
> > mov(16) vgrf2<2>:UD, vgrf3<2>:UD
> >
> > That our simd lowering pass would typically split in instructions
>
On 11/07/16 14:54, Kenneth Graunke wrote:
> On Monday, July 11, 2016 1:37:46 PM PDT Samuel Iglesias Gonsálvez wrote:
>> From: Iago Toral Quiroga
>>
>> Gen7 hardware does not support double immediates so these need
>> to be moved in 32-bit chunks to a regular vgrf instead. Instead
>> of doing thi
On Monday 11 July 2016 10:11:30 Emil Velikov wrote:
> Sounds similar (the same?) as
> https://bugs.freedesktop.org/show_bug.cgi?id=89347.
Output error looks lo be same.
> Which version of mako do you have, can you give things a try with
> 0.8.0 or later ?
If you mean mako python module, then I h
On Sun, Jun 26, 2016 at 08:40:55PM -0400, Jan Vesely wrote:
> Both explicit and implicit.
> Using vtx 0 (as existing llvm code implies) does not work for dynamic offsets.
>
> Signed-off-by: Jan Vesely
I have no idea why vtx#3 works when vtx#0, maybe add a comment
explaining why we are using vtx#
On Wed, Jun 29, 2016 at 2:04 PM, Ian Romanick wrote:
> From: Ian Romanick
>
> BFM is (((1u << a) - 1) << b). Recognize a couple patterns that look
> like this, and replace them with BFM.
>
> NOTE: Using lower_bitfield_insert is definitely not the right way to
> flag this optimization... so, I'm
On Thu, Jul 7, 2016 at 10:16 AM, Ian Romanick wrote:
> From: Ian Romanick
>
> v2: Retype LZD source as UD to avoid potential problems with 0x8000.
> Suggested by Matt. Also update comment about problem values with
> LZD(abs(x)). Suggested by Curro.
>
> Signed-off-by: Ian Romanick
> ---
>
Would you mind updating the README as well? With that, patches 2 & 3 are
Reviewed-by: Nicolai Hähnle
Patch 1 is
Acked-by: Nicolai Hähnle
On 11.07.2016 20:10, Marek Olšák wrote:
From: Marek Olšák
Use MESA_SHADER_CAPTURE_PATH instead.
---
split-to-files.py | 138 --
Reviewed-by: Ilia Mirkin
On Mon, Jul 11, 2016 at 4:25 PM, Samuel Pitoiset
wrote:
> This might avoid mistakes if the size is bumped in the future.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 8
> src/gallium/drivers/nouveau/nvc0/n
This might avoid mistakes if the size is bumped in the future.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 8
src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 4 ++--
src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c| 2 +-
s
Reviewed-by: Ilia Mirkin
A follow-up patch to replace all those 2048's with some #define would
be great :)
On Mon, Jul 11, 2016 at 3:26 PM, Samuel Pitoiset
wrote:
> The size of the driver constant buffer for each stage should be 2048
> and not 512 because it has been increased recently for buff
The size of the driver constant buffer for each stage should be 2048
and not 512 because it has been increased recently for buffers/images.
While we are at it, do the same change for indirect draws.
This fixes all ARB_shader_draw_parameters tests on GM107.
Signed-off-by: Samuel Pitoiset
Cc: 12.0
Francisco Jerez writes:
> Samuel Iglesias Gonsálvez writes:
>
>> From: Iago Toral Quiroga
>>
>> In fp64 we can produce code like this:
>>
>> mov(16) vgrf2<2>:UD, vgrf3<2>:UD
>>
>> That our simd lowering pass would typically split in instructions with a
>> width of 8, writing to two consecutive
Samuel Iglesias Gonsálvez writes:
> So that we can have gen7 split large writes produced by this lowering pass.
>
> Signed-off-by: Samuel Iglesias Gonsálvez
Reviewed-by: Francisco Jerez
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +-
> 1 file changed, 5 insertions(+), 5 deletio
Samuel Iglesias Gonsálvez writes:
> From: Iago Toral Quiroga
>
> In fp64 we can produce code like this:
>
> mov(16) vgrf2<2>:UD, vgrf3<2>:UD
>
> That our simd lowering pass would typically split in instructions with a
> width of 8, writing to two consecutive registers each. Unfortunately, gen7
>
On Fri, Jul 8, 2016 at 3:18 PM, Matt Turner wrote:
> I do appreciate the cleverness, but unfortunately it prevents a lot more
> cleverness in the form of additional compiler optimizations brought on
> by -fstrict-aliasing.
>
> No difference in OglBatch7 (n=20).
>
> Co-authored-by: Davin McCall
>
On Monday, July 11, 2016 8:10:44 PM PDT Marek Olšák wrote:
> From: Marek Olšák
>
> $ fdupes -rdN .
>
>[+] ./yofrankie/129.shader_test
>[-] ./yofrankie/126.shader_test
>
>[+] ./yofrankie/123.shader_test
>[-] ./yofrankie/132.shader_test
>
>[+] ./humus-volumetricfogging2/9.sha
From: Marek Olšák
$ fdupes -rdN .
[+] ./yofrankie/129.shader_test
[-] ./yofrankie/126.shader_test
[+] ./yofrankie/123.shader_test
[-] ./yofrankie/132.shader_test
[+] ./humus-volumetricfogging2/9.shader_test
[-] ./humus-celshading/9.shader_test
[+] ./nexuiz/6.shader_test
From: Marek Olšák
---
si-report.py | 3 +++
1 file changed, 3 insertions(+)
diff --git a/si-report.py b/si-report.py
index c7fe1b5..69af89e 100755
--- a/si-report.py
+++ b/si-report.py
@@ -366,6 +366,9 @@ def compare_results(before_all_results, after_all_results):
errors_names.appe
From: Marek Olšák
Use MESA_SHADER_CAPTURE_PATH instead.
---
split-to-files.py | 138 --
1 file changed, 138 deletions(-)
delete mode 100755 split-to-files.py
diff --git a/split-to-files.py b/split-to-files.py
deleted file mode 100755
index 72
On Mon, Jul 11, 2016 at 2:01 PM, Marek Olšák wrote:
> On Mon, Jul 11, 2016 at 7:55 PM, Ilia Mirkin wrote:
>> On Mon, Jul 11, 2016 at 1:48 PM, Marek Olšák wrote:
>>> On Mon, Jul 11, 2016 at 7:31 PM, Ilia Mirkin wrote:
On Mon, Jul 11, 2016 at 1:28 PM, Marek Olšák wrote:
> From: Marek Ol
On Thu, Jul 7, 2016 at 8:12 PM, Jason Ekstrand wrote:
> Drp...
>
> Reviewed-by: Jason Ekstrand
>
I added my R-B to your two and pushed the lot of them. Thanks for the
fixups!
> On Jul 7, 2016 4:06 PM, "Chad Versace" wrote:
>
>> Swap srcAccessMask and dstAccessMask.
>> ---
>> src/intel/vulka
On Mon, Jul 11, 2016 at 7:55 PM, Ilia Mirkin wrote:
> On Mon, Jul 11, 2016 at 1:48 PM, Marek Olšák wrote:
>> On Mon, Jul 11, 2016 at 7:31 PM, Ilia Mirkin wrote:
>>> On Mon, Jul 11, 2016 at 1:28 PM, Marek Olšák wrote:
From: Marek Olšák
This bug is uncovered by glsl/lower_if_to_co
On Mon, Jul 11, 2016 at 1:48 PM, Marek Olšák wrote:
> On Mon, Jul 11, 2016 at 7:31 PM, Ilia Mirkin wrote:
>> On Mon, Jul 11, 2016 at 1:28 PM, Marek Olšák wrote:
>>> From: Marek Olšák
>>>
>>> This bug is uncovered by glsl/lower_if_to_cond_assign.
>>> I don't know if it can be reproduced in any o
According to https://llvm.org/bugs/show_bug.cgi?id=19778#c3 this code
was violating the spec, resulting in it failing to compile.
Cc: mesa-sta...@lists.freedesktop.org
Co-authored-by: Tomasz Paweł Gajc
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89599
---
I've tried for months to repro
On Mon, Jul 11, 2016 at 7:31 PM, Ilia Mirkin wrote:
> On Mon, Jul 11, 2016 at 1:28 PM, Marek Olšák wrote:
>> From: Marek Olšák
>>
>> This bug is uncovered by glsl/lower_if_to_cond_assign.
>> I don't know if it can be reproduced in any other way.
>>
>> Cc:
>> ---
>> src/mesa/state_tracker/st_gl
On Fri, Jul 8, 2016 at 5:29 PM, Ilia Mirkin wrote:
> Signed-off-by: Ilia Mirkin
> Cc: "11.2 12.0"
> ---
>
> v1 -> v2: also include a mesa_is_etc2_format function which takes a GLenum.
>
> src/mesa/main/glformats.c | 23 +++
> src/mesa/main/glformats.h | 3 +++
> src/mesa/ma
On Mon, Jul 11, 2016 at 1:28 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> This bug is uncovered by glsl/lower_if_to_cond_assign.
> I don't know if it can be reproduced in any other way.
>
> Cc:
> ---
> src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 12 +++-
> 1 file changed, 7 insertion
From: Marek Olšák
This bug is uncovered by glsl/lower_if_to_cond_assign.
I don't know if it can be reproduced in any other way.
Cc:
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_
On Sat, Jul 09, 2016 at 12:17:28PM -0700, Jason Ekstrand wrote:
> ---
> src/intel/isl/isl.c | 11 +++
> src/intel/isl/isl.h | 17 +
> src/intel/isl/isl_format_layout.csv | 1 +
> src/intel/isl/isl_gen6.c| 8
> src/intel
On Mon, Jul 11, 2016 at 8:37 AM, Pohjolainen, Topi <
topi.pohjolai...@intel.com> wrote:
> On Sat, Jul 09, 2016 at 12:17:24PM -0700, Jason Ekstrand wrote:
> > ---
> > src/intel/isl/isl.c | 2 +-
> > src/intel/isl/isl_gen6.c | 2 +-
> > s
On Sat, Jul 09, 2016 at 12:17:27PM -0700, Jason Ekstrand wrote:
> ---
> src/intel/isl/gen_format_layout.py | 1 -
> src/intel/isl/isl.c| 11 ++-
> src/intel/isl/isl.h| 5 ++---
> src/intel/isl/isl_gen9.c | 14 +++---
> src/intel/isl/isl_s
On Sat, Jul 09, 2016 at 12:17:24PM -0700, Jason Ekstrand wrote:
> ---
> src/intel/isl/isl.c | 2 +-
> src/intel/isl/isl_gen6.c | 2 +-
> src/intel/isl/isl_gen7.c | 2 +-
> src/intel/isl/isl_storage_image.c
On Sat, Jul 09, 2016 at 12:17:21PM -0700, Jason Ekstrand wrote:
> This is based on a very long set of discussions between Chad and myself
> about how we should properly represent HiZ and CCS buffers. The end result
> of that discussion was that a tiling actually has two different sizes, a
> logica
On Mon, Jul 11, 2016 at 8:04 AM, Pohjolainen, Topi <
topi.pohjolai...@intel.com> wrote:
> On Sat, Jul 09, 2016 at 12:17:20PM -0700, Jason Ekstrand wrote:
> > ---
> > src/intel/isl/isl.c | 52
> +---
> > 1 file changed, 25 insertions(+), 27 deletions
On Sat, Jul 09, 2016 at 12:17:20PM -0700, Jason Ekstrand wrote:
> ---
> src/intel/isl/isl.c | 52 +---
> 1 file changed, 25 insertions(+), 27 deletions(-)
>
> diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
> index decba3d..6f57ac2 100644
> -
On 11/07/16 17:40, i...@iirolaiho.net wrote:
Hi,
I am asking about freedesktop bug #71759.
The bug has been open since 2013, but the problems are beginning to
surface now: on Fedora+[RPMFusion|UnitedRPMs], it breaks h.264 playback
on Totem with default settings (1). Fabrice Bellet has done some
Hi,
I am asking about freedesktop bug #71759.
The bug has been open since 2013, but the problems are beginning to
surface now: on Fedora+[RPMFusion|UnitedRPMs], it breaks h.264
playback on Totem with default settings (1). Fabrice Bellet has done
some debugging on the problem and even submi
On Mon, Jul 11, 2016 at 6:31 AM, Francesco Ansanelli
wrote:
> ---
> src/gallium/drivers/i915/i915_context.c |6 +++---
> src/gallium/drivers/i915/i915_flush.c |6 +++---
Please prefix patches to this directory "i915g: "
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git
---
src/gallium/drivers/i915/i915_context.c |6 +++---
src/gallium/drivers/i915/i915_flush.c |6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/i915/i915_context.c
b/src/gallium/drivers/i915/i915_context.c
index 82798bb..d7cdfd9 100644
--- a/sr
On Saturday, July 9, 2016 10:16:29 AM PDT Francesco Ansanelli wrote:
> ---
> src/mesa/drivers/dri/i965/gen6_queryobj.c |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c
> b/src/mesa/drivers/dri/i965/gen6_queryobj.c
> index 96db5
On Monday, July 11, 2016 1:37:46 PM PDT Samuel Iglesias Gonsálvez wrote:
> From: Iago Toral Quiroga
>
> Gen7 hardware does not support double immediates so these need
> to be moved in 32-bit chunks to a regular vgrf instead. Instead
> of doing this every time we need to create a DF immediate,
> c
On Monday, July 11, 2016 1:19:34 PM PDT Samuel Iglesias Gonsálvez wrote:
>
> On 06/07/16 22:32, Kenneth Graunke wrote:
> > On Wednesday, July 6, 2016 12:09:58 PM PDT Samuel Iglesias Gonsálvez wrote:
> >> From: Iago Toral Quiroga
> >>
> >> ---
> >> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 6 +++
Am 06.07.2016 um 20:03 schrieb Leo Liu:
We'll use weave shader in the later patch.
Signed-off-by: Leo Liu
I think I would prefer having a separate component for format conversion
of video buffers instead of pushing that into the compositor as well. We
could still share the weave shader in a
On Sat, Jul 09, 2016 at 10:16:29AM +0200, Francesco Ansanelli wrote:
> ---
> src/mesa/drivers/dri/i965/gen6_queryobj.c |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c
> b/src/mesa/drivers/dri/i965/gen6_queryobj.c
> index 96db5
From: Iago Toral Quiroga
In fp64 we can produce code like this:
mov(16) vgrf2<2>:UD, vgrf3<2>:UD
That our simd lowering pass would typically split in instructions with a
width of 8, writing to two consecutive registers each. Unfortunately, gen7
hardware has a bug affecting execution masking and
So that we can have gen7 split large writes produced by this lowering pass.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dr
From: Iago Toral Quiroga
So that we can have gen7 split large writes produced by the pack lowering.
Reviewed-by: Francisco Jerez
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/m
So far we only used instructions with this size in situations where we
did not operate per-channel and we wanted to ignore the execution mask,
but gen7 fp64 will need to emit code with a width of 4 that needs
normal execution masking.
v2:
- Modify the assert instead of deleting it (Curro)
Reviewe
From: Iago Toral Quiroga
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 94c719b..acc8c1e 100644
--- a/
Hello,
This is the second version of this patch series [0].
The use of DIM instruction on HSW to setup an 64-bit immediate reg
(suggested by Kenneth here [1]) will be sent in a separate patch series.
Thanks,
Sam
[0] https://lists.freedesktop.org/archives/mesa-dev/2016-July/122416.html
[1] http
From: Iago Toral Quiroga
Gen7 hardware does not support double immediates so these need
to be moved in 32-bit chunks to a regular vgrf instead. Instead
of doing this every time we need to create a DF immediate,
create a helper function that does the right thing depending
on the hardware generatio
On 06/07/16 22:32, Kenneth Graunke wrote:
> On Wednesday, July 6, 2016 12:09:58 PM PDT Samuel Iglesias Gonsálvez wrote:
>> From: Iago Toral Quiroga
>>
>> ---
>> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/src/mesa/dr
https://bugs.freedesktop.org/show_bug.cgi?id=96853
--- Comment #5 from denis.fisse...@tu-dortmund.de ---
(In reply to Roland Scheidegger from comment #3)
> In theory if there already is a user-provided gs (which doesn't output
> points) then the emulation code doesn't really apply. But I don't re
On 10 July 2016 at 22:11, Pali Rohár wrote:
> Hello, compiling mesa from git is failing on this error:
>
> Making all in isl
> make[5]: Entering directory `/«PKGBUILDDIR»/build/dri/src/intel/isl'
> python2.7 ../../../../../src/intel/isl/gen_format_layout.py \
> --csv ../../../../../sr
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