This series is ACK'ed by,
Edward O'Callaghan
On 06/24/2016 01:52 PM, Timothy Arceri wrote:
> V4:
> - add vec4 backend support and enable for Gen6+
>
> V3:
> - Rewrite patch 9 (add support for packing arrays) to not add
> hacks to the type_size() functions.
> - Add packing support for the load_o
On 24.06.2016 03:59, Kenneth Graunke wrote:
> Module: Mesa
> Branch: master
> Commit: ef78df8d3b0cf540e5f08c8c2f6caa338b64a6c7
> URL:
> http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef78df8d3b0cf540e5f08c8c2f6caa338b64a6c7
>
> Author: Kenneth Graunke
> Date: Fri Apr 29 18:05:26 2016 -070
Previously we were only restricting based on ES/non-ES-ness and whether
the overall enable bit had been flipped on. However we have been adding
more fine-grained restrictions, such as based on compat profiles, as
well as specific ES versions. Most of the time this doesn't matter, but
it can create
On Fri, Jun 24, 2016 at 12:20 AM, Rob Herring wrote:
> On Thu, Jun 23, 2016 at 7:01 PM, Ilia Mirkin wrote:
>> As before, you need to keep the dupfd. There's even a long comment there to
>> explain why.
>
> And I responded why I don't think it is:
>
> "Those 2 commits predate commit 13bccee87d63 w
On Fri, Jun 24, 2016 at 12:20 AM, Rob Herring wrote:
> On Thu, Jun 23, 2016 at 7:01 PM, Ilia Mirkin wrote:
>> As before, you need to keep the dupfd. There's even a long comment there to
>> explain why.
>
> And I responded why I don't think it is:
>
> "Those 2 commits predate commit 13bccee87d63 w
Both are
Reviewed-by: Matt Turner
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On Thu, Jun 23, 2016 at 7:01 PM, Ilia Mirkin wrote:
> As before, you need to keep the dupfd. There's even a long comment there to
> explain why.
And I responded why I don't think it is:
"Those 2 commits predate commit 13bccee87d63 which dup's the fd for the
DRI2 ST before calling pipe loader fun
---
docs/GL3.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index ce34869..0e89a12 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -193,11 +193,11 @@ GL 4.4, GLSL 4.40:
GL_MAX_VERTEX_ATTRIB_STRIDE DONE (all drive
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 27dfb0c..9989611 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 4082a2c..b261b39 100644
--- a/src/mesa/drivers/dri/i965/brw
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 33
1 file changed, 29 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index c18e51c..aaa4980 100644
--- a/
For example where n=3 first_component=1 this will give us
0xE (WRITEMASK_YZW).
---
src/mesa/drivers/dri/i965/brw_reg.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
b/src/mesa/drivers/dri/i965/brw_reg.h
index 8e6fcd5..792015b 100644
--- a/src/mesa/d
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 22 ++
2 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index f
---
src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp
index 9ebfb27..4b15302 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp
+++ b/src/mesa/dr
Here we create a new output_generic_reg array with the ability to
store the dst_reg for each component of user defined varyings.
This is needed as the previous code only stored the dst_reg based
on the varying location which meant packed varyings would overwrite
each other.
---
src/mesa/drivers/dr
---
src/mesa/drivers/dri/i965/brw_vec4_tes.cpp | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp
index 6639c86..22293da 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp
---
src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp | 17 +
src/mesa/drivers/dri/i965/brw_vec4_tcs.h | 1 +
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
index 0a33a39..27b8988
Here we add a new helper function calc_type_size_offset() to help
calculate the size of a varying once packing is taken into account.
---
src/compiler/nir/nir_lower_io.c | 55 +++--
1 file changed, 48 insertions(+), 7 deletions(-)
diff --git a/src/compiler/nir/
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index f3b4528..cbe7468 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i9
---
src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp | 8 ++--
src/mesa/drivers/dri/i965/brw_vec4_tcs.h | 1 +
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
index f61c612..8c76e81 100644
--- a
---
src/compiler/glsl/link_varyings.cpp | 16 +---
src/compiler/nir/nir_lower_io.c | 16
2 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/src/compiler/glsl/link_varyings.cpp
b/src/compiler/glsl/link_varyings.cpp
index 89cfd1c..754305b 100644
--- a/s
---
src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
index 8c76e81..0a33a39 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
+++ b/src/mesa/drivers/d
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 27 ++-
1 file changed, 18 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index b261b39..2186336 100644
--- a/src/m
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index aaa4980..6d589ed 100644
--- a/src/mesa/drive
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 38 +++-
1 file changed, 33 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 6d589ed..4082a2c 100644
--- a/src/mesa/drivers/dri/i965/brw_
This will be used to swizzle components to the beginning or end
of the vector based on the component layout qualifier and whether
we are doing a load or store.
---
src/mesa/drivers/dri/i965/brw_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
b/src/
Reviewed-by: Kenneth Graunke
---
src/compiler/nir_types.cpp | 6 ++
src/compiler/nir_types.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/src/compiler/nir_types.cpp b/src/compiler/nir_types.cpp
index 835d53b..f694a84 100644
--- a/src/compiler/nir_types.cpp
+++ b/src/compiler/nir_ty
---
src/compiler/nir_types.cpp | 6 ++
src/compiler/nir_types.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/src/compiler/nir_types.cpp b/src/compiler/nir_types.cpp
index 4ea7a2f..835d53b 100644
--- a/src/compiler/nir_types.cpp
+++ b/src/compiler/nir_types.cpp
@@ -257,6 +257,12 @@ g
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index adb9230..c18e51c 100644
--- a/src/mesa/drivers/dri/i
Reviewed-by: Kenneth Graunke
---
src/compiler/nir/nir.h| 4 ++--
src/compiler/nir/nir_lower_io.c | 28 ++--
src/mesa/drivers/dri/i965/brw_nir.c | 8 +---
src/mesa/drivers/dri/i965/brw_program.c | 4 ++--
src/mesa/state_tracker/s
This will be used to store the total number of components used at this location
when packing via ARB_enhanced_layouts.
---
src/compiler/glsl/glsl_to_nir.cpp | 1 +
src/compiler/glsl/ir.h | 5 +++
src/compiler/glsl/link_varyings.cpp | 74 -
src/c
This offset is used for packing.
Reviewed-by: Kenneth Graunke
---
src/compiler/nir/nir.h| 6 ++
src/compiler/nir/nir_intrinsics.h | 12 ++--
src/compiler/nir/nir_lower_io.c | 8
src/compiler/nir/nir_print.c | 3 +++
4 files changed, 23 insertions(+), 6
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 20
src/mesa/drivers/dri/i965/brw_fs.h | 5 +++--
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 29 -
3 files changed, 35 insertions(+), 19 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_f
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 38 +++-
1 file changed, 33 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 77355ff..adb9230 100644
--- a/
V4:
- add vec4 backend support and enable for Gen6+
V3:
- Rewrite patch 9 (add support for packing arrays) to not add
hacks to the type_size() functions.
- Add packing support for the load_output intrinsics (patch 12)
- Add glsl_dvec_type() helper (patch 8)
V2:
- validation fixes patches 1-2
- ad
On Thursday, June 23, 2016 16:53:59 you wrote:
> On Friday 17 June 2016, mathias.froehl...@gmx.net wrote:
> > From: Mathias Fröhlich
> >
> > Implement the equivalent of vbo_all_varyings_in_vbos for
> > vertex array objects.
> >
> > Signed-off-by: Mathias Fröhlich
> > ---
> > src/mesa/main/arra
On 23 June 2016 at 23:25, Emil Velikov wrote:
> On 23 June 2016 at 03:49, Michel Dänzer wrote:
>> On 22.06.2016 21:04, Emil Velikov wrote:
>>> From: Emil Velikov
>>>
>>> Do not rely on the git sha1:
>>> - its current truncated form makes it less unique
>>> - it does not attribute for local (Vu
brw_tex.c is a tiny file containing a single function. It's closely
tied to the validation logic in intel_tex_validate.c, so it makes sense
to put both in the same file.
While we're at it, update the function to our modern style.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/Mak
The old return type of GLuint was wonky - it should have been bool.
But nothing actually uses the return value anyway, so we can just drop
that and make it a void function.
In theory, it might make sense to ask whether the texture validated
successfully, but just checking intel_obj->mt != NULL wor
When EGL is used on some other thread than the thread that drives the
main wl_display queue, the Wayland EGL dri2 implementation is
vulnerable to a race condition related to display round trips and global
object advertisements.
The race that may happen is that after after a proxy is created, but
b
We were ignoring the incoming box parameters, and were providing totally
bogus stride/layer stride, and other bits, for when a non-full-surface
map was requested.
Signed-off-by: Ilia Mirkin
Cc:
---
src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c | 17 -
1 file changed, 12 inser
On 23.06.2016 22:25, Emil Velikov wrote:
> On 23 June 2016 at 03:49, Michel Dänzer wrote:
>> On 22.06.2016 21:04, Emil Velikov wrote:
>>> From: Emil Velikov
>>>
>>> Do not rely on the git sha1:
>>> - its current truncated form makes it less unique
>>> - it does not attribute for local (Vulkand
Under some circumstances, the driver may choose to return a temporary
surface instead of a pointer to the original. Make sure to pass the
actual view volume to be mapped to the transfer function rather than
adjusting the map pointer after-the-fact.
Signed-off-by: Ilia Mirkin
---
Perhaps this sho
Isn't this true for any-non-alpha-having format? I.e. _BaseFormat !=
GL_RGBA && _BaseFormat != GL_ALPHA && _BaseFormat !=
GL_LUMINANCE_ALPHA && _BaseFormat != GL_INTENSITY? (Not sure about
that last one tbh.)
On Thu, Jun 23, 2016 at 10:07 PM, Brian Paul wrote:
> This indicates the alpha channel o
This is needed when we're using an RGBA surface but it should act as if
it were RGB (A=1).
---
src/gallium/drivers/svga/svga_context.h| 3 +-
src/gallium/drivers/svga/svga_pipe_blend.c | 90 ++
src/gallium/drivers/svga/svga_state_rss.c | 9 ++-
3 files changed, 7
Instead of creating the blend object right away, wait until state
validation time. We'll build on this in the next commit.
---
src/gallium/drivers/svga/svga_context.h| 6 +++
src/gallium/drivers/svga/svga_pipe_blend.c | 70 --
src/gallium/drivers/svga/svga_state_r
If the user requests an RGB drawing surface but we actually create an
RGBA surface, we need it to act as if A=1. For blending, this means
adjusting the blending terms to use 1/0 instead of DST_ALPHA/INV_DST_ALPHA.
Drivers can use this flag to determine when that's needed.
A previous patch I poste
This indicates the alpha channel of the surface should always be one.
Drivers can use this to adjust blending terms when needed.
---
src/mesa/state_tracker/st_cb_fbo.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/state_tracker/st_cb_fbo.c
b/src/mesa/state_tracker/st_cb_fbo.c
in
On 06/23/2016 03:30 PM, Ilia Mirkin wrote:
> On Thu, Jun 23, 2016 at 6:07 PM, Ian Romanick wrote:
>> On 06/16/2016 12:12 PM, Ilia Mirkin wrote:
>>> On Thu, Jun 16, 2016 at 3:06 PM, Ian Romanick wrote:
From: Ian Romanick
Outputs from the vertex shader need to be able to match
https://bugs.freedesktop.org/show_bug.cgi?id=96656
Ilia Mirkin changed:
What|Removed |Added
Assignee|mesa-dev@lists.freedesktop. |nouveau@lists.freedesktop.o
Jan Vesely writes:
> On Wed, 2016-06-22 at 20:22 -0700, Francisco Jerez wrote:
>> Jan Vesely writes:
>>
>> > On Wed, 2016-06-22 at 17:07 -0700, Francisco Jerez wrote:
>> > > Jan Vesely writes:
>> > >
>> > > > On Mon, 2016-06-13 at 17:24 -0700, Francisco Jerez wrote:
>> > > > > Serge Martin w
On Thu, Jun 23, 2016 at 7:42 PM, Nicolai Hähnle wrote:
> Hi,
>
> I'm sending out two changes for Polaris support that should still go into
> 12.0 (fingers crossed that that's it :-)).
>
> Note that the DRAW_PREAMBLE change should really be applicable to all CIK+
> parts, but let's not do anything
Thanks for the additions!
Reviewed-by: Matt Turner
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We recently had a mistake where we emitted SEND instructions with EOT
set, but from g107 rather than g112-g127. Adding validation code should
prevent these sorts of problems from slipping back in.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_eu_validate.c | 18 ++
As before, you need to keep the dupfd. There's even a long comment there to
explain why.
On Jun 23, 2016 7:58 PM, "Rob Herring" wrote:
> Use the common pipe_screen ref counting and fd hashing functions. The
> mutex can be dropped as the pipe loader protects the create_screen()
> calls.
>
> Signed
Use the common pipe_screen ref counting and fd hashing functions. The
mutex can be dropped as the pipe loader protects the create_screen()
calls.
Signed-off-by: Rob Herring
Cc: "Marek Olšák"
Cc: Ilia Mirkin
---
src/gallium/drivers/r300/r300_screen.c| 3 -
src/gallium/drivers/r600/
Use the common pipe_screen ref counting and fd hashing functions. The
mutex can be dropped as the pipe loader protects the create_screen()
calls.
Cc: Eric Anholt
Signed-off-by: Rob Herring
---
src/gallium/winsys/vc4/drm/vc4_drm_winsys.c | 9 -
1 file changed, 8 insertions(+), 1 deletion
Use the common pipe_screen ref counting and fd hashing functions. The
mutex can be dropped as the pipe loader protects the create_screen()
calls.
Signed-off-by: Rob Herring
Cc: Alexandre Courbot
---
src/gallium/drivers/nouveau/nouveau_screen.c | 6 --
src/gallium/drivers/nouveau/nouveau_
Use the common pipe_screen ref counting and fd hashing functions. The
mutex can be dropped as the pipe loader protects the create_screen()
calls.
Signed-off-by: Rob Herring
Cc: Rob Clark
---
src/gallium/drivers/freedreno/freedreno_screen.c | 1 -
src/gallium/drivers/freedreno/freedreno_scree
Use the common pipe_screen ref counting and fd hashing functions. The
mutex can be dropped as the pipe loader protects the create_screen()
calls.
Signed-off-by: Rob Herring
---
src/gallium/winsys/svga/drm/vmw_screen.c | 51
src/gallium/winsys/svga/drm/vmw_screen.
Use the common pipe_screen ref count. amdgpu is unique in its hashing
the dev pointer rather than the fd, so the common fd hashing cannot be
used. However, the same reference count can be used instead of the
private one. The mutex can be dropped as the pipe loader protects the
create_screen() calls
Use pipe_screen_unreference as it will call pipe_screen->destroy() when
the pipe_screen is no longer referenced.
The pipe_screen referencing is done within create_screen() functions
as drivers (like amdgpu) may have special needs for ref counting.
Signed-off-by: Rob Herring
Cc: Emil Velikov
---
Use the common pipe_screen ref counting and fd hashing functions.
The mutex can be dropped as the pipe loader protects the create_screen()
calls. The fd does not need to be dup'ed as the caller has already done
that.
Signed-off-by: Rob Herring
Cc: Dave Airlie
---
src/gallium/winsys/virgl/drm/vi
Creating a screen needs to be an atomic operation in order to support
reusing existing screen. With this, driver private mutexes in
create screen functions can be removed.
Signed-off-by: Rob Herring
Cc: Emil Velikov
---
src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c | 8
1 file ch
In order to prevent multiple pipe_screens being created in the same
process, lookup of the DRM FD and reference counting of the pipe_screen
are needed. Several implementations of this exist in various gallium
drivers/winsys already. This creates a common version which is opt-in
for winsys implement
I needed to add screen ref counting to vc4 driver, so rather than yet
another copy of the same fd hashing and ref counting code, I implemented
it in the pipe-loader. AFAICT, the pipe-loader is the only place the
winsys create screen functions are called and seemed to be the best
location to put thi
In preparation to add reference counting of pipe_screen in the pipe-loader,
pipe_loader_release needs to destroy the pipe_screen instead of state
trackers.
Signed-off-by: Rob Herring
Cc: Emil Velikov
---
src/gallium/auxiliary/pipe-loader/pipe_loader.h | 1 +
src/gallium/auxiliary/pipe-loade
From: Nicolai Hähnle
The non-MULTI variants will be removed in Polaris firmware.
Cc: 12.0
---
src/gallium/drivers/radeonsi/si_state_draw.c | 46 ++--
1 file changed, 36 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gall
Hi,
I'm sending out two changes for Polaris support that should still go into
12.0 (fingers crossed that that's it :-)).
Note that the DRAW_PREAMBLE change should really be applicable to all CIK+
parts, but let's not do anything risky last-minute to the hardware that's
already out there.
Please
From: Nicolai Hähnle
It will be removed from the firmware for the Polaris.
Cc: 12.0
---
src/gallium/drivers/radeon/r600_cs.h | 22 ++
src/gallium/drivers/radeonsi/si_state_draw.c | 7 ++-
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/src/galliu
Nayan Deshmukh wrote:
Hi Andy,
Could you test the new patch series that I have sent? It should probably
work this time.
Only had time for some quick tests so far.
The scaling is now 99% OK, maybe 100% as I don't really know what
artifacts to expect from artificial tests.
The aspect is now co
On Thu, Jun 23, 2016 at 6:07 PM, Ian Romanick wrote:
> On 06/16/2016 12:12 PM, Ilia Mirkin wrote:
>> On Thu, Jun 16, 2016 at 3:06 PM, Ian Romanick wrote:
>>> From: Ian Romanick
>>>
>>> Outputs from the vertex shader need to be able to match
>>> per-vertex-arrayed inputs of later stages. Acompli
On 06/16/2016 12:12 PM, Ilia Mirkin wrote:
> On Thu, Jun 16, 2016 at 3:06 PM, Ian Romanick wrote:
>> From: Ian Romanick
>>
>> Outputs from the vertex shader need to be able to match
>> per-vertex-arrayed inputs of later stages. Acomplish this by stripping
>> one level of arrayness from the names
The spec has been updated adding new PCI IDs.
Signed-off-by: Rodrigo Vivi
---
include/drm/i915_pciids.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 9094599..87dde1c 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i91
The spec has been updated adding new PCI IDs.
Signed-off-by: Rodrigo Vivi
---
intel/intel_chipset.h | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index e2554c3..0c3ca82 100644
--- a/intel/intel_chipset.h
+++ b/in
The spec has been updated adding new PCI IDs.
Signed-off-by: Rodrigo Vivi
---
include/pci_ids/i965_pci_ids.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index fce00da..7a7897f 100644
--- a/include/pci_ids/i965_pci_ids.h
+
This is unusual. Usually IDs listed on early stages of platform
definition are kept there as reserved for later use.
However these IDs here are not listed anymore in any of steppings
and devices IDs tables for Kabylake on configurations overview
section of BSpec.
So it is better removing them bef
This is unusual. Usually IDs listed on early stages of platform
definition are kept there as reserved for later use.
However these IDs here are not listed anymore in any of steppings
and devices IDs tables for Kabylake on configurations overview
section of BSpec.
So it is better removing them bef
This is unusual. Usually IDs listed on early stages of platform
definition are kept there as reserved for later use.
However these IDs here are not listed anymore in any of steppings
and devices IDs tables for Kabylake on configurations overview
section of BSpec.
So it is better removing them bef
Reviewed-by: Matt Turner
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ping
I'll have a response to Ilia's feedback shortly.
On 06/16/2016 12:06 PM, Ian Romanick wrote:
> From: Ian Romanick
>
> Outputs from the vertex shader need to be able to match
> per-vertex-arrayed inputs of later stages. Acomplish this by stripping
> one level of arrayness from the names an
ping
*Before* 12.0 ships, we must either land this patch or a patch that
redacts the GLES 3.1 functions (e.g., glDispatchCompute) that we already
statically export.
On 06/17/2016 10:20 AM, Ian Romanick wrote:
> From: Ian Romanick
>
> Khronos recommends that the GLES 3.1 library also be called l
It defaults to true so default behavior doesn't change but it allows you to
do NIR_VALIDATE=false if you don't want validation. Disabling validation
can substantially speed up shader compiles so you frequently want to turn
it off if compiler invariants aren't in question.
---
src/compiler/nir/nir
On Thu, Jun 23, 2016 at 2:06 PM, Kenneth Graunke wrote:
> These only exist post-Sandybridge, and always use send-from-GRF.
> So inst->base_mrf will be -1, and we will have already returned 0.
>
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 18 --
Hi Andy,
Could you test the new patch series that I have sent? It should probably
work this time.
Thanks,
Nayan.
On Wed, Jun 22, 2016 at 7:07 PM, Andy Furniss wrote:
> Andy Furniss wrote:
>
> re-testing with an unpatched mesa and return false after PREFERS I see
>> the same.
>>
>> s/w decode m
ping
On 06/16/2016 12:07 PM, Ian Romanick wrote:
> From: Ian Romanick
>
> v2: Also update varying_matches::compute_packing_class(). Suggested by
> Timothy Arceri.
>
> Signed-off-by: Ian Romanick
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96358
> Cc: "12.0"
> Cc: Gregory Hainaut
Kenneth Graunke writes:
> On MRF platforms, we need to set base_mrf to the first MRF value we'd
> like to use for the message. On send-from-GRF platforms, we set it to
> -1 to indicate that the operation doesn't use MRFs.
>
> As MRF platforms are becoming increasingly a thing of the past, we've
R-B
On Thu, Jun 23, 2016 at 1:56 PM, Chad Versace
wrote:
> Will be needed for resolving auxiliary surfaces.
>
> I didn't add anv_render_pass_attachment::stencil_store_op, as the driver
> would likely never use it, as stencil surfaces never have auxiliary
> surfaces.
> ---
> src/intel/vulkan/anv
use bicubic filtering as high quality scaling L1.
v2: fix a typo and add a newline to code
v3: -render the unscaled image on a temporary surface (Christian)
-apply noise reduction and sharpness filter on
unscaled surface
-render the final scaled surface using bicubic
interpolati
This is a shader based bicubic interpolater which uses cubic
Hermite spline algorithm.
v2: set dst_area and dst_clip during scaling (Christian)
Signed-off-by: Nayan Deshmukh
---
src/gallium/auxiliary/Makefile.sources | 2 +
src/gallium/auxiliary/vl/vl_bicubic_filter.c | 402
These are now unnecessary, as base_mrf is -1 by default.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 4
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 12
2 files changed, 16 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/m
On MRF platforms, we need to set base_mrf to the first MRF value we'd
like to use for the message. On send-from-GRF platforms, we set it to
-1 to indicate that the operation doesn't use MRFs.
As MRF platforms are becoming increasingly a thing of the past, we've
forgotten to bother with this. It
These only exist post-Sandybridge, and always use send-from-GRF.
So inst->base_mrf will be -1, and we will have already returned 0.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 18 --
1 file changed, 18 deletions(-)
diff --git a/src/mesa/drivers/dri/
---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 169 +-
1 file changed, 1 insertion(+), 168 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 2a7ae31..bdb4f66 100644
--- a/src/mesa/dri
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 213 +
1 file changed, 1 insertion(+), 212 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index f4375ea..ed26271 100644
--- a/src/mesa/drivers/d
---
src/intel/isl/isl.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 4aedb11..5011d15 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -506,6 +506,32 @@ enum isl_dim_layout {
ISL_DIM_LAYOUT_GEN9_1D,
---
src/intel/genxml/Android.mk | 15 +++
src/intel/genxml/Makefile.am | 3 +++
src/intel/genxml/Makefile.sources | 3 +++
src/intel/genxml/gen4.xml | 52
src/intel/genxml/gen45.xml| 56 ++
---
src/mesa/drivers/dri/i965/gen8_blorp.c | 47 +++---
1 file changed, 38 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c
b/src/mesa/drivers/dri/i965/gen8_blorp.c
index b5c600b..918f3d6 100644
--- a/src/mesa/drivers/dri/i965/gen8_blo
---
src/mesa/drivers/dri/i965/gen8_blorp.c | 99 ++
1 file changed, 4 insertions(+), 95 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c
b/src/mesa/drivers/dri/i965/gen8_blorp.c
index fcf5a53..b5c600b 100644
--- a/src/mesa/drivers/dri/i965/gen8_blo
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 11 ++-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 9 +
src/mesa/drivers/dri/i965/gen8_surface_state.c| 9 +
3 files changed, 16 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw
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