On Apr 12, 2016 1:06 AM, "Samuel Iglesias Gonsálvez"
wrote:
>
> Some instructions (like flrp in i965) cannot be lowered depending on the
> bit size because it doesn't support all bit sizes.
>
> If the bit size field is defined in nir_opt_algebraic.py, take it into
> account.
I'm sorry I keep punt
On Apr 23, 2016 4:39 PM, "Kenneth Graunke" wrote:
>
> From: Jason Ekstrand
>
> Reviewed-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 8 +++-
> src/mesa/drivers/dri/i965/brw_shader.cpp | 3 ++-
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/src/
Is there any known measurable performance impact?
On Apr 23, 2016 8:58 PM, "Jason Ekstrand" wrote:
>
> On Apr 23, 2016 4:39 PM, "Kenneth Graunke" wrote:
> >
> > Often, we don't need a full 4 channels worth of data from the sampler.
> > For example, depth comparisons and red textures only return
Reviewed-by Jason Ekstrand
The rest of the patches look just as good to me now as when I wrote them,
but you can't very well call that a review. :-p
On Apr 23, 2016 4:39 PM, "Kenneth Graunke" wrote:
> Calling textureOffset() with an offset of <0, 0, 0> is equivalent to
> calliing texture(). We
On Apr 23, 2016 4:39 PM, "Kenneth Graunke" wrote:
>
> Often, we don't need a full 4 channels worth of data from the sampler.
> For example, depth comparisons and red textures only return one value.
> To handle this, the sampler message header contains a mask which can
> be used to disable channels
Signed-off-by: Edward O'Callaghan
---
src/mapi/glapi/glapi_getproc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mapi/glapi/glapi_getproc.c b/src/mapi/glapi/glapi_getproc.c
index 524a771..178fd6e 100644
--- a/src/mapi/glapi/glapi_getproc.c
+++ b/src/mapi/glapi/glapi_ge
On Saturday, April 23, 2016 8:29:14 PM PDT Jonathan Gray wrote:
> On Sat, Apr 23, 2016 at 01:09:43AM -0700, Kenneth Graunke wrote:
> > On Saturday, April 23, 2016 5:39:02 PM PDT Jonathan Gray wrote:
> > > src/intel/genxml/gen_pack_header.py requires python3.
> > >
> > > v2: check for python3.5 as
From: Jason Ekstrand
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 8 +++-
src/mesa/drivers/dri/i965/brw_shader.cpp | 3 ++-
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw
From: Jason Ekstrand
Reviewed-by: Kenneth Graunke
---
src/compiler/nir/nir.c | 25 +
src/compiler/nir/nir.h | 2 ++
2 files changed, 27 insertions(+)
diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index 5cafc41..92bbc37 100644
--- a/src/compiler/nir/nir.c
From: Jason Ekstrand
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 11 ++-
2 files changed, 3 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/d
Often, we don't need a full 4 channels worth of data from the sampler.
For example, depth comparisons and red textures only return one value.
To handle this, the sampler message header contains a mask which can
be used to disable channels, and reduce the message length (in SIMD16
mode on all hardwa
Calling textureOffset() with an offset of <0, 0, 0> is equivalent to
calliing texture(). We don't actually need to set up an offset,
which causes a message header to be created.
A fairly common pattern is to sample at a point with a bunch of
offsets, and average them. It's natural to write all t
From: Jason Ekstrand
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
index b095421..99b4ff5 100644
--- a/src/me
On Sat, Apr 23, 2016 at 8:35 AM, Pohjolainen, Topi <
topi.pohjolai...@intel.com> wrote:
> On Fri, Apr 22, 2016 at 04:19:10PM -0700, Jason Ekstrand wrote:
> > They didn't really add anything other than a key and extra layers of
> > function calls. This commit just inlines the extra functions and g
On Sat, Apr 23, 2016 at 8:11 AM, Pohjolainen, Topi <
topi.pohjolai...@intel.com> wrote:
> On Fri, Apr 22, 2016 at 04:19:14PM -0700, Jason Ekstrand wrote:
> > This commit is mostly mechanical except that it changes where we set the
> > swizzle. Previously, the blorp_surface_info constructor defaul
---
report.py | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/report.py b/report.py
index f9b1776..8dfc72a 100755
--- a/report.py
+++ b/report.py
@@ -10,7 +10,7 @@ def get_results(filename):
results = {}
-re_match = re.compile(r"(\S+) - (\S+ \S+) shader: (\
https://bugs.freedesktop.org/show_bug.cgi?id=95071
Kai changed:
What|Removed |Added
CC||e...@anholt.net,
|
On Fri, Apr 22, 2016 at 04:23:59PM -0700, Kenneth Graunke wrote:
> On Tuesday, April 12, 2016 3:30:14 PM PDT Nanley Chery wrote:
> > From: Nanley Chery
> >
> > When uploading a linear, void-extent, ASTC LDR block on Skylake, we are
> > required to flush to zero the UNORM16 channel values that wou
Le jeudi 21 avril 2016, 14:16:05 CEST Emil Velikov a écrit :
> From: Emil Velikov
>
> Autoconf already does the exact same thing as the manually written rule.
>
> Signed-off-by: Emil Velikov
> ---
>
> IMHO we can/should nuke --with-vulkan-icddir all together and/or
> change it to /usr/share vs
On Thu, Apr 21, 2016 at 8:42 AM, Emil Velikov wrote:
> Hi Rob,
>
> On 19 April 2016 at 20:38, Rob Herring wrote:
>> The RGBX/RGBA pixel formats used in the Android EGL don't get configs
>> created due to the missing formats in the DRI state tracker. This series
>> adds the necessary formats for c
https://bugs.freedesktop.org/show_bug.cgi?id=95071
--- Comment #1 from Nick Sarnie ---
Thanks for tracking this down Daniel, I was loosing my mind.
Same issue here on Radeon 7950/TAHITI with mesa/xserver git. Reverting that
commit fixes it.
Thanks,
sarnex
--
You are receiving this mail becaus
https://bugs.freedesktop.org/show_bug.cgi?id=95071
Rex Dieter changed:
What|Removed |Added
CC||rdie...@math.unl.edu
--
You are receiving
https://bugs.freedesktop.org/show_bug.cgi?id=95088
Bug ID: 95088
Summary: src/intel/vulkan/anv_entrypoints.h:162:69: error:
unknown type name âVkXcbSurfaceCreateInfoKHRâ
Product: Mesa
Version: git
Hardware: x86-64 (AMD6
On Sat, Apr 23, 2016 at 05:40:25PM +0300, Pohjolainen, Topi wrote:
> On Sat, Apr 23, 2016 at 07:32:33AM -0700, Jason Ekstrand wrote:
> >On Apr 23, 2016 3:46 AM, "Pohjolainen, Topi"
> ><[1]topi.pohjolai...@intel.com> wrote:
> >>
> >> On Fri, Apr 22, 2016 at 04:19:08PM -0700, Jason Ek
On Fri, Apr 22, 2016 at 04:19:10PM -0700, Jason Ekstrand wrote:
> They didn't really add anything other than a key and extra layers of
> function calls. This commit just inlines the extra functions and gets rid
> of the extra classes.
> ---
> src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 224
>
On Fri, Apr 22, 2016 at 04:19:14PM -0700, Jason Ekstrand wrote:
> This commit is mostly mechanical except that it changes where we set the
> swizzle. Previously, the blorp_surface_info constructor defaulted the
> swizzle to SWIZZLE_XYZW. Now, we memset to zero and fill out the swizzle
> when we s
On Sat, Apr 23, 2016 at 07:32:33AM -0700, Jason Ekstrand wrote:
>On Apr 23, 2016 3:46 AM, "Pohjolainen, Topi"
><[1]topi.pohjolai...@intel.com> wrote:
>>
>> On Fri, Apr 22, 2016 at 04:19:08PM -0700, Jason Ekstrand wrote:
>> > Instead of having a virtual member function for gettin
On Apr 22, 2016 10:51 AM, "Pohjolainen, Topi"
wrote:
>
> On Fri, Apr 22, 2016 at 10:39:37AM -0700, Kenneth Graunke wrote:
> > On Friday, April 22, 2016 3:01:27 PM PDT Juha-Pekka Heikkila wrote:
> > > base_mrf is unsigned, checking if its greater or equal to zero will
> > > not fail.
> > >
> > > Si
Reviewed-by: Jason Ekstrand
In general, we should be using mesa compat headers for this sort of thing
rather than hand-rolling it.
On Apr 23, 2016 12:28 AM, "Jonathan Gray" wrote:
> Remove a wrapper around __builtin_ffs that conflicts with system
> headers on OpenBSD and perhaps elsewhere:
>
>
LGTM
Reviewed-by: Jason Ekstrand
On Apr 23, 2016 12:42 AM, "Jonathan Gray" wrote:
> Allows the build to work when the python3 binary is not "python3".
>
> v2: remove x bit from the script at Emil's suggestion
>
> Signed-off-by: Jonathan Gray
> Reviewed-by: Emil Velikov
> ---
> src/intel/genx
On Apr 23, 2016 3:46 AM, "Pohjolainen, Topi"
wrote:
>
> On Fri, Apr 22, 2016 at 04:19:08PM -0700, Jason Ekstrand wrote:
> > Instead of having a virtual member function for getting the WM/PS
kernel,
> > we simply add fields for prog_data and the kernel to brw_blorp_parms and
> > always make sure th
https://bugs.freedesktop.org/show_bug.cgi?id=95083
Bug ID: 95083
Summary: ilo driver draws only the mouse cursor
Product: Mesa
Version: 11.2
Hardware: Other
OS: All
Status: NEW
Severity: normal
P
Am 23.04.2016 um 06:01 schrieb Nicolai Hähnle:
From: Nicolai Hähnle
A semantic error was introduced in a past refactoring that caused the bind
parameter to be passed into the use_reusable_pool parameter of buffer_create.
Since this clearly makes no sense, and there is no clear reason why the
ca
Fixes a Coverity defect by adding checks to see if a value is negative
before using it to index an array. By checking the value first it makes
the code more clean and it doesn't change the outcome of the function.
CID: 1355598
Signed-off-by: Jakob Sinclair
---
src/gallium/drivers/radeonsi/si_st
This patch fixes a Coverity defect. By checking if the value is negative before
using it to index an array it makes the code a bit safer and cleaner but it
should not actually change the outcome of the functions.
CID: 1355598
Jakob Sinclair (1):
radeonsi: check if value is negative
src/galli
https://bugs.freedesktop.org/show_bug.cgi?id=95079
Tobias Droste changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=92877
Tobias Droste changed:
What|Removed |Added
CC||legrand.cedric...@gmail.com
--- Comment
On Fri, Apr 22, 2016 at 04:19:08PM -0700, Jason Ekstrand wrote:
> Instead of having a virtual member function for getting the WM/PS kernel,
> we simply add fields for prog_data and the kernel to brw_blorp_parms and
> always make sure those get set as part of the different constructors.
> ---
> src
On Sat, Apr 23, 2016 at 01:09:43AM -0700, Kenneth Graunke wrote:
> On Saturday, April 23, 2016 5:39:02 PM PDT Jonathan Gray wrote:
> > src/intel/genxml/gen_pack_header.py requires python3.
> >
> > v2: check for python3.5 as well
> >
> > Signed-off-by: Jonathan Gray
> > Reviewed-by: Emil Velikov
https://bugs.freedesktop.org/show_bug.cgi?id=95079
Cédric Legrand changed:
What|Removed |Added
CC||legrand.cedric...@gmail.com
--
You are
https://bugs.freedesktop.org/show_bug.cgi?id=95079
Bug ID: 95079
Summary: GLX and OpenGL should be separated
Product: Mesa
Version: unspecified
Hardware: All
OS: All
Status: NEW
Severity: normal
This patch modifies r600_colorformat_endian_swap(), so for 16-bit and for
32-bit buffers, the endianess configuration will be determined not only
by the color/texture format, but also by the do_endian_swap parameter.
The only exception is for array formats, which are always set to not do
swapping,
Because r600 GPUs can't do swap in their DB unit, we need to disable
endianess swapping for textures that are handled by DB.
There are four format translation functions in r600g driver:
- r600_translate_texformat
- r600_colorformat_endian_swap
- r600_translate_colorformat
- r600_translate_colorsw
Hi,
v4:
Per marek's remarks I:
- removed all changes to evergreen_init_color_surface_rat(), as it is used
only in compute and don't handle DB surfaces.
- Set V_0280A0_COLOR_16_16 and V_0280A0_COLOR_16_16_FLOAT to always do 8IN16
endian swap (array formats that still need to do byte swap).
For some texture formats we need to take "do_endian_swap" into account
when configuring their swizzling.
Signed-off-by: Oded Gabbay
---
src/gallium/drivers/r600/r600_state_common.c | 35 +++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/src/gallium/driver
For some formats we need to take "do_endian_swap" into account when
configuring swapping for color buffers.
Signed-off-by: Oded Gabbay
---
src/gallium/drivers/r600/r600_state_common.c | 2 +-
src/gallium/drivers/radeon/r600_texture.c| 20 +---
2 files changed, 14 insertions(
On Saturday, April 23, 2016 5:39:02 PM PDT Jonathan Gray wrote:
> src/intel/genxml/gen_pack_header.py requires python3.
>
> v2: check for python3.5 as well
>
> Signed-off-by: Jonathan Gray
> Reviewed-by: Emil Velikov
> Reviewed-by: Kenneth Graunke
> ---
> configure.ac | 2 ++
> 1 file changed
Allows the build to work when the python3 binary is not "python3".
v2: remove x bit from the script at Emil's suggestion
Signed-off-by: Jonathan Gray
Reviewed-by: Emil Velikov
---
src/intel/genxml/Makefile.am| 4 +++-
src/intel/genxml/gen_pack_header.py | 0
2 files changed, 3 insertio
src/intel/genxml/gen_pack_header.py requires python3.
v2: check for python3.5 as well
Signed-off-by: Jonathan Gray
Reviewed-by: Emil Velikov
Reviewed-by: Kenneth Graunke
---
configure.ac | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configure.ac b/configure.ac
index 6b00cf9..2474078 1
Remove a wrapper around __builtin_ffs that conflicts with system
headers on OpenBSD and perhaps elsewhere:
isl_priv.h:44: error: conflicting types for 'ffs'
v2: include strings.h to ensure prototype is found
Signed-off-by: Jonathan Gray
---
src/intel/isl/isl_priv.h | 6 +-
1 file changed,
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