https://bugs.freedesktop.org/show_bug.cgi?id=92265
Michel Dänzer changed:
What|Removed |Added
CC||custos.men...@gmail.com
--- Comment #4 f
On Sat, Oct 3, 2015 at 11:13 AM, Jason Ekstrand wrote:
> On Fri, Oct 2, 2015 at 2:37 PM, Connor Abbott wrote:
>> Before, we would only do scheduling after register allocation if we
>> spilled, despite the fact that the pre-RA scheduler was only supposed to
>> be for register pressure and set the
---
docs/GL3.txt | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index e020deb..09c711f 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -178,7 +178,13 @@ GL 4.4, GLSL 4.40:
GL_MAX_VERTEX_ATTRIB_STRIDE DONE (all driv
Signed-off-by: Jan Vesely
---
include/c11/threads_posix.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/c11/threads_posix.h b/include/c11/threads_posix.h
index 3def6c4..ce9853b 100644
--- a/include/c11/threads_posix.h
+++ b/include/c11/threads_posix.h
@@ -136,8 +136,14 @@ cnd_
On Saturday, October 03, 2015 10:57:28 AM Matt Turner wrote:
> ---
> src/mesa/drivers/dri/i965/brw_vec4.h | 8
> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 10 --
> src/mesa/drivers/dri/i965/brw_vs.h | 5 -
> 3 files changed, 23 deletions(-)
>
>
https://bugs.freedesktop.org/show_bug.cgi?id=79783
gregory.hain...@gmail.com changed:
What|Removed |Added
Status|NEW |ASSIGNED
Assignee|m
https://bugs.freedesktop.org/show_bug.cgi?id=89599
--- Comment #5 from Marek Olšák ---
The patch should be sent to the mailing list.
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mesa
On Sat, Oct 3, 2015 at 2:50 PM, Matt Turner wrote:
> On Sat, Oct 3, 2015 at 11:31 AM, Ilia Mirkin wrote:
>> On Sat, Oct 3, 2015 at 1:57 PM, Matt Turner wrote:
>>> With NIR, it actually hurts things.
>>
>> Buuutt not everything uses NIR.
>
> Well...
>
>> Of course I'm sure it has a
>> similar
On Sat, Oct 3, 2015 at 11:31 AM, Ilia Mirkin wrote:
> On Sat, Oct 3, 2015 at 1:57 PM, Matt Turner wrote:
>> With NIR, it actually hurts things.
>
> Buuutt not everything uses NIR.
Well...
> Of course I'm sure it has a
> similarly negative effect with nouveau/codegen, but I'm not so sure
> a
On Sat, Oct 3, 2015 at 2:38 PM, Jason Ekstrand wrote:
> On Sat, Oct 3, 2015 at 11:32 AM, Ilia Mirkin wrote:
>> On Sat, Oct 3, 2015 at 2:28 PM, Jason Ekstrand wrote:
>>> On Sat, Oct 3, 2015 at 11:26 AM, Ilia Mirkin wrote:
On Sat, Oct 3, 2015 at 2:13 PM, Jason Ekstrand
wrote:
> On
On Sat, Oct 3, 2015 at 11:32 AM, Ilia Mirkin wrote:
> On Sat, Oct 3, 2015 at 2:28 PM, Jason Ekstrand wrote:
>> On Sat, Oct 3, 2015 at 11:26 AM, Ilia Mirkin wrote:
>>> On Sat, Oct 3, 2015 at 2:13 PM, Jason Ekstrand wrote:
On Fri, Oct 2, 2015 at 2:37 PM, Connor Abbott wrote:
> Before, w
On Sat, Oct 3, 2015 at 2:28 PM, Jason Ekstrand wrote:
> On Sat, Oct 3, 2015 at 11:26 AM, Ilia Mirkin wrote:
>> On Sat, Oct 3, 2015 at 2:13 PM, Jason Ekstrand wrote:
>>> On Fri, Oct 2, 2015 at 2:37 PM, Connor Abbott wrote:
Before, we would only do scheduling after register allocation if we
On Sat, Oct 3, 2015 at 1:57 PM, Matt Turner wrote:
> With NIR, it actually hurts things.
Buuutt not everything uses NIR. Of course I'm sure it has a
similarly negative effect with nouveau/codegen, but I'm not so sure
about things like nv30 which don't have an optimizing compiler
backend. IMHO
On Sat, Oct 3, 2015 at 11:26 AM, Ilia Mirkin wrote:
> On Sat, Oct 3, 2015 at 2:13 PM, Jason Ekstrand wrote:
>> On Fri, Oct 2, 2015 at 2:37 PM, Connor Abbott wrote:
>>> Before, we would only do scheduling after register allocation if we
>>> spilled, despite the fact that the pre-RA scheduler was
On Sat, Oct 3, 2015 at 2:13 PM, Jason Ekstrand wrote:
> On Fri, Oct 2, 2015 at 2:37 PM, Connor Abbott wrote:
>> Before, we would only do scheduling after register allocation if we
>> spilled, despite the fact that the pre-RA scheduler was only supposed to
>> be for register pressure and set the l
On Fri, Oct 2, 2015 at 2:37 PM, Connor Abbott wrote:
> Previously, we were using some heuristics to try and detect when a write
> was about to begin a live range, or when a read was about to end a live
> range. We never used the liveness analysis information used by the
> register allocator, thoug
On Fri, Oct 2, 2015 at 2:37 PM, Connor Abbott wrote:
> Before, we would only do scheduling after register allocation if we
> spilled, despite the fact that the pre-RA scheduler was only supposed to
> be for register pressure and set the latencies of every instruction to
> 1. This meant that unless
instructions in affected programs: 44204 -> 43762 (-1.00%)
helped:221
---
src/mesa/drivers/dri/i965/Makefile.sources | 2 +-
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
.../dri/i965/brw_fs_peephole_predicated_break.cpp | 149 -
---
src/mesa/drivers/dri/i965/brw_vec4.h | 8
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 10 --
src/mesa/drivers/dri/i965/brw_vs.h | 5 -
3 files changed, 23 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i
We're not using any fs_inst fields, and the next commit will make the
peephole used by the vec4 backend.
---
src/mesa/drivers/dri/i965/brw_fs_peephole_predicated_break.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_peephole_predicat
With NIR, it actually hurts things.
total instructions in shared programs: 6529329 -> 652 (-0.01%)
instructions in affected programs: 14833 -> 14392 (-2.97%)
helped:299
HURT: 1
In all affected programs I inspected (including
We never emit IF instructions with an embedded comparison (lost in the
switch to NIR), so this code is not used. If we want to readd support,
we should have a pass that merges a CMP instruction with an IF or a
WHILE instruction after other optimizations have run.
---
.../dri/i965/brw_fs_peephole_p
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_state_draw.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 43170ec..5face42 100644
--- a/src/gallium/drivers/radeon
From: Marek Olšák
Broken by one of the cleanups: 0d46c3bc9d09b376d74f7399e1a2d1b0a923640b
Not applicable to stable.
---
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_state_shaders.c | 18 ++
2 files changed, 19 insertions(+)
diff --git a
On Wed, Aug 13, 2014 at 10:07 AM, wrote:
> From: Ville Syrjälä
>
> i915 fragment programs utilize the texture coordinate registers
> for both texture coordinates and varyings. Unfortunately the
> code doesn't check if the same index might be in use for both.
> It just naively uses the index to p
https://bugs.freedesktop.org/show_bug.cgi?id=92265
--- Comment #3 from Emil Velikov ---
(In reply to Jason Ekstrand from comment #2)
> I'm going to hazard a guess and say that mesa is probably the only ES driver
> to support GL_EXT_abgr.
>
Sounds about right according to ilia's glxinfo list
htt
https://bugs.freedesktop.org/show_bug.cgi?id=92265
Jason Ekstrand changed:
What|Removed |Added
CC||i...@freedesktop.org,
Jordan Justen writes:
> From: Francisco Jerez
>
> Fixes
> arb_shader_image_load_store/execution/load-from-cleared-image.shader_test
>
> Cc: Chris Wilson
> Cc: Jason Ekstrand
> Tested-by: Jordan Justen
> ---
> RE: i965: Perform an explicit flush after doing _mesa_meta_pbo_TexSubImage
>
> cu
https://bugs.freedesktop.org/show_bug.cgi?id=92265
Boyan Ding changed:
What|Removed |Added
Component|EGL/Wayland |Mesa core
Assignee|wayland-bugs@l
Mesa 10.6.9 is now available.
This release covers KDE crashes with i965, regression in Unreal Tournament
with gallium drivers, fixes for Redway3D Flat (Demo) and Astromenace.
The mangled GL build has also been fixed.
NOTE: It is anticipated that 10.6.9 will be the final release in the 10.6
series
https://bugs.freedesktop.org/show_bug.cgi?id=92265
Boyan Ding changed:
What|Removed |Added
CC||el...@igalia.com
--- Comment #1 from Boyan
On 24 September 2015 at 13:20, Emil Velikov wrote:
> Hi all,
>
> On 16 September 2015 at 16:38, Emil Velikov wrote:
>> From: Matthew Waters
>>
>> Move all the enums but CONTEXT_FLAGS. The spec seems quite explicit
>> about the latter (wrt OpenGL ES)
>>
>> "In OpenGL ES versions prior to and
https://bugs.freedesktop.org/show_bug.cgi?id=91044
Emil Velikov changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
On 3 October 2015 at 02:12, Marek Olšák wrote:
> I'm not sure if this is correct or if we should just return NULL in
> this case like the "case" statement above that does.
>
Actually I was thinking about bailing out when the requested attribute
is set. I.e.
diff --git a/src/egl/drivers/dri2/egl_d
Not sure if this series in general was discarded after Matt's second
email on "Add a pass to predicate short blocks", but in any case, I find
this specific patch useful and LGTM. Just in case you were expecting for
someone taking a look to it:
Reviewed-by: Alejandro Piñeiro
On 29/09/15 00:26, M
https://bugs.freedesktop.org/show_bug.cgi?id=77449
Bug 77449 depends on bug 91342, which changed state.
Bug 91342 Summary: Very dark textures on some objects in indoors environments
in Postal 2
https://bugs.freedesktop.org/show_bug.cgi?id=91342
What|Removed |Ad
On Sat, 03 Oct 2015 09:35:49 +
Mike Lothian wrote:
> Would it be better to have is_interstage=0 rather than a double negative?
>
Yes. I think it just need to set 1 in the constructor (forget to
update it by the way...) as default value. Otherwise it can be
renamed to is_unlinked_io (or som
Would it be better to have is_interstage=0 rather than a double negative?
On Sat, 3 Oct 2015 10:32 am Gregory Hainaut
wrote:
> > In short, SSO allow to match by name but you can't make any hypothesis
> on the
> > previous/next stage. Therefore you must consider all inputs and output as
> > activ
> In short, SSO allow to match by name but you can't make any hypothesis on the
> previous/next stage. Therefore you must consider all inputs and output as
> actives.
New version based on Ian's feedbacks.
* Real interstage variables of the program are still optimized
* Both output and input of th
GL_ARB_separate_shader_objects allow to match by name variable or block
interface. Input varying can't be removed as it is will impact the location
assignment.
It fixes the bug 79783 and likely any application that uses
GL_ARB_separate_shader_objects extension.
Signed-off-by: Gregory Hainaut
---
Signed-off-by: Gregory Hainaut
---
src/glsl/linker.cpp | 47 +++
1 file changed, 47 insertions(+)
diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index fd69dbc..a4a8ab4 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -3378,6 +3378,
The negative form was used to keep interstage as the default value
Note: I put the ir_set_not_interstage_io function in opt_dead_code
because it will be used to disable deadcode optimization. Feel free
to point me a better place if it exists.
Signed-off-by: Gregory Hainaut
---
src/glsl/ir.h
Hi Emil,
Am Freitag, 2. Oktober 2015, 18:55:47 schrieb Emil Velikov:
> Hi Marc,
>
> On 29 September 2015 at 10:31, Marc Dietrich wrote:
> > As expressed before, using hidden attribute only hides some hack on how to
> > find the head of the dispatch entry table afaict.
> >
> > I just replaced it
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