On 31/03/15 17:46, Brian Paul wrote:
On 03/31/2015 08:42 AM, Martin Peres wrote:
The issue has been detected by coverty.
v2:
- move the declaration of obj to the else clause (Brian Paul)
v3: Review by Brian Paul
- get rid of the obj declaration in favor of a direct reference
Signed-off-by: Ma
On Tue, Mar 31, 2015 at 8:41 AM, Ryan Houdek wrote:
> I'm proposing changing from explicitly disallowing token pasting in OpenGL
> ES to allowing it in a similar fashion to desktop OpenGL.
> I'm proposing this for multiple reasons:
> - The Dolphin emulator uses it, and has been broken with Mes
On 01.04.2015 00:36, Roland Scheidegger wrote:
> Am 31.03.2015 um 08:33 schrieb Michel Dänzer:
>> From: Michel Dänzer
>>
>> Signed-off-by: Michel Dänzer
>> ---
>> src/gallium/auxiliary/gallivm/lp_bld_debug.cpp | 5 +
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/src/gallium/auxiliary
---
src/gallium/state_trackers/clover/core/kernel.cpp | 1 +
src/gallium/state_trackers/clover/core/module.hpp | 9 +
src/gallium/state_trackers/clover/llvm/invocation.cpp | 6 +-
3 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/src/gallium/state_trackers/clover/
I'm proposing changing from explicitly disallowing token pasting in OpenGL
ES to allowing it in a similar fashion to desktop OpenGL.
I'm proposing this for multiple reasons:
- The Dolphin emulator uses it, and has been broken with Mesa's OpenGL
ES for a number of months.
- A number of propr
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hi,
could you use the same ordering as in the 1965 patch?
scale[0]
scale[1]
scale[2]
translate[0]
translate[1]
translate[2]
This simplifies reading and comparing a lot.
Best wishes
Michael
-BEGIN PGP SIGNATURE-
Version: GnuPG v2.0.22 (GNU/L
On Tue, Mar 31, 2015 at 9:03 PM, Roland Scheidegger wrote:
> Am 01.04.2015 um 00:57 schrieb Rob Clark:
>> From: Rob Clark
>>
>> Based on the algo from NV50LegalizeSSA::handleDIV() and handleMOD().
>> See also trans_idiv() in freedreno/ir3/ir3_compiler.c (which was an
>> adaptation of the nv50 cod
On Tue, Mar 31, 2015 at 8:54 PM, Kenneth Graunke wrote:
> On Tuesday, March 31, 2015 06:57:30 PM Rob Clark wrote:
>> From: Rob Clark
>>
>> In freedreno these get implemented as the matching f* instruction plus a
>> u2f to convert the result to float 1.0/0.0. But less lines of code to
>> just let
Am 01.04.2015 um 00:57 schrieb Rob Clark:
> From: Rob Clark
>
> Based on the algo from NV50LegalizeSSA::handleDIV() and handleMOD().
> See also trans_idiv() in freedreno/ir3/ir3_compiler.c (which was an
> adaptation of the nv50 code from Ilia).
>
> Just sending as an rfc right now, since I'm not
Thank you Ilia and Roland for the information and prompt response.
Shervin
On Tue, Mar 31, 2015 at 1:18 PM, Roland Scheidegger
wrote:
> FWIW this works by emulation of these formats - mesa will uncompress
> them when specified to some uncompressed format. This means though
> there's zero bene
Reviewed-by: Mark Janes
Eduardo Lima Mitev writes:
> From: Iago Toral Quiroga
>
> Even if they only have one slice, otherwise textureSize() won't
> produce correct results for the depth value.
>
> Fixes 10 dEQP tests in this category:
> dEQP-GLES3.functional.shaders.texture_functions.texturesi
On Tuesday, March 31, 2015 06:57:30 PM Rob Clark wrote:
> From: Rob Clark
>
> In freedreno these get implemented as the matching f* instruction plus a
> u2f to convert the result to float 1.0/0.0. But less lines of code to
> just let nir_opt_algebraic handle this for us, plus opens up some small
On Tue, Mar 31, 2015 at 6:57 PM, Rob Clark wrote:
> From: Rob Clark
>
> Based on the algo from NV50LegalizeSSA::handleDIV() and handleMOD().
> See also trans_idiv() in freedreno/ir3/ir3_compiler.c (which was an
> adaptation of the nv50 code from Ilia).
>
> Just sending as an rfc right now, since
Thanks Emil. Both are
Reviewed-by: Matt Turner
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
On Tue, Mar 31, 2015 at 4:06 PM, Matt Turner wrote:
> On Tue, Mar 31, 2015 at 3:57 PM, Rob Clark wrote:
>> From: Rob Clark
>>
>> Signed-off-by: Rob Clark
>> ---
>
> It's not just a description -- it's the expression used for constant
> evaluation. Presumably the mistake hasn't caused problems b
On Tue, Mar 31, 2015 at 6:57 PM, Rob Clark wrote:
> From: Rob Clark
>
> Signed-off-by: Rob Clark
> ---
> src/glsl/nir/nir_opcodes.py | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/glsl/nir/nir_opcodes.py b/src/glsl/nir/nir_opcodes.py
> index 062cd62..b92fc7e 10
On Tue, Mar 31, 2015 at 3:57 PM, Rob Clark wrote:
> From: Rob Clark
>
> Freedreno and vc4 want this behavior for the time being (until we have
> real flow control). Even after that, we probably want to turn this into
> some sort of driver tunable threshold, since for at least some hardware,
> re
On Tue, Mar 31, 2015 at 3:57 PM, Rob Clark wrote:
> From: Rob Clark
>
> Signed-off-by: Rob Clark
> ---
It's not just a description -- it's the expression used for constant
evaluation. Presumably the mistake hasn't caused problems because
optimizations in GLSL IR evaluated any f2b and i2b of a c
From: Rob Clark
Freedreno and vc4 want this behavior for the time being (until we have
real flow control). Even after that, we probably want to turn this into
some sort of driver tunable threshold, since for at least some hardware,
reasonably large if/else is best flattend rather than having div
From: Rob Clark
Based on the algo from NV50LegalizeSSA::handleDIV() and handleMOD().
See also trans_idiv() in freedreno/ir3/ir3_compiler.c (which was an
adaptation of the nv50 code from Ilia).
Just sending as an rfc right now, since I'm not quite at the point to be
able to test it on actual hw.
From: Rob Clark
In freedreno these get implemented as the matching f* instruction plus a
u2f to convert the result to float 1.0/0.0. But less lines of code to
just let nir_opt_algebraic handle this for us, plus opens up some small
window for other opt passes to improve (ie. if some shader ended
From: Rob Clark
Signed-off-by: Rob Clark
---
src/glsl/nir/nir_opcodes.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/glsl/nir/nir_opcodes.py b/src/glsl/nir/nir_opcodes.py
index 062cd62..b92fc7e 100644
--- a/src/glsl/nir/nir_opcodes.py
+++ b/src/glsl/nir/nir_opcod
On Wed, Feb 11, 2015 at 2:54 PM, Matt Turner wrote:
> mul x, -y is equivalent to mul -x, y; and mul x, y is the negation of
> mul x, -y.
>
> total instructions in shared programs: 5937689 -> 5929512 (-0.14%)
> instructions in affected programs: 871152 -> 862975 (-0.94%)
> helped:
On Tuesday, March 31, 2015 08:33:24 AM mathias.froehl...@gmx.net wrote:
> From: Mathias Fröhlich
>
> Hi,
>
> The patch aims to implement ARB_clip_control on intel chips.
> I hope to have found all places to cover all supported chipsets.
> I have done some limited testing on an Ivybridge Mobile a
On Tue, Mar 31, 2015 at 12:13 PM, Chris Forbes wrote:
> I'd adjust the write to surf[0] to use surf_type too.
I'll fix that. Thanks.
>
> Other than that, this patch is:
>
> Reviewed-by: Chris Forbes
>
> On Tue, Mar 31, 2015 at 10:04 AM, Anuj Phogat wrote:
>> Makes no functional changes in the co
FWIW this works by emulation of these formats - mesa will uncompress
them when specified to some uncompressed format. This means though
there's zero benefit in using them over uncompressed formats (same
memory requirements and performance when texturing, just increased
overhead when specifying the
On Tuesday, March 31, 2015 01:02:40 PM Matt Turner wrote:
> ---
> No changes to the generated code (functions are marked as inline, so
> the compiler can figure this out, I guess).
>
> src/mesa/drivers/dri/i965/brw_inst.h | 24
> 1 file changed, 12 insertions(+), 12 delet
---
No changes to the generated code (functions are marked as inline, so
the compiler can figure this out, I guess).
src/mesa/drivers/dri/i965/brw_inst.h | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_inst.h
b/src/mesa
I'd adjust the write to surf[0] to use surf_type too.
Other than that, this patch is:
Reviewed-by: Chris Forbes
On Tue, Mar 31, 2015 at 10:04 AM, Anuj Phogat wrote:
> Makes no functional changes in the code.
>
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/gen8_surface_state.
It should work fine, AFAIK. It's required by ES 3.0, and as you can
see, llvmpipe exposes ES 3.0 contexts:
http://people.freedesktop.org/~imirkin/glxinfo/glxinfo.html#p=es
On Tue, Mar 31, 2015 at 3:03 PM, Shervin Sharifi wrote:
> Hi,
>
> I was wondering what's the status of ETC2 support with ll
Hi,
I was wondering what's the status of ETC2 support with llvmpipe backend.
Thanks,
Shervin
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
On Tue, Mar 31, 2015 at 2:33 PM, Matt Turner wrote:
> On Tue, Mar 31, 2015 at 11:30 AM, Rob Clark wrote:
>> On Tue, Mar 31, 2015 at 2:20 PM, Matt Turner wrote:
>>> Alternatively, Jason's implemented a pass to "resolve" booleans to
>>> these values, which is necessary for us on i965 Gen4 and Gen5
On Tue, Mar 31, 2015 at 11:30 AM, Rob Clark wrote:
> On Tue, Mar 31, 2015 at 2:20 PM, Matt Turner wrote:
>> Alternatively, Jason's implemented a pass to "resolve" booleans to
>> these values, which is necessary for us on i965 Gen4 and Gen5. You
>> could probably use that.
>
> ok, is that already
On Tue, Mar 31, 2015 at 2:20 PM, Matt Turner wrote:
> On Tue, Mar 31, 2015 at 11:11 AM, Rob Clark wrote:
>> On Tue, Mar 31, 2015 at 2:03 PM, Kenneth Graunke
>> wrote:
>>> I'm pretty sure you want b2f here, not u2f...the slt/sge/seq/sne opcodes
>>> are defined to return either 0.0 or 1.0. flt a
On Tue, Mar 31, 2015 at 11:11 AM, Rob Clark wrote:
> On Tue, Mar 31, 2015 at 2:03 PM, Kenneth Graunke
> wrote:
>> I'm pretty sure you want b2f here, not u2f...the slt/sge/seq/sne opcodes
>> are defined to return either 0.0 or 1.0. flt and friends return 0 or
>> 0x. u2f converts the num
On Tue, Mar 31, 2015 at 2:11 PM, Rob Clark wrote:
> On Tue, Mar 31, 2015 at 2:03 PM, Kenneth Graunke
> wrote:
>> On Tuesday, March 31, 2015 11:30:17 AM Rob Clark wrote:
>>> From: Rob Clark
>>>
>>> In freedreno these get implemented as the matching f* instruction plus a
>>> u2f to convert the re
On Mon, Mar 23, 2015 at 8:13 PM, Jason Ekstrand wrote:
> ---
> src/glsl/Makefile.sources| 1 +
> src/glsl/nir/nir_opt_peephole_ffma.c | 220
> +++
> 2 files changed, 221 insertions(+)
> create mode 100644 src/glsl/nir/nir_opt_peephole_ffma.c
>
> dif
On Tue, Mar 31, 2015 at 2:03 PM, Kenneth Graunke wrote:
> On Tuesday, March 31, 2015 11:30:17 AM Rob Clark wrote:
>> From: Rob Clark
>>
>> In freedreno these get implemented as the matching f* instruction plus a
>> u2f to convert the result to float 1.0/0.0. But less lines of code to
>> just let
https://bugs.freedesktop.org/show_bug.cgi?id=89624
--- Comment #4 from Dan Sebald ---
The attached images aren't very precise. There is a Piglit test here:
https://bugs.freedesktop.org/attachment.cgi?id=114711
that might be more helpful. The difference between the following two
illustrations
On Tue, Mar 31, 2015 at 10:46 AM, Matt Turner wrote:
> On Mon, Mar 23, 2015 at 8:13 PM, Jason Ekstrand wrote:
>> This series contains several optimization-related patches that are all
>> focussed around being able to do better at emitting MAD instructions.
>>
>> Final shader-db results for the wh
On Mon, Mar 23, 2015 at 8:43 PM, Jason Ekstrand wrote:
> On Mon, Mar 23, 2015 at 8:34 PM, Matt Turner wrote:
>> On Mon, Mar 23, 2015 at 8:13 PM, Jason Ekstrand wrote:
>>> total instructions in shared programs: 4422307 -> 4422363 (0.00%)
>>> instructions in affected programs: 4230 -> 4286 (1.
On Tuesday, March 31, 2015 11:30:17 AM Rob Clark wrote:
> From: Rob Clark
>
> In freedreno these get implemented as the matching f* instruction plus a
> u2f to convert the result to float 1.0/0.0. But less lines of code to
> just let nir_opt_algebraic handle this for us, plus opens up some small
On Thu, Mar 19, 2015 at 6:40 PM, Robert Bragg wrote:
> Hi Samuel,
>
> I thought I should let you and others know of some related changes
> I've been playing around with to try and improve our support for the
> INTEL_performance_query extension in the i965 dri driver, since it's
> quite related to
On Mon, Mar 23, 2015 at 8:40 PM, Jason Ekstrand wrote:
> On Mon, Mar 23, 2015 at 8:34 PM, Matt Turner wrote:
>> On Mon, Mar 23, 2015 at 8:13 PM, Jason Ekstrand wrote:
>>> The idea here is that fusing multiply-add combinations too early can reduce
>>> our ability to perform CSE and value-numberin
On Mon, Mar 23, 2015 at 8:13 PM, Jason Ekstrand wrote:
> This series contains several optimization-related patches that are all
> focussed around being able to do better at emitting MAD instructions.
>
> Final shader-db results for the whole series on Haswell:
>
>total NIR instructions in shar
On Tue, Mar 31, 2015 at 6:58 AM, Neil Roberts wrote:
> Commit cf67ca9ffa9 made the layouting code pick a special layout for
> 1D images on Skylake. This should not be used for depth and stencil
> buffers because these need to be treated as 2D tiled images. However
> the patch was missing a check f
Emil Velikov writes:
> The header was added with commit 2a135c470e3(nir: Add an ALU op builder
> kind of like ir_builder.h) but did not made it into to the sources list.
>
> Fortunately it remained unused until a recent commit faf6106c6f6(nir:
> Implement a Mesa IR -> NIR translator.)
>
> v2: Rem
Thomas Helland writes:
> On 31 Mar 2015 02:19, "Eric Anholt" wrote:
>>
>> Thomas Helland writes:
>>
>> > This should give better cache locality, less memory consumption,
>> > less code, and should also be faster since we avoid a modulo operation.
>> > Also change table size to be power of two.
Reviewed-by: Matt Turner
Thanks!
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Hello Robert,
Sorry for the delay, I just saw your message few days ago, and I
probably removed the mail by mistake too...
I have never heard about your work on this area, happy to know right now. :)
Well, regarding the backend stuff, I would prefer to keep the same for
both GL_AMD_performan
On 31.03.2015 17:22, Leo Liu wrote:
This will help encoding VUI into the bitstream
v2: make backward compatible
Signed-off-by: Leo Liu
---
src/gallium/drivers/radeon/radeon_vce.c| 6 ++-
src/gallium/drivers/radeon/radeon_vce.h| 2 +
src/gallium/drivers/radeon/radeon_vce_4
On 03/31/2015 12:37 AM, mathias.froehl...@gmx.net wrote:
From: Mathias Froehlich
This is the only real user of _WindowMap which has the depth
buffer scaling multiplied in. Maintain the _WindowMap of the
one and only viewport inside TNLcontext.
Signed-off-by: Mathias Froehlich
---
src/mesa/s
This will help encoding VUI into the bitstream
v2: make backward compatible
Signed-off-by: Leo Liu
---
src/gallium/drivers/radeon/radeon_vce.c| 6 ++-
src/gallium/drivers/radeon/radeon_vce.h| 2 +
src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 53 ++
Am 31.03.2015 um 08:33 schrieb Michel Dänzer:
> From: Michel Dänzer
>
> Signed-off-by: Michel Dänzer
> ---
> src/gallium/auxiliary/gallivm/lp_bld_debug.cpp | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp
> b/src/gallium/auxiliary/ga
From: Rob Clark
In freedreno these get implemented as the matching f* instruction plus a
u2f to convert the result to float 1.0/0.0. But less lines of code to
just let nir_opt_algebraic handle this for us, plus opens up some small
window for other opt passes to improve (ie. if some shader ended
Right. I actually thought I already pushed this but turns out I didn't...
Roland
Am 30.03.2015 um 17:46 schrieb Ilia Mirkin:
> Perhaps mention that llvmpipe now supports ARB_texture_gather in
> GL3.txt and relnotes/10.6.0.html?
>
> On Sun, Mar 29, 2015 at 8:12 PM, wrote:
>> From: Roland Scheid
On 03/31/2015 08:42 AM, Martin Peres wrote:
The issue has been detected by coverty.
v2:
- move the declaration of obj to the else clause (Brian Paul)
v3: Review by Brian Paul
- get rid of the obj declaration in favor of a direct reference
Signed-off-by: Martin Peres
---
src/mesa/main/fbobje
The issue has been detected by coverty.
v2:
- move the declaration of obj to the else clause (Brian Paul)
v3: Review by Brian Paul
- get rid of the obj declaration in favor of a direct reference
Signed-off-by: Martin Peres
---
src/mesa/main/fbobject.c | 9 +++--
1 file changed, 3 insertion
On 31/03/15 17:31, Brian Paul wrote:
On 03/31/2015 03:32 AM, Martin Peres wrote:
The issue has been detected by coverty.
v2:
- move the declaration of obj to the else clause (Brian Paul)
Signed-off-by: Martin Peres
---
src/mesa/main/fbobject.c | 5 ++---
1 file changed, 2 insertions(+), 3
Tom Stellard writes:
> v2:
> - Only call notification for build errors
> - Fix clCompileProgram()
>
> Cc: 10.5 10.4
> ---
> src/gallium/state_trackers/clover/api/program.cpp | 16 ++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/state_trackers
On 03/31/2015 03:32 AM, Martin Peres wrote:
The issue has been detected by coverty.
v2:
- move the declaration of obj to the else clause (Brian Paul)
Signed-off-by: Martin Peres
---
src/mesa/main/fbobject.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/mesa/ma
Tom Stellard writes:
> v2:
> - Don't use _errs map
>
> Cc: 10.5 10.4
Reviewed-by: Francisco Jerez
> ---
> src/gallium/state_trackers/clover/core/program.cpp | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/src/gallium/state_trackers/clover/core/program.cpp
> b/src/gallium/state_
Iago Toral Quiroga writes:
> This is a problem when we have IR like this:
>
> (array_ref (var_ref temps) (swiz x (expression ivec4 bitcast_f2i
>(swiz (array_ref (var_ref temps) (constant int (2)) ) )) )) ) )
>
> where we are indexing an array with the result of an expression that
> acces
Commit cf67ca9ffa9 made the layouting code pick a special layout for
1D images on Skylake. This should not be used for depth and stencil
buffers because these need to be treated as 2D tiled images. However
the patch was missing a check for images with a base format of
GL_STENCIL_INDEX. In practice
On Tue, 31 Mar 2015 07:27:50 +0200, Dave Airlie wrote:
From: Dave Airlie
This code to handle absolute values on op3 srcs was a bit too simple,
it really needs a temp reg per src, not one per channel, make it
easier and let sb clean up the mess.
Bugzilla: https://bugs.freedesktop.org/show_bug
It looks good to me.
Marek
On Tue, Mar 31, 2015 at 9:39 AM, Samuel Pitoiset
wrote:
>
>
> On 03/30/2015 11:17 PM, Marek Olšák wrote:
>>
>> You can add a flag to each driver query identifying what kind of query
>> it is (a hw perf counter or a CPU-only query). Then you can enumerate
>> all queries
The header was added with commit 2a135c470e3(nir: Add an ALU op builder
kind of like ir_builder.h) but did not made it into to the sources list.
Fortunately it remained unused until a recent commit faf6106c6f6(nir:
Implement a Mesa IR -> NIR translator.)
v2: Remove the bogus dependency. Tweak com
The issue has been detected by coverty.
v2:
- move the declaration of obj to the else clause (Brian Paul)
Signed-off-by: Martin Peres
---
src/mesa/main/fbobject.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index 0
On 31 Mar 2015 02:19, "Eric Anholt" wrote:
>
> Thomas Helland writes:
>
> > This should give better cache locality, less memory consumption,
> > less code, and should also be faster since we avoid a modulo operation.
> > Also change table size to be power of two.
> > This gives better performance
On 31/03/15 07:33, Michel Dänzer wrote:
From: Michel Dänzer
Signed-off-by: Michel Dänzer
---
src/gallium/auxiliary/gallivm/lp_bld_debug.cpp | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp
b/src/gallium/auxiliary/gallivm/lp_bld_debug.c
On 03/30/2015 11:17 PM, Marek Olšák wrote:
You can add a flag to each driver query identifying what kind of query
it is (a hw perf counter or a CPU-only query). Then you can enumerate
all queries and see if there's at least one perf counter and if so,
advertise the extension.
Or add a CAP and
This is a problem when we have IR like this:
(array_ref (var_ref temps) (swiz x (expression ivec4 bitcast_f2i
(swiz (array_ref (var_ref temps) (constant int (2)) ) )) )) ) )
where we are indexing an array with the result of an expression that
accesses the same array.
In this scenario, te
72 matches
Mail list logo
