Re: [lttng-dev] [PATCH urcu] Add support for the RISC-V architecture

2018-03-23 Thread Mathieu Desnoyers
- On Mar 23, 2018, at 5:22 PM, Michael Jeanson mjean...@efficios.com wrote: > On 2018-03-21 19:00, Mathieu Desnoyers wrote: >> - On Mar 21, 2018, at 5:38 PM, Michael Jeanson mjean...@efficios.com >> wrote: >> >>> Tested in QEMU 2.12.0-rc0, requires --disable-compiler-tls to go >>> throu

Re: [lttng-dev] [PATCH urcu] Add support for the RISC-V architecture

2018-03-23 Thread Michael Jeanson
On 2018-03-21 19:00, Mathieu Desnoyers wrote: > - On Mar 21, 2018, at 5:38 PM, Michael Jeanson mjean...@efficios.com > wrote: > >> Tested in QEMU 2.12.0-rc0, requires --disable-compiler-tls to go >> through the benchmarks reliably. > > Is it possible to find a RISC-V board in the wild ? (for

Re: [lttng-dev] [PATCH urcu] Add support for the RISC-V architecture

2018-03-21 Thread Mathieu Desnoyers
- On Mar 21, 2018, at 5:38 PM, Michael Jeanson mjean...@efficios.com wrote: > Tested in QEMU 2.12.0-rc0, requires --disable-compiler-tls to go > through the benchmarks reliably. Is it possible to find a RISC-V board in the wild ? (for testing ?) I've seen gcc builtins get it wrong barrier-wi

[lttng-dev] [PATCH urcu] Add support for the RISC-V architecture

2018-03-21 Thread Michael Jeanson
Tested in QEMU 2.12.0-rc0, requires --disable-compiler-tls to go through the benchmarks reliably. Signed-off-by: Michael Jeanson --- configure.ac | 1 + include/Makefile.am | 2 ++ include/urcu/arch/riscv.h| 49 include/