----- On Mar 21, 2018, at 5:38 PM, Michael Jeanson mjean...@efficios.com wrote:
> Tested in QEMU 2.12.0-rc0, requires --disable-compiler-tls to go
> through the benchmarks reliably.
Is it possible to find a RISC-V board in the wild ? (for testing ?)
I've seen gcc builtins get it wrong barrier-wise on some architectures
in the past, so I'd really like to test on proper hardware.
Thanks,
Mathieu
>
> Signed-off-by: Michael Jeanson <mjean...@efficios.com>
> ---
> configure.ac | 1 +
> include/Makefile.am | 2 ++
> include/urcu/arch/riscv.h | 49 ++++++++++++++++++++++++++++++++++++++++++++
> include/urcu/uatomic/riscv.h | 44 +++++++++++++++++++++++++++++++++++++++
> 4 files changed, 96 insertions(+)
> create mode 100644 include/urcu/arch/riscv.h
> create mode 100644 include/urcu/uatomic/riscv.h
>
> diff --git a/configure.ac b/configure.ac
> index d0b4a9a..9145081 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -151,6 +151,7 @@ AS_CASE([$host_cpu],
> [tile*], [ARCHTYPE="tile"],
> [hppa*], [ARCHTYPE="hppa"],
> [m68k], [ARCHTYPE="m68k"],
> + [riscv*], [ARCHTYPE="riscv"],
> [ARCHTYPE="unknown"]
> )
>
> diff --git a/include/Makefile.am b/include/Makefile.am
> index dcdf304..36667b4 100644
> --- a/include/Makefile.am
> +++ b/include/Makefile.am
> @@ -27,6 +27,7 @@ EXTRA_DIST = urcu/arch/aarch64.h \
> urcu/arch/mips.h \
> urcu/arch/nios2.h \
> urcu/arch/ppc.h \
> + urcu/arch/riscv.h \
> urcu/arch/s390.h \
> urcu/arch/sparc64.h \
> urcu/arch/tile.h \
> @@ -43,6 +44,7 @@ EXTRA_DIST = urcu/arch/aarch64.h \
> urcu/uatomic/mips.h \
> urcu/uatomic/nios2.h \
> urcu/uatomic/ppc.h \
> + urcu/uatomic/riscv.h \
> urcu/uatomic/s390.h \
> urcu/uatomic/sparc64.h \
> urcu/uatomic/tile.h \
> diff --git a/include/urcu/arch/riscv.h b/include/urcu/arch/riscv.h
> new file mode 100644
> index 0000000..1fd7d62
> --- /dev/null
> +++ b/include/urcu/arch/riscv.h
> @@ -0,0 +1,49 @@
> +#ifndef _URCU_ARCH_RISCV_H
> +#define _URCU_ARCH_RISCV_H
> +
> +/*
> + * arch/riscv.h: definitions for the RISC-V architecture
> + *
> + * Copyright (c) 2018 Michael Jeanson <mjean...@efficios.com>
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301
> USA
> + */
> +
> +#include <urcu/compiler.h>
> +#include <urcu/config.h>
> +#include <urcu/syscall-compat.h>
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include <stdlib.h>
> +#include <sys/time.h>
> +
> +/*
> + * On Linux, define the membarrier system call number if not yet available in
> + * the system headers.
> + */
> +#if (defined(__linux__) && !defined(__NR_membarrier))
> +#define __NR_membarrier 283
> +#endif
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#include <urcu/arch/generic.h>
> +
> +#endif /* _URCU_ARCH_RISCV_H */
> diff --git a/include/urcu/uatomic/riscv.h b/include/urcu/uatomic/riscv.h
> new file mode 100644
> index 0000000..a6700e1
> --- /dev/null
> +++ b/include/urcu/uatomic/riscv.h
> @@ -0,0 +1,44 @@
> +/*
> + * Atomic exchange operations for the RISC-V architecture. Let GCC do it.
> + *
> + * Copyright (c) 2018 Michael Jeanson <mjean...@efficios.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> copy
> + * of this software and associated documentation files (the "Software"), to
> + * deal in the Software without restriction, including without limitation the
> + * rights to use, copy, modify, merge, publish, distribute, sublicense,
> and/or
> + * sell copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> THE
> + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#ifndef _URCU_ARCH_UATOMIC_RISCV_H
> +#define _URCU_ARCH_UATOMIC_RISCV_H
> +
> +#include <urcu/compiler.h>
> +#include <urcu/system.h>
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#define UATOMIC_HAS_ATOMIC_BYTE
> +#define UATOMIC_HAS_ATOMIC_SHORT
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#include <urcu/uatomic/generic.h>
> +
> +#endif /* _URCU_ARCH_UATOMIC_RISCV_H */
> --
> 2.7.4
--
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com
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