[llvm-commits] CVS: llvm/include/llvm/CodeGen/Passes.h LinkAllCodegenComponents.h

Changes in directory llvm/include/llvm/CodeGen: Passes.h updated: 1.27 -> 1.28 LinkAllCodegenComponents.h updated: 1.5 -> 1.6 --- Log message: check in the BigBlock local register allocator --- Diffs of the changes: (+10 -0) LinkAllCodegenComponents.h |1 + Passes.h

[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocBigBlock.cpp

Changes in directory llvm/lib/CodeGen: RegAllocBigBlock.cpp added (r1.1) --- Log message: check in the BigBlock local register allocator --- Diffs of the changes: (+852 -0) RegAllocBigBlock.cpp | 852 +++ 1 files changed, 852 insertions(+)

Re: [llvm-commits] CVS: llvm/lib/CodeGen/RegAllocBigBlock.cpp

Hi Duraid .. This looks nifty. Thanks for adding it. Some minor comments ... Reid. Duraid Madina wrote: >Changes in directory llvm/lib/CodeGen: > >RegAllocBigBlock.cpp added (r1.1) >--- >Log message: > >check in the BigBlock local register allocator > > > >--- >Diffs of the changes: (+852 -0)

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMISelLowering.h

Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.58 -> 1.59 ARMISelLowering.h updated: 1.17 -> 1.18 --- Log message: Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from TargetLowering to SelectionDAG so that they have more convenient access to the curr

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86ISelLowering.h

Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.149 -> 1.150 X86ISelLowering.cpp updated: 1.413 -> 1.414 X86ISelLowering.h updated: 1.100 -> 1.101 --- Log message: Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from TargetLowering to SelectionDAG so t

[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/Sparc: SparcISelDAGToDAG.cpp updated: 1.122 -> 1.123 --- Log message: Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from TargetLowering to SelectionDAG so that they have more convenient access to the current DAG, in preparation for the Va

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCISelLowering.h

Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.230 -> 1.231 PPCISelLowering.cpp updated: 1.274 -> 1.275 PPCISelLowering.h updated: 1.65 -> 1.66 --- Log message: Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from TargetLowering to SelectionDAG so

[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h

Changes in directory llvm/include/llvm/CodeGen: SelectionDAG.h updated: 1.150 -> 1.151 --- Log message: Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from TargetLowering to SelectionDAG so that they have more convenient access to the current DAG, in preparation for the Value

[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h

Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.128 -> 1.129 --- Log message: Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from TargetLowering to SelectionDAG so that they have more convenient access to the current DAG, in preparation for the Valu

[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/Alpha: AlphaISelDAGToDAG.cpp updated: 1.70 -> 1.71 --- Log message: Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from TargetLowering to SelectionDAG so that they have more convenient access to the current DAG, in preparation for the Valu

Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp

On Jun 22, 2007, at 7:59 AM, Dan Gohman wrote: > Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from > TargetLowering to SelectionDAG so that they have more convenient > access to the current DAG, in preparation for the ValueType routines > being changed from standalone functio

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td

Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.113 -> 1.114 --- Log message: Fix the build. --- Diffs of the changes: (+1 -1) ARMInstrInfo.td |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target

[llvm-commits] CVS: llvm/lib/Transforms/Scalar/GVNPRE.cpp

Changes in directory llvm/lib/Transforms/Scalar: GVNPRE.cpp updated: 1.52 -> 1.53 --- Log message: Remove some code that I was using for collecting performance information that should not have been committed. --- Diffs of the changes: (+18 -18) GVNPRE.cpp | 36 ++

Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrFPStack.td X86InstrInfo.cpp X86InstrInfo.h X86InstrInfo.td X86InstrMMX.td X86InstrSSE.td

>> How about this proposal (Obviously feel free to pick better names for >> these things): >> >> 1. Reintroduce the 'isremat-able' flag, set it to true for all the >> instructions that are *potentially* rematerializable. >> 2. Add a virtual target hook that can override the flag: >> "TII::isReallyR

[llvm-commits] CVS: llvm/lib/Transforms/Scalar/GVNPRE.cpp

Changes in directory llvm/lib/Transforms/Scalar: GVNPRE.cpp updated: 1.53 -> 1.54 --- Log message: Perform fewer set insertions while calculating ANTIC_IN. This reduces the amount of time to optimize 403.gcc from 21.9s to 18.2s. --- Diffs of the changes: (+31 -40) GVNPRE.cpp | 71 +

[llvm-commits] [128742] Fix warning.

Revision: 128742 Author: dpatel Date: 2007-06-22 13:28:02 -0700 (Fri, 22 Jun 2007) Log Message: --- Fix warning. Modified Paths: -- apple-local/branches/llvm/gcc/c-lex.c Modified: apple-local/branches/llvm/gcc/c-lex.c

[llvm-commits] CVS: llvm/lib/Transforms/Scalar/GVNPRE.cpp

Changes in directory llvm/lib/Transforms/Scalar: GVNPRE.cpp updated: 1.54 -> 1.55 --- Log message: Rework topo_sort so eliminate some behavior that scaled terribly. This reduces the time to optimize 403.gcc from 18.2s to 17.5s, and has an even larger effect on larger testcases. --- Diffs o