Changes in directory llvm/include/llvm/CodeGen:
SelectionDAGNodes.h updated: 1.179 -> 1.180
---
Log message:
Add a utility function to test whether a load is unindexed.
---
Diffs of the changes: (+7 -0)
SelectionDAGNodes.h |7 +++
1 files changed, 7 insertions(+)
Index: llvm/inclu
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.274 -> 1.275
---
Log message:
Avoid combining indexed load further.
---
Diffs of the changes: (+14 -8)
DAGCombiner.cpp | 22 ++
1 files changed, 14 insertions(+), 8 deletions(-)
Index: llv
Changes in directory llvm/test/CodeGen/ARM:
2007-03-07-CombinerCrash.ll added (r1.1)
---
Log message:
New test case.
---
Diffs of the changes: (+21 -0)
2007-03-07-CombinerCrash.ll | 21 +
1 files changed, 21 insertions(+)
Index: llvm/test/CodeGen/ARM/2007-03-07-Combi
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.131 -> 1.132
---
Log message:
Cleanup: make SetCounter an instance variable
---
Diffs of the changes: (+26 -28)
DwarfWriter.cpp | 54 ++
1 files changed, 26 insertions(+)
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.18 -> 1.19
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+1 -2)
ARMISelLowering.cpp |3 +--
1 files changed, 1 insertion(+), 2 del
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAGISel.h updated: 1.32 -> 1.33
SelectionDAGNodes.h updated: 1.180 -> 1.181
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+17 -16)
SelectionDAGISel.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.363 -> 1.364
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+2 -12)
X86ISelLowering.cpp | 14 ++
1 files changed, 2 inser
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.483 -> 1.484
SelectionDAGISel.cpp updated: 1.381 -> 1.382
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+31 -31)
LegalizeDAG.cpp
Changes in directory llvm/lib/Target/Sparc:
SparcISelDAGToDAG.cpp updated: 1.121 -> 1.122
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+4 -2)
SparcISelDAGToDAG.cpp |6 --
1 files changed, 4 insertio
Changes in directory llvm/lib/Target/IA64:
IA64ISelLowering.cpp updated: 1.55 -> 1.56
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+4 -2)
IA64ISelLowering.cpp |6 --
1 files changed, 4 insertions(+)
Changes in directory llvm/utils/TableGen:
CallingConvEmitter.cpp updated: 1.5 -> 1.6
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+6 -2)
CallingConvEmitter.cpp |8 ++--
1 files changed, 6 insertions
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.110 -> 1.111
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+3 -2)
TargetLowering.h |5 +++--
1 files changed, 3 insertions(+), 2
Changes in directory llvm/lib/Target/Alpha:
AlphaISelLowering.cpp updated: 1.83 -> 1.84
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+4 -2)
AlphaISelLowering.cpp |6 --
1 files changed, 4 insertions
Changes in directory llvm/lib/Target:
TargetCallingConv.td updated: 1.4 -> 1.5
---
Log message:
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
---
Diffs of the changes: (+1 -1)
TargetCallingConv.td |2 +-
1 files changed, 1 insertion(+), 1 deletion
> Refactoring of formal parameter flags. Enable properly use of
> zext/sext/aext stuff.
Thanks Anton!
-Chris
>
> ---
> Diffs of the changes: (+4 -2)
>
> SparcISelDAGToDAG.cpp |6 --
> 1 files changed, 4 insertions(+), 2 deletions(-)
>
>
> Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.
Changes in directory llvm/lib/Target/X86:
X86InstrMMX.td updated: 1.16 -> 1.17
---
Log message:
Remove useless pattern fragments.
---
Diffs of the changes: (+0 -2)
X86InstrMMX.td |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/
Changes in directory llvm/lib/Target/ARM:
ARMLoadStoreOptimizer.cpp updated: 1.4 -> 1.5
---
Log message:
Only safe to use a call-clobbered or spilled callee-saved register as scratch
register.
---
Diffs of the changes: (+8 -2)
ARMLoadStoreOptimizer.cpp | 10 --
1 files changed, 8
Changes in directory llvm-poolalloc/lib/DSA:
DataStructure.cpp updated: 1.248.2.4.2.2 -> 1.248.2.4.2.3
---
Log message:
Mark globals that are accessable to external functions incomplete.
---
Diffs of the changes: (+3 -1)
DataStructure.cpp |4 +++-
1 files changed, 3 insertions(+), 1 de
Changes in directory llvm-poolalloc/lib/DSA:
TopDownClosure.cpp updated: 1.92.2.1.2.1 -> 1.92.2.1.2.2
---
Log message:
It is possible that MetaPools may be added which have no DSNode.
Skip them properly.
---
Diffs of the changes: (+1 -1)
TopDownClosure.cpp |2 +-
1 files changed, 1 ins
Changes in directory llvm-poolalloc/lib/DSA:
Local.cpp updated: 1.158.2.4.2.2 -> 1.158.2.4.2.3
---
Log message:
Nodes returned from llva_save_stackp() are now collapsed.
Ensure that all globals with a DSNode have a MetaPool.
Disabled debugging and random kernel hacks.
---
Diffs of the changes
Changes in directory llvm/lib/VMCore:
Constants.cpp updated: 1.226 -> 1.227
---
Log message:
Added ContainsRelocations() to check if a constant might only be resolvable at
load time.
---
Diffs of the changes: (+11 -0)
Constants.cpp | 11 +++
1 files changed, 11 insertions(+)
In
Changes in directory llvm/include/llvm:
Constant.h updated: 1.34 -> 1.35
---
Log message:
Added ContainsRelocations() to check if a constant might only be resolvable at
load time.
---
Diffs of the changes: (+4 -0)
Constant.h |4
1 files changed, 4 insertions(+)
Index: llvm/inclu
Changes in directory llvm/include/llvm/Target:
TargetAsmInfo.h updated: 1.27 -> 1.28
---
Log message:
Add ReadOnlySection directive.
---
Diffs of the changes: (+9 -1)
TargetAsmInfo.h | 10 +-
1 files changed, 9 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Target/TargetA
Changes in directory llvm/lib/Target:
TargetAsmInfo.cpp updated: 1.20 -> 1.21
---
Log message:
Add ReadOnlySection directive.
---
Diffs of the changes: (+1 -0)
TargetAsmInfo.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/TargetAsmInfo.cpp
diff -u llvm/lib/Target/Targ
Changes in directory llvm/lib/Target/X86:
X86AsmPrinter.cpp updated: 1.235 -> 1.236
X86TargetAsmInfo.cpp updated: 1.33 -> 1.34
---
Log message:
Put constant data to .const, .const_data, .literal{4|8|16} sections.
---
Diffs of the changes: (+25 -2)
X86AsmPrinter.cpp| 25 +++
Changes in directory llvm/lib/Target/PowerPC:
PPCAsmPrinter.cpp updated: 1.235 -> 1.236
PPCTargetAsmInfo.cpp updated: 1.18 -> 1.19
---
Log message:
For Darwin, put constant data into .const, .const_data, .literal{4|8|16}
sections.
---
Diffs of the changes: (+27 -2)
PPCAsmPrinter.cpp|
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.58 -> 1.59
ARMTargetAsmInfo.cpp updated: 1.12 -> 1.13
---
Log message:
For Darwin, put constant data into .const, .const_data, .literal{4|8|16}
sections.
---
Diffs of the changes: (+26 -2)
ARMAsmPrinter.cpp| 25 +++
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.648 -> 1.649
---
Log message:
For PR1205: http://llvm.org/PR1205 :
Add a new ComputeMaskedBits function that is APIntified. We'll slowly
convert things over to use this version. When its all done, we'll remove
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.649 -> 1.650
---
Log message:
For PR1205: http://llvm.org/PR1205 :
Provide an APIntified version of MaskedValueIsZero. This will (temporarily)
cause a "defined but not used" message from the compiler. It will b
Changes in directory llvm/lib/Target/ARM:
ARMLoadStoreOptimizer.cpp updated: 1.5 -> 1.6
---
Log message:
Bug fix. Not advancing the register scavenger iterator correctly.
---
Diffs of the changes: (+21 -8)
ARMLoadStoreOptimizer.cpp | 29 +
1 files changed, 21 i
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.td updated: 1.14 -> 1.15
---
Log message:
Change register allocation order to Dale's suggestion.
---
Diffs of the changes: (+18 -14)
ARMRegisterInfo.td | 32 ++--
1 files changed, 18 insertions(+), 14 de
> + // Read-only data.
> + bool isIntFPLiteral = Type->isInteger() || Type-
> >isFloatingPoint();
> + if (C->ContainsRelocations() && Subtarget->isTargetDarwin
> () &&
> + TM.getRelocationModel() != Reloc::Static)
Please rearrange this to:
if (isdarwin &&
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.650 -> 1.651
---
Log message:
Fix a bug in APIntified ComputeMaskedBits().
---
Diffs of the changes: (+4 -8)
InstructionCombining.cpp | 12
1 files changed, 4 insertions(+), 8 deletions(-)
Changes in directory llvm/lib/Transforms/Scalar:
ScalarReplAggregates.cpp updated: 1.76 -> 1.77
---
Log message:
Second half of PR1226: http://llvm.org/PR1226 . This is currently still
disabled, until I have a chance to
do the correctness/performance analysis testing.
---
Diffs of the chang
Changes in directory llvm/lib/Transforms/Scalar:
ScalarReplAggregates.cpp updated: 1.77 -> 1.78
---
Log message:
This appears correct, enable it so we can see perf changes on testers
---
Diffs of the changes: (+1 -1)
ScalarReplAggregates.cpp |2 +-
1 files changed, 1 insertion(+), 1 de
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.382 -> 1.383
---
Log message:
make this fail even in non-assert builds.
---
Diffs of the changes: (+4 -2)
SelectionDAGISel.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/l
On Mar 7, 2007, at 9:15 PM, Chris Lattner wrote:
>> + // Read-only data.
>> + bool isIntFPLiteral = Type->isInteger() || Type-
>> >isFloatingPoint();
>> + if (C->ContainsRelocations() && Subtarget-
>> >isTargetDarwin() &&
>> + TM.getRelocationModel() !=
On Mar 7, 2007, at 11:22 PM, Evan Cheng wrote:
>
> On Mar 7, 2007, at 9:15 PM, Chris Lattner wrote:
>
>>> + // Read-only data.
>>> + bool isIntFPLiteral = Type->isInteger() || Type-
>>> >isFloatingPoint();
>>> + if (C->ContainsRelocations() && Subtarget-
>>> >isTarge
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