Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.td updated: 1.14 -> 1.15
---
Log message:
Change register allocation order to Dale's suggestion.
---
Diffs of the changes: (+18 -14)
ARMRegisterInfo.td | 32 ++++++++++++++++++--------------
1 files changed, 18 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.td
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.td:1.14
llvm/lib/Target/ARM/ARMRegisterInfo.td:1.15
--- llvm/lib/Target/ARM/ARMRegisterInfo.td:1.14 Tue Mar 6 20:46:23 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.td Wed Mar 7 20:56:40 2007
@@ -99,30 +99,34 @@
// generate large stack offset. Make it available once we have register
// scavenging. Similarly r3 is reserved in Thumb mode for now.
let MethodBodies = [{
- // FP is R11, R9 is available, R12 is available.
+ // FP is R11, R9 is available.
static const unsigned ARM_GPR_AO_1[] = {
ARM::R3, ARM::R2, ARM::R1, ARM::R0,
+ ARM::R12,ARM::LR,
ARM::R4, ARM::R5, ARM::R6, ARM::R7,
- ARM::R8, ARM::R9, ARM::R10,ARM::R12,
- ARM::LR, ARM::R11 };
- // FP is R11, R9 is not available, R12 is available.
+ ARM::R8, ARM::R9, ARM::R10,
+ ARM::R11 };
+ // FP is R11, R9 is not available.
static const unsigned ARM_GPR_AO_2[] = {
ARM::R3, ARM::R2, ARM::R1, ARM::R0,
+ ARM::R12,ARM::LR,
ARM::R4, ARM::R5, ARM::R6, ARM::R7,
- ARM::R8, ARM::R10,ARM::R12,
- ARM::LR, ARM::R11 };
- // FP is R7, R9 is available, R12 is available.
+ ARM::R8, ARM::R10,
+ ARM::R11 };
+ // FP is R7, R9 is available.
static const unsigned ARM_GPR_AO_3[] = {
ARM::R3, ARM::R2, ARM::R1, ARM::R0,
- ARM::R4, ARM::R5, ARM::R6, ARM::R8,
- ARM::R9, ARM::R10,ARM::R11,ARM::R12,
- ARM::LR, ARM::R7 };
- // FP is R7, R9 is not available, R12 is available.
+ ARM::R12,ARM::LR,
+ ARM::R4, ARM::R5, ARM::R6,
+ ARM::R8, ARM::R9, ARM::R10,ARM::R11,
+ ARM::R7 };
+ // FP is R7, R9 is not available.
static const unsigned ARM_GPR_AO_4[] = {
ARM::R3, ARM::R2, ARM::R1, ARM::R0,
- ARM::R4, ARM::R5, ARM::R6, ARM::R8,
- ARM::R10,ARM::R11,ARM::R12,
- ARM::LR, ARM::R7 };
+ ARM::R12,ARM::LR,
+ ARM::R4, ARM::R5, ARM::R6,
+ ARM::R8, ARM::R10,ARM::R11,
+ ARM::R7 };
// FP is R7, only low registers available.
static const unsigned THUMB_GPR_AO[] = {
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