Changes in directory llvm/test/Regression/Transforms/InstCombine:
xor.ll updated: 1.16 -> 1.17
---
Log message:
new testcases
---
Diffs of the changes: (+15 -0)
xor.ll | 15 +++
1 files changed, 15 insertions(+)
Index: llvm/test/Regression/Transforms/InstCombine/xor.ll
diff
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.456 -> 1.457
---
Log message:
Fold A^(B&A) -> (B&A)^A
Fold (B&A)^A == ~B & A
This implements InstCombine/xor.ll:test2[56]
---
Diffs of the changes: (+46 -7)
InstructionCombining.cpp | 53 ++
Changes in directory llvm/test/Regression/Transforms/InstCombine:
2006-04-01-InfLoop.ll added (r1.1)
---
Log message:
New testcase that caused instcombine to infinitely loop (with my recent
patch), distilled from Applications/JM/ldecod
---
Diffs of the changes: (+441 -0)
2006-04-01-InfLoop
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.457 -> 1.458
---
Log message:
Fix InstCombine/2006-04-01-InfLoop.ll
---
Diffs of the changes: (+2 -1)
InstructionCombining.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrAltivec.td updated: 1.29 -> 1.30
---
Log message:
Implement vnot using VNOR instead of using 'vspltisb v0, -1' and vxor
---
Diffs of the changes: (+4 -0)
PPCInstrAltivec.td |4
1 files changed, 4 insertions(+)
Index: llvm/lib
Changes in directory llvm/lib/Transforms/Utils:
ValueMapper.cpp updated: 1.22 -> 1.23
---
Log message:
add valuemapper support for inline asm
---
Diffs of the changes: (+1 -1)
ValueMapper.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Transforms/Utils/Value
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
2006-04-01-FloatDoubleExtend.ll added (r1.1)
---
Log message:
New testcase that crashes the compiler.
---
Diffs of the changes: (+7 -0)
2006-04-01-FloatDoubleExtend.ll |7 +++
1 files changed, 7 insertions(+)
Index: llvm/
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.214 -> 1.215
---
Log message:
Prefer larger register classes over smaller ones when a register occurs in
multiple register classes. This fixes PowerPC/2006-04-01-FloatDoubleExtend.ll
---
Diffs of the changes:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.124 -> 1.125
---
Log message:
Custom lower all BUILD_VECTOR's so that we can compile vec_splat_u8(8) into
"vspltisb v0, 8" instead of a constant pool load.
---
Diffs of the changes: (+2 -0)
PPCISelLowering.cpp |
Changes in directory llvm/lib/VMCore:
ConstantFolding.cpp updated: 1.84 -> 1.85
---
Log message:
Constant fold casts from things like <4 x int> -> <4 x uint>, likewise int<->fp.
---
Diffs of the changes: (+108 -0)
ConstantFolding.cpp | 108 +
Changes in directory llvm/lib/Target:
README.txt updated: 1.27 -> 1.28
---
Log message:
New note
---
Diffs of the changes: (+6 -0)
README.txt |6 ++
1 files changed, 6 insertions(+)
Index: llvm/lib/Target/README.txt
diff -u llvm/lib/Target/README.txt:1.27 llvm/lib/Target/README.t
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAGNodes.h updated: 1.125 -> 1.126
---
Log message:
simplify this method
---
Diffs of the changes: (+1 -3)
SelectionDAGNodes.h |4 +---
1 files changed, 1 insertion(+), 3 deletions(-)
Index: llvm/include/llvm/CodeGen/Selection
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.293 -> 1.294
---
Log message:
Add some missing node names
---
Diffs of the changes: (+9 -0)
SelectionDAG.cpp |9 +
1 files changed, 9 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDA
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.294 -> 1.295
---
Log message:
These entries already exist
---
Diffs of the changes: (+0 -4)
SelectionDAG.cpp |4
1 files changed, 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.136 -> 1.137
---
Log message:
Implement constant folding of bit_convert of arbitrary constant vbuild_vector
nodes.
---
Diffs of the changes: (+139 -2)
DAGCombiner.cpp | 141
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.348 -> 1.349
SelectionDAGISel.cpp updated: 1.215 -> 1.216
---
Log message:
Add a new -view-legalize-dags command line option
---
Diffs of the changes: (+13 -3)
LegalizeDAG.cpp | 13 -
Selectio
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.137 -> 1.138
---
Log message:
Constant fold all of the vector binops. This allows us to compile this:
"vector unsigned char mergeLowHigh = (vector unsigned char)
( 8, 9, 10, 11, 16, 17, 18, 19, 12, 13, 14, 15, 20,
Changes in directory llvm/utils/TableGen:
IntrinsicEmitter.cpp updated: 1.19 -> 1.20
---
Log message:
Adjust the Intrinsics.gen interface a little bit
---
Diffs of the changes: (+2 -2)
IntrinsicEmitter.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/utils/Ta
Changes in directory llvm/lib/Transforms/Utils:
Local.cpp updated: 1.53 -> 1.54
---
Log message:
Adjust to change in Intrinsics.gen interface.
---
Diffs of the changes: (+1 -0)
Local.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Transforms/Utils/Local.cpp
diff -u llvm/li
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.216 -> 1.217
---
Log message:
Intrinsics that just load from memory can be treated like loads: they don't
have to serialize against each other. This allows us to schedule lvx's
across each other, for example.
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.349 -> 1.350
---
Log message:
Implement the Expand action for binary vector operations to break the binop
into elements and operate on each piece. This allows generic vector integer
multiplies to work on PPC, though
Changes in directory llvm/lib/Target/PowerPC:
README_ALTIVEC.txt updated: 1.9 -> 1.10
---
Log message:
add a note
---
Diffs of the changes: (+11 -0)
README_ALTIVEC.txt | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.350 -> 1.351
---
Log message:
Implement promotion for EXTRACT_VECTOR_ELT, allowing v16i8 multiplies to work
with PowerPC.
---
Diffs of the changes: (+27 -16)
LegalizeDAG.cpp | 43 +++-
Changes in directory llvm/win32/x86:
x86.vcproj updated: 1.22 -> 1.23
---
Log message:
Fix tablegen related dependencies in Visual Studio.
---
Diffs of the changes: (+19 -2)
x86.vcproj | 21 +++--
1 files changed, 19 insertions(+), 2 deletions(-)
Index: llvm/win32/x86/x8
Changes in directory llvm/win32/VMCore:
VMCore.vcproj updated: 1.19 -> 1.20
---
Log message:
Fix tablegen related dependencies in Visual Studio.
---
Diffs of the changes: (+8 -8)
VMCore.vcproj | 16
1 files changed, 8 insertions(+), 8 deletions(-)
Index: llvm/win32/VMCo
Changes in directory llvm/lib/Target/PowerPC:
README_ALTIVEC.txt updated: 1.10 -> 1.11
---
Log message:
Remove done item
---
Diffs of the changes: (+0 -5)
README_ALTIVEC.txt |5 -
1 files changed, 5 deletions(-)
Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/T
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.458 -> 1.459
---
Log message:
Turn altivec lvx/stvx intrinsics into loads and stores. This allows the
elimination of one load from this:
int AreSecondAndThirdElementsBothNegative( vector float *in ) {
#define
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.459 -> 1.460
---
Log message:
Allow transforming this:
%tmp = cast <4 x uint>* %testData to <4 x int>* ; <<4 x int>*>
[#uses=1]
%tmp = load <4 x int>* %tmp ; <<4 x int>> [#
Changes in directory llvm/lib/VMCore:
Type.cpp updated: 1.137 -> 1.138
---
Log message:
vector casts never reinterpret bits
---
Diffs of the changes: (+5 -0)
Type.cpp |5 +
1 files changed, 5 insertions(+)
Index: llvm/lib/VMCore/Type.cpp
diff -u llvm/lib/VMCore/Type.cpp:1.137 llv
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.460 -> 1.461
---
Log message:
vector casts of casts are eliminable. Transform this:
%tmp = cast <4 x uint> %tmp to <4 x int>; <<4 x int>>
[#uses=1]
%tmp = cast <4 x int> %tmp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.138 -> 1.139
---
Log message:
Add a little dag combine to compile this:
int %AreSecondAndThirdElementsBothNegative(<4 x float>* %in) {
entry:
%tmp1 = load <4 x float>* %in ; <<4 x float>> [#uses=1]
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.51 -> 1.52
---
Log message:
Allow targets to compute masked bits for intrinsics.
---
Diffs of the changes: (+9 -4)
TargetLowering.cpp | 13 +
1 files changed, 9 insertions(+), 4 deletions(-)
Index: llvm/lib
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.52 -> 1.53
---
Log message:
relax assertion
---
Diffs of the changes: (+4 -1)
TargetLowering.cpp |5 -
1 files changed, 4 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Ta
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.125 -> 1.126
PPCISelLowering.h updated: 1.37 -> 1.38
---
Log message:
Inform the dag combiner that the predicate compares only return a low bit.
---
Diffs of the changes: (+39 -1)
PPCISelLowering.cpp | 35 ++
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.83 -> 1.84
---
Log message:
add a note
---
Diffs of the changes: (+9 -0)
README.txt |9 +
1 files changed, 9 insertions(+)
Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:
35 matches
Mail list logo
