Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.33 -> 1.34
---
Log message:
We only need to specify the most-implied feature for an architecture.
---
Diffs of the changes: (+21 -33)
X86.td | 54 +-
1 files changed, 21 insert
Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.32 -> 1.33
---
Log message:
3DNowA implies 3DNow. 64-bit implies SSE1, SSE2, and I assume MMX.
---
Diffs of the changes: (+5 -3)
X86.td |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86
> One question: are there any cpus that support "3dnowa" but not
> "3dnow"?
I definitely think, that no.
--
With best regards, Anton Korobeynikov.
Faculty of Mathematics & Mechanics, Saint Petersburg State University.
___
llvm-commits mailing list
>
>> Does 64-bit imply sse2 or sse3?
>>
> Again, I didn't know. :-) If they do, I can fix it.
X86Subtarget.cpp says that SSE2 is always available if the cpu is 64-
bit. Can the logic in that file be simplified with your changes?
(is it ever possible to have SSE2 bit set but not SSE1 now?)
-C
On May 5, 2007, at 1:43 PM, Bill Wendling wrote:
> On May 5, 2007, at 1:32 PM, Anton Korobeynikov wrote:
>
>> Hello, Bill.
>>
>>> I didn't know if they should or not. Should they? :-)
>> I can check anything 3dnow-related in hardware. Do you have some
>> testcase?
>>
> Not for 3dnow...In truth, o
On May 5, 2007, at 1:32 PM, Anton Korobeynikov wrote:
> Hello, Bill.
>
>> I didn't know if they should or not. Should they? :-)
> I can check anything 3dnow-related in hardware. Do you have some
> testcase?
>
Not for 3dnow...In truth, our support for 3dnow is lacking. We don't
have a lot of the
Hello, Bill.
> I didn't know if they should or not. Should they? :-)
I can check anything 3dnow-related in hardware. Do you have some
testcase?
--
With best regards, Anton Korobeynikov.
Faculty of Mathematics & Mechanics, Saint Petersburg State University.
On May 5, 2007, at 10:56 AM, Chris Lattner wrote:
> On May 4, 2007, at 1:39 PM, Bill Wendling wrote:
>> Add an "implies" field to features. This indicates that, if the
>> current
>> feature is set, then the features in the implied list should be set
>> also.
>> The opposite is also enforced: if a
On May 4, 2007, at 1:39 PM, Bill Wendling wrote:
> Add an "implies" field to features. This indicates that, if the
> current
> feature is set, then the features in the implied list should be set
> also.
> The opposite is also enforced: if a feature in the implied list
> isn't set,
> then the
Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.31 -> 1.32
---
Log message:
Add an "implies" field to features. This indicates that, if the current
feature is set, then the features in the implied list should be set also.
The opposite is also enforced: if a feature in the implied li
Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.30 -> 1.31
X86InstrInfo.td updated: 1.305 -> 1.306
---
Log message:
Add SSSE3 as a feature of Core2. Add MMX registers to the list of registers
clobbered by a call.
---
Diffs of the changes: (+2 -1)
X86.td |2 +-
X86I
Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.29 -> 1.30
X86CodeEmitter.cpp updated: 1.131 -> 1.132
X86InstrInfo.h updated: 1.62 -> 1.63
X86InstrInfo.td updated: 1.300 -> 1.301
X86InstrSSE.td updated: 1.179 -> 1.180
X86Subtarget.cpp updated: 1.53 -> 1.54
X86Subtarget.h updated: 1.2
Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.24 -> 1.25
X86InstrInfo.h updated: 1.50 -> 1.51
---
Log message:
ImmMask should be 3 for a two-bit field; Compact X86II
---
Diffs of the changes: (+3 -4)
X86.td |2 +-
X86InstrInfo.h |5 ++---
2 files changed, 3 ins
Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.23 -> 1.24
X86RegisterInfo.cpp updated: 1.153 -> 1.154
X86RegisterInfo.h updated: 1.38 -> 1.39
---
Log message:
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
---
Diffs of the changes: (+28 -7)
X86.td
Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.22 -> 1.23
---
Log message:
Remove PointerType from class Target
---
Diffs of the changes: (+0 -3)
X86.td |3 ---
1 files changed, 3 deletions(-)
Index: llvm/lib/Target/X86/X86.td
diff -u llvm/lib/Target/X86/X86.td:1.22 llvm/
Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.21 -> 1.22
X86CodeEmitter.cpp updated: 1.86 -> 1.87
X86InstrInfo.h updated: 1.48 -> 1.49
X86InstrInfo.td updated: 1.226 -> 1.227
---
Log message:
- Use xor to clear integer registers (set R, 0).
- Added a new format for instructions wh
Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.20 -> 1.21
X86ISelLowering.cpp updated: 1.70 -> 1.71
X86ISelLowering.h updated: 1.22 -> 1.23
X86InstrInfo.td updated: 1.224 -> 1.225
X86Subtarget.h updated: 1.9 -> 1.10
---
Log message:
* Fix 80-column violations
* Rename hasSSE -> has
Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.19 -> 1.20
---
Log message:
Fix typo.
---
Diffs of the changes: (+1 -1)
X86.td |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86.td
diff -u llvm/lib/Target/X86/X86.td:1.19 llvm/lib/Target/X8
Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.17 -> 1.18
X86InstrInfo.td updated: 1.218 -> 1.219
---
Log message:
PHI and INLINEASM are now built-in instructions provided by Target.td
---
Diffs of the changes: (+0 -4)
X86.td |1 -
X86InstrInfo.td |3 ---
2 fi
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