Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.29 -> 1.30
X86CodeEmitter.cpp updated: 1.131 -> 1.132
X86InstrInfo.h updated: 1.62 -> 1.63
X86InstrInfo.td updated: 1.300 -> 1.301
X86InstrSSE.td updated: 1.179 -> 1.180
X86Subtarget.cpp updated: 1.53 -> 1.54
X86Subtarget.h updated: 1.28 -> 1.29
---
Log message:
Add support for our first SSSE3 instruction "pmulhrsw".
---
Diffs of the changes: (+54 -10)
X86.td | 2 ++
X86CodeEmitter.cpp | 8 ++++++++
X86InstrInfo.h | 5 ++++-
X86InstrInfo.td | 3 +++
X86InstrSSE.td | 40 +++++++++++++++++++++++++++++++++-------
X86Subtarget.cpp | 1 +
X86Subtarget.h | 5 +++--
7 files changed, 54 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/X86/X86.td
diff -u llvm/lib/Target/X86/X86.td:1.29 llvm/lib/Target/X86/X86.td:1.30
--- llvm/lib/Target/X86/X86.td:1.29 Mon Feb 26 12:17:14 2007
+++ llvm/lib/Target/X86/X86.td Tue Apr 10 17:10:25 2007
@@ -30,6 +30,8 @@
"Enable SSE2 instructions">;
def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
"Enable SSE3 instructions">;
+def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
+ "Enable SSSE3 instructions">;
def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
"Enable 3DNow! instructions">;
def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel",
"ThreeDNowA",
Index: llvm/lib/Target/X86/X86CodeEmitter.cpp
diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.131
llvm/lib/Target/X86/X86CodeEmitter.cpp:1.132
--- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.131 Wed Mar 14 15:20:19 2007
+++ llvm/lib/Target/X86/X86CodeEmitter.cpp Tue Apr 10 17:10:25 2007
@@ -584,6 +584,14 @@
case X86II::TB:
Need0FPrefix = true; // Two-byte opcode prefix
break;
+ case X86II::T8:
+ MCE.emitByte(0x0F);
+ MCE.emitByte(0x38);
+ break;
+ case X86II::TA:
+ MCE.emitByte(0x0F);
+ MCE.emitByte(0x3A);
+ break;
case X86II::REP: break; // already handled.
case X86II::XS: // F3 0F
MCE.emitByte(0xF3);
Index: llvm/lib/Target/X86/X86InstrInfo.h
diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.62
llvm/lib/Target/X86/X86InstrInfo.h:1.63
--- llvm/lib/Target/X86/X86InstrInfo.h:1.62 Fri Jan 26 08:34:52 2007
+++ llvm/lib/Target/X86/X86InstrInfo.h Tue Apr 10 17:10:25 2007
@@ -154,7 +154,10 @@
// XS, XD - These prefix codes are for single and double precision scalar
// floating point operations performed in the SSE registers.
- XD = 11 << Op0Shift, XS = 12 << Op0Shift,
+ XD = 11 << Op0Shift, XS = 12 << Op0Shift,
+
+ // T8, TA - Prefix after the 0x0F prefix.
+ T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
//===------------------------------------------------------------------===//
// REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.300
llvm/lib/Target/X86/X86InstrInfo.td:1.301
--- llvm/lib/Target/X86/X86InstrInfo.td:1.300 Tue Mar 20 19:16:56 2007
+++ llvm/lib/Target/X86/X86InstrInfo.td Tue Apr 10 17:10:25 2007
@@ -167,6 +167,7 @@
def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
+def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
def FPStack : Predicate<"!Subtarget->hasSSE2()">;
def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
def In64BitMode : Predicate<"Subtarget->is64Bit()">;
@@ -248,6 +249,8 @@
class DF { bits<4> Prefix = 10; }
class XD { bits<4> Prefix = 11; }
class XS { bits<4> Prefix = 12; }
+class T8 { bits<4> Prefix = 13; }
+class TA { bits<4> Prefix = 14; }
//===----------------------------------------------------------------------===//
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.179
llvm/lib/Target/X86/X86InstrSSE.td:1.180
--- llvm/lib/Target/X86/X86InstrSSE.td:1.179 Tue Mar 20 19:16:56 2007
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 10 17:10:25 2007
@@ -183,15 +183,17 @@
//===----------------------------------------------------------------------===//
// Instruction templates
-// SSI - SSE1 instructions with XS prefix.
-// SDI - SSE2 instructions with XD prefix.
-// PSI - SSE1 instructions with TB prefix.
-// PDI - SSE2 instructions with TB and OpSize prefixes.
+// SSI - SSE1 instructions with XS prefix.
+// SDI - SSE2 instructions with XD prefix.
+// PSI - SSE1 instructions with TB prefix.
+// PDI - SSE2 instructions with TB and OpSize prefixes.
// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
-// S3I - SSE3 instructions with TB and OpSize prefixes.
-// S3SI - SSE3 instructions with XS prefix.
-// S3DI - SSE3 instructions with XD prefix.
+// S3I - SSE3 instructions with TB and OpSize prefixes.
+// S3SI - SSE3 instructions with XS prefix.
+// S3DI - SSE3 instructions with XD prefix.
+// SS38I - SSSE3 instructions with T8 and OpSize prefixes.
+// SS3AI - SSSE3 instructions with TA and OpSize prefixes.
class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
: I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
@@ -212,6 +214,11 @@
class S3I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
: I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
+class SS38I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
+ : I<o, F, ops, asm, pattern>, T8, OpSize, Requires<[HasSSSE3]>;
+class SS3AI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
+ : I<o, F, ops, asm, pattern>, TA, OpSize, Requires<[HasSSSE3]>;
+
//===----------------------------------------------------------------------===//
// Helpers for defining instructions that directly correspond to intrinsics.
@@ -1311,6 +1318,22 @@
}
}
+/// SS3I_binop_rm_int - Simple SSSE3 binary operatr whose type is v2i64.
+let isTwoAddress = 1 in {
+ multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
+ bit Commutable = 0> {
+ def rr : SS38I<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
+ [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
+ let isCommutable = Commutable;
+ }
+ def rm : SS38I<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
+ [(set VR128:$dst,
+ (IntId VR128:$src1,
+ (bitconvert (loadv2i64 addr:$src2))))]>;
+ }
+}
// 128-bit Integer Arithmetic
@@ -1340,6 +1363,9 @@
defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
+defm PMULHRSW128 : SS3I_binop_rm_int<0x0B, "pmulhrsw",
+ int_x86_ssse3_pmulhrsw_128, 1>;
+
defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
Index: llvm/lib/Target/X86/X86Subtarget.cpp
diff -u llvm/lib/Target/X86/X86Subtarget.cpp:1.53
llvm/lib/Target/X86/X86Subtarget.cpp:1.54
--- llvm/lib/Target/X86/X86Subtarget.cpp:1.53 Fri Mar 23 18:46:48 2007
+++ llvm/lib/Target/X86/X86Subtarget.cpp Tue Apr 10 17:10:25 2007
@@ -113,6 +113,7 @@
if ((EDX >> 25) & 0x1) X86SSELevel = SSE1;
if ((EDX >> 26) & 0x1) X86SSELevel = SSE2;
if (ECX & 0x1) X86SSELevel = SSE3;
+ if ((ECX >> 9) & 0x1) X86SSELevel = SSSE3;
if (memcmp(text.c, "GenuineIntel", 12) == 0) {
X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
Index: llvm/lib/Target/X86/X86Subtarget.h
diff -u llvm/lib/Target/X86/X86Subtarget.h:1.28
llvm/lib/Target/X86/X86Subtarget.h:1.29
--- llvm/lib/Target/X86/X86Subtarget.h:1.28 Tue Jan 16 11:51:40 2007
+++ llvm/lib/Target/X86/X86Subtarget.h Tue Apr 10 17:10:25 2007
@@ -38,7 +38,7 @@
};
protected:
enum X86SSEEnum {
- NoMMXSSE, MMX, SSE1, SSE2, SSE3
+ NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3
};
enum X863DNowEnum {
@@ -51,7 +51,7 @@
/// PICStyle - Which PIC style to use
PICStyle::Style PICStyle;
- /// X86SSELevel - MMX, SSE1, SSE2, SSE3, or none supported.
+ /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, or none supported.
X86SSEEnum X86SSELevel;
/// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
@@ -110,6 +110,7 @@
bool hasSSE1() const { return X86SSELevel >= SSE1; }
bool hasSSE2() const { return X86SSELevel >= SSE2; }
bool hasSSE3() const { return X86SSELevel >= SSE3; }
+ bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
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