Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.81 -> 1.82
PPCInstrInfo.td updated: 1.255 -> 1.256
---
Log message:
dform 8/9 are identical to dform 1
---
Diffs of the changes: (+6 -15)
PPCInstrFormats.td |9 -
PPCInstrInfo.td| 12 ++--
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.74 -> 1.75
PPCInstrInfo.td updated: 1.229 -> 1.230
---
Log message:
remove unused flag
---
Diffs of the changes: (+0 -2)
PPCInstrFormats.td |1 -
PPCInstrInfo.td|1 -
2 files changed, 2 deletions(-)
I
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.73 -> 1.74
PPCInstrInfo.td updated: 1.220 -> 1.221
---
Log message:
Add PowerPC intrinsics to support dcbz[l]
---
Diffs of the changes: (+25 -0)
PPCInstrFormats.td | 17 +
PPCInstrInfo.td|
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.66 -> 1.67
PPCInstrInfo.td updated: 1.201 -> 1.202
---
Log message:
Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
---
Diffs of the changes: (+8 -9)
PPCInstrFormats.td |2 +-
PPCInstrInfo.
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.63 -> 1.64
PPCInstrInfo.td updated: 1.174 -> 1.175
---
Log message:
PHI and INLINEASM are now built-in instructions provided by Target.td
---
Diffs of the changes: (+1 -5)
PPCInstrFormats.td |3 +--
PPCInstrInf
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.61 -> 1.62
PPCInstrInfo.td updated: 1.156 -> 1.157
---
Log message:
Add support for fmul node of type v4f32.
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.60 -> 1.61
PPCInstrInfo.td updated: 1.152 -> 1.153
---
Log message:
Add support patterns to many load and store instructions which will
hopefully use patterns in the near future.
---
Diffs of the changes: (+133 -76)
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.59 -> 1.60
PPCInstrInfo.td updated: 1.147 -> 1.148
---
Log message:
Define BR in the .td file now that Evan made tblgen smarter.
---
Diffs of the changes: (+10 -5)
PPCInstrFormats.td |3 ++-
PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.58 -> 1.59
PPCInstrInfo.td updated: 1.146 -> 1.147
---
Log message:
Represent the encoding of the SPR instructions as they actually are, so
that we can use the correct SPR numbers in the InstrInfo.td file. This is
nece
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.57 -> 1.58
PPCInstrInfo.td updated: 1.145 -> 1.146
---
Log message:
Add the remainder of the AltiVec 4 x float instructions. Further
enhancements will be necessary to teach the code generator that since
there is no fmu
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.55 -> 1.56
PPCInstrInfo.td updated: 1.143 -> 1.144
PPCRegisterInfo.td updated: 1.20 -> 1.21
---
Log message:
Some first bits of AltiVec stuff: Instruction Formats, Encodings, and
Registers. Apologies to Jim if the sche
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.54 -> 1.55
PPCInstrInfo.td updated: 1.135 -> 1.136
---
Log message:
Allow pseudos to have patterns, no functionality change
---
Diffs of the changes: (+13 -13)
PPCInstrFormats.td |4 ++--
PPCInstrInfo.td|
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