Author: rafael
Date: Mon Nov 5 17:12:20 2007
New Revision: 43742
URL: http://llvm.org/viewvc/llvm-project?rev=43742&view=rev
Log:
Move the LowerMEMCPY and LowerMEMCPYCall to a common place.
Thanks for the suggestions Bill :-)
Modified:
llvm/trunk/include/llvm/Target/TargetLowering.h
ll
> You probably can get away with forward declaring the TargetSubtarget
> class instead of #including here.
Good catch. Will try that.
> If you're going to do this, why not just get rid of Subtarget
> altogether and just use BaseSubtarget? It can be set to 0 for targets
> that don't use it. Then a
The attached patch passes a "make check". I haven't committed yet
because I am going on vacations and will be a bit slow to respond. I
will still have Internet access and can commit if there is positive
feedback.
One ugly hack in the CL in to make "Subtarget" and "BaseSubtarget"
independent fields
Author: rafael
Date: Wed Oct 31 09:39:58 2007
New Revision: 43554
URL: http://llvm.org/viewvc/llvm-project?rev=43554&view=rev
Log:
Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into
getMaxInlineSizeThreshold
and by restructuring the X86 version.
New I just have to move this
Author: rafael
Date: Wed Oct 31 06:52:06 2007
New Revision: 43552
URL: http://llvm.org/viewvc/llvm-project?rev=43552&view=rev
Log:
Make ARM an X86 memcpy expansion more similar to each other.
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.
This should not change gen
> Hey Rafael,
>
> I just asked Bill to look into merging these memcpy lowering
> implementations. Have you already started on this, or should Bill
> look into it?
>
I have started, but I could use some help :-)
The items I have in mind:
1) make the arm inline version work on thumb
2) add a Subta
On 22/10/2007, Evan Cheng <[EMAIL PROTECTED]> wrote:
> Hi Rafael,
>
> There a couple of problems with this patch.
>
> 1. This breaks a number of tests for me:
> llc-beta /MultiSource/Applications/JM/ldecod/ldecod
> llc /MultiSource/Applications/JM/ldecod/ldecod
> llc /External/SPEC/CINT2000/254.gap
Author: rafael
Date: Fri Oct 19 09:35:17 2007
New Revision: 43176
URL: http://llvm.org/viewvc/llvm-project?rev=43176&view=rev
Log:
split LowerMEMCPY into LowerMEMCPYCall and LowerMEMCPYInline in the ARM backend.
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target
Author: rafael
Date: Fri Oct 19 06:29:21 2007
New Revision: 43173
URL: http://llvm.org/viewvc/llvm-project?rev=43173&view=rev
Log:
Test byval with a 8 bit aligned struct
Added:
llvm/trunk/test/CodeGen/X86/byval5.ll
Added: llvm/trunk/test/CodeGen/X86/byval5.ll
URL:
http://llvm.org/viewvc/llv
Author: rafael
Date: Fri Oct 19 05:41:11 2007
New Revision: 43172
URL: http://llvm.org/viewvc/llvm-project?rev=43172&view=rev
Log:
Add support for byval function whose argument is not 32 bit aligned.
To do this it is necessary to add a "always inline" argument to the
memcpy node. For completeness
> I think this behavior makes sense. If the size is variable, it could
> be arbitrarily large. We should assume that memcpy (the library
> implementation) is tuned as best as possible for handling the unknown
> size case.
Yes, we know that libc memcpy is better for big values and that inline
is
Author: rafael
Date: Fri Sep 28 07:53:01 2007
New Revision: 42433
URL: http://llvm.org/viewvc/llvm-project?rev=42433&view=rev
Log:
Refactor the memcpy lowering for the x86 target.
The only generated code difference is that now we call memcpy when
the size of the array is unknown. This matches GCC
Author: rafael
Date: Fri Sep 21 10:50:22 2007
New Revision: 42192
URL: http://llvm.org/viewvc/llvm-project?rev=42192&view=rev
Log:
Don't add a default STACK_ALIGN (use the generic ABI alignment)
Implement calls to functions with byval arguments on X86
Modified:
llvm/trunk/lib/Target/TargetDat
Author: rafael
Date: Fri Sep 21 09:55:38 2007
New Revision: 42189
URL: http://llvm.org/viewvc/llvm-project?rev=42189&view=rev
Log:
small cleanup: use LowerMemArgument in LowerFastCCArguments also
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86I
Author: rafael
Date: Fri Sep 14 10:48:13 2007
New Revision: 41953
URL: http://llvm.org/viewvc/llvm-project?rev=41953&view=rev
Log:
Add support for functions with byval arguments on x86
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
Author: rafael
Date: Fri Sep 7 09:52:14 2007
New Revision: 41768
URL: http://llvm.org/viewvc/llvm-project?rev=41768&view=rev
Log:
Add support for having different alignment for objects on call frames.
The x86-64 ABI states that objects passed on the stack have
8 byte alignment. Implement that.
A
On 04/09/07, Evan Cheng <[EMAIL PROTECTED]> wrote:
> Hi Rafael,
>
> Thanks for catching this!
>
> As far as I know Darwin follows the ABI exactly. I'll fix that. BTW,
> is it possible for you to add a test case?
In a sense, I have one:
test/CodeGen/X86/byval2.ll
If
(Align & 3) != 0
the MEMCPY no
> Where do you need the representation? Loads and stores in the LLVM IR and
> the target-independent load and store nodes in the SelectionDAG IR have an
> alignment attribute; are either of those sufficient?
I need the alignment while expanding a call to a function. In this
case I have the DAG nod
To handle calls to functions with byval arguments, the code generator
must create copies of those arguments. To do that efficiently, it
needs to know the alignment.
On x86-64, all stack arguments are 8 byte aligned. I am trying to find
out how to represent that on LLVM.
The GCC way would be to ad
Author: rafael
Date: Fri Aug 31 10:06:30 2007
New Revision: 41643
URL: http://llvm.org/viewvc/llvm-project?rev=41643&view=rev
Log:
Initial support for calling functions with byval arguments on x86-64
Added:
llvm/trunk/test/CodeGen/X86/byval2.ll
Modified:
llvm/trunk/lib/Target/X86/X86ISel
Author: rafael
Date: Fri Aug 31 07:23:58 2007
New Revision: 41642
URL: http://llvm.org/viewvc/llvm-project?rev=41642&view=rev
Log:
Align i64 and f64 at 8 byte on x86-64.
This is mandated table 3.1 at
http://www.x86-64.org/documentation/abi.pdf
Modified:
llvm/trunk/lib/Target/X86/X86Subtarget
> I'm not aware of any cases where memmove vs. memcpy matters before
> codegen currently. If it were done at the LLVM IR level, would it be
> too trivial to be in a pass by itself, or would you want to add it,
> along with an addRequired, to some existing pass?
Doing it at the LLVM IL would also b
Author: rafael
Date: Mon Aug 27 12:48:26 2007
New Revision: 41502
URL: http://llvm.org/viewvc/llvm-project?rev=41502&view=rev
Log:
Add a comment about using libc memset/memcpy or generating inline code.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X
Author: rafael
Date: Mon Aug 27 05:18:20 2007
New Revision: 41479
URL: http://llvm.org/viewvc/llvm-project?rev=41479&view=rev
Log:
call libc memcpy/memset if array size is bigger then threshold.
Coping 100MB array (after a warmup) shows that glibc 2.6.1 implementation on
x86-64 (core 2) is 30% fa
According to table 3.1 of http://www.x86-64.org/documentation/abi.pdf,
the i64 and f64 types should have 8 byte alignment.
The attached patch changes this for targets that are not darwin.
OK to commit?
Cheers,
--
Rafael Avila de Espindola
Google Ireland Ltd.
Gordon House
Barrow Street
Dublin 4
Currently we expand a memcpy/memset node to a call to the libc implementation if
if ((Align & 3) != 0 ||
(I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
Shouldn't this be a ">". The libc memcpy/memset are very fast for big arrays.
If I compile
--
Author: rafael
Date: Mon Aug 20 10:18:24 2007
New Revision: 41179
URL: http://llvm.org/viewvc/llvm-project?rev=41179&view=rev
Log:
Partial implementation of calling functions with byval arguments:
*) The needed information is propagated to the DAG
*) The X86-64 backend detects it and aborts
Mod
Author: rafael
Date: Thu Aug 16 08:09:02 2007
New Revision: 41123
URL: http://llvm.org/viewvc/llvm-project?rev=41123&view=rev
Log:
add byval test
Added:
llvm/trunk/test/CodeGen/X86/byval.ll
Added: llvm/trunk/test/CodeGen/X86/byval.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/
> define void @_Z1g1S(%struct.S* noalias %s) {
> entry:%tmp131415 = getelementptr %struct.S* %s, i32 0, i32 0
> ; [#uses=1]%tmp16 = load i32 (...)*** %tmp131415,
> align 4 ; [#uses=1]
> %tmp26277 = load i32 (...)** %tmp16 ;
> [#uses=1]
>
> I think this patch is looking very good. As it can only affect
> things marked 'byval', please feel free to commit what you have.
done.
> As a next step, it would be good to implement passing of a struct
> into a call by-val.
I Agree :-)
> -Chris
Cheers,
--
Rafael Avila de Espindola
Google
Author: rafael
Date: Fri Aug 10 09:44:42 2007
New Revision: 40986
URL: http://llvm.org/viewvc/llvm-project?rev=40986&view=rev
Log:
propagate struct size and alignment of byval arguments to the DAG
Modified:
llvm/trunk/include/llvm/CodeGen/CallingConvLower.h
llvm/trunk/include/llvm/CodeGen
The attached patch implements code generation of byval arguments on
the callee. For now only the case were the struct is in the stack is
handle correctly.
With the patch, the function
---
%struct.s = type { i64, i64, i64 }
define i64 @f(%struct.s* b
> The problem is that not all "byval" structs get passed in registers.
> On x86-32 for example, they all get passed on the stack, just a very
> "specific" part of the stack.
I think that this can be represented. For example, we would compile the function
int f(int a) { return a; }
on x86-32 into
> could you please explain this some more. Are you saying that the copy
> has to be placed very specifically in the stack frame, or does it not
> matter very much where it is? Since an offset to it is passed to the
> callee I guessed that it doesn't matter much were it is exactly.
The offset is
Author: rafael
Date: Tue Jul 17 08:34:23 2007
New Revision: 39971
URL: http://llvm.org/viewvc/llvm-project?rev=39971&view=rev
Log:
detect invalid combination of sret and byval
Modified:
llvm/trunk/lib/VMCore/Verifier.cpp
Modified: llvm/trunk/lib/VMCore/Verifier.cpp
URL:
http://llvm.org/view
> I see now that I was mislead by the assertion message which should probably
> be "Attribute ByVal should not apply to function return values!". I thought
> you were not allowing this attribute on any parameter of a function. By the
> way, do you catch the case in which a parameter is marked bot
> I actually don't like this approach, because this depends a lot of
> decisions made in the code generator: the copy may be in registers
> (hopefully) or on the stack, or with some magic funny thing. Adding
> an extra copy at the llvm level would require the codegen to remove
> it, which is reall
On 11/07/07, Duncan Sands <[EMAIL PROTECTED]> wrote:
> Hi Rafael,
>
> > +Assert(!Attrs->paramHasAttr(0, ParamAttr::ByVal),
> > + "Attribute ByVal should not apply to functions!");
>
> why not?
What does it means to a function to have such an attribute?
> > +"Attribut
Author: rafael
Date: Tue Jul 10 14:28:12 2007
New Revision: 38506
URL: http://llvm.org/viewvc/llvm-project?rev=38506&view=rev
Log:
check for correct usage of the byval attribute
Added:
llvm/trunk/test/Verifier/byval-1.ll
llvm/trunk/test/Verifier/byval-2.ll
llvm/trunk/test/Verifier/byv
> exactly, and thus alias analysis, inlining etc are all being mislead,
> because they will think you are modifying the original. This is very
> dual to StructReturn by the way: if you assign to the sret parameter
> before calling the routine, and try to read those values inside the
> routine, you
Sorry for the delay...
> first let me point out that much of what you say also applies to
> StructReturn, which probably can also be used for returning arrays,
> ints etc. And like StructReturn this is all about the ABI: my
> understanding is that on some platforms the ABI allows for passing
> (s
> The patch looks good. Some questions/comments:
>
> +++ include/llvm/CodeGen/SelectionDAGNodes.h(working copy)
>
> +SturtByVal= 1<<4, ///< Struct passed by value
>
> This looks like a typo "sturt"
Changed to "ByVal" based on Duncan's comment.
> +++ utils/TableGen/CallingConvEmit
Author: rafael
Date: Fri Jul 6 05:57:03 2007
New Revision: 37940
URL: http://llvm.org/viewvc/llvm-project?rev=37940&view=rev
Log:
Add the byval attribute
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/trunk/include/llvm/ParameterAttributes.h
llvm/trunk/lib/AsmPars
The first email bounced, so lets try again.
This patch implements the first part of the proposed solution to bug
1521. It adds the byval attribute and propagates it to DAG level.
The patch also changes the matching code for CCIfType, so that no
backend matches a byval argument. Instead, a backen
The attached patch adds the "byval" attribute. This is the first step
to fix bug 1521.
--
Rafael Avila de Espindola
Google Ireland Ltd.
Gordon House
Barrow Street
Dublin 4
Ireland
Registered in Dublin, Ireland
Registration Number: 368047
Index: include/llvm/ParameterAttributes.h
===
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.95 -> 1.96
ARMInstrInfo.td updated: 1.82 -> 1.83
---
Log message:
implement missing compares
patch by Lauro
bug fixed by me
---
Diffs of the changes: (+67 -38)
ARMISelDAGToDAG.cpp | 103 ++
Changes in directory llvm/test/Regression/CodeGen/ARM:
fpcmp_ueq.ll added (r1.1)
---
Log message:
implement missing compares
patch by Lauro
bug fixed by me
---
Diffs of the changes: (+11 -0)
fpcmp_ueq.ll | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/test/Regression/Co
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.93 -> 1.94
---
Log message:
fix comment
---
Diffs of the changes: (+1 -1)
ARMISelDAGToDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.80 -> 1.81
---
Log message:
remove duplicated line
bug noticed by Lauro
---
Diffs of the changes: (+0 -1)
ARMInstrInfo.td |1 -
1 files changed, 1 deletion(-)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.29 -> 1.30
---
Log message:
macros -> Inline functions
Lauros's patch
---
Diffs of the changes: (+13 -9)
ARMRegisterInfo.cpp | 22 +-
1 files changed, 13 insertions(+), 9 deletions(-)
Index: ll
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.39 -> 1.40
---
Log message:
move ExtWeakSymbols to AsmPrinter
---
Diffs of the changes: (+1 -10)
ARMAsmPrinter.cpp | 11 +--
1 files changed, 1 insertion(+), 10 deletions(-)
Index: llvm/lib/Target/ARM/ARMAsm
Changes in directory llvm/lib/Target/X86:
X86ATTAsmPrinter.cpp updated: 1.78 -> 1.79
X86AsmPrinter.cpp updated: 1.221 -> 1.222
X86AsmPrinter.h updated: 1.38 -> 1.39
---
Log message:
move ExtWeakSymbols to AsmPrinter
---
Diffs of the changes: (+2 -14)
X86ATTAsmPrinter.cpp |2 +-
X86AsmP
Changes in directory llvm/include/llvm/CodeGen:
AsmPrinter.h updated: 1.57 -> 1.58
---
Log message:
move ExtWeakSymbols to AsmPrinter
---
Diffs of the changes: (+5 -0)
AsmPrinter.h |5 +
1 files changed, 5 insertions(+)
Index: llvm/include/llvm/CodeGen/AsmPrinter.h
diff -u llvm/i
Changes in directory llvm/lib/CodeGen:
AsmPrinter.cpp updated: 1.125 -> 1.126
---
Log message:
move ExtWeakSymbols to AsmPrinter
---
Diffs of the changes: (+12 -0)
AsmPrinter.cpp | 12
1 files changed, 12 insertions(+)
Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/li
Changes in directory llvm/lib/Target/PowerPC:
PPCAsmPrinter.cpp updated: 1.221 -> 1.222
---
Log message:
move ExtWeakSymbols to AsmPrinter
---
Diffs of the changes: (+3 -15)
PPCAsmPrinter.cpp | 18 +++---
1 files changed, 3 insertions(+), 15 deletions(-)
Index: llvm/lib/Tar
Changes in directory llvm/test/Regression/CodeGen/ARM:
constants.ll updated: 1.5 -> 1.6
---
Log message:
avoid using a constant table when a constant can be used inline
---
Diffs of the changes: (+10 -0)
constants.ll | 10 ++
1 files changed, 10 insertions(+)
Index: llvm/test/R
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.91 -> 1.92
---
Log message:
avoid using a constant table when a constant can be used inline
---
Diffs of the changes: (+82 -24)
ARMISelDAGToDAG.cpp | 106
1 files
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.28 -> 1.29
---
Log message:
Avoid creating invalid sub/add instructions on the prolog/epilog
patch by Lauro
---
Diffs of the changes: (+86 -10)
ARMRegisterInfo.cpp | 96 ++
Changes in directory llvm/test/Regression/CodeGen/ARM:
addSubConstant.ll added (r1.1)
---
Log message:
Avoid creating invalid sub/add instructions on the prolog/epilog
patch by Lauro
---
Diffs of the changes: (+19 -0)
addSubConstant.ll | 19 +++
1 files changed, 19 insert
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.90 -> 1.91
ARMInstrInfo.td updated: 1.78 -> 1.79
---
Log message:
more general matching of the MVN instruction
---
Diffs of the changes: (+11 -37)
ARMISelDAGToDAG.cpp | 37 +++--
ARMI
Changes in directory llvm/test/Regression/CodeGen/ARM:
mvn.ll updated: 1.3 -> 1.4
---
Log message:
more general matching of the MVN instruction
---
Diffs of the changes: (+7 -1)
mvn.ll |8 +++-
1 files changed, 7 insertions(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/AR
Changes in directory llvm/test/Regression/CodeGen/ARM:
mvn.ll updated: 1.2 -> 1.3
---
Log message:
don't use "ordinary" addressing mode 1 when mvn is appropriate
---
Diffs of the changes: (+12 -1)
mvn.ll | 13 -
1 files changed, 12 insertions(+), 1 deletion(-)
Index: llvm/t
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.89 -> 1.90
---
Log message:
don't use "ordinary" addressing mode 1 when mvn is appropriate
---
Diffs of the changes: (+2 -0)
ARMISelDAGToDAG.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/ARM
Changes in directory llvm/test/Regression/CodeGen/ARM:
long.ll updated: 1.8 -> 1.9
mvn.ll updated: 1.1 -> 1.2
---
Log message:
use MVN to handle small negative constants
---
Diffs of the changes: (+7 -7)
long.ll |4 ++--
mvn.ll | 10 +-
2 files changed, 7 insertions(+), 7 de
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.88 -> 1.89
ARMInstrInfo.td updated: 1.77 -> 1.78
---
Log message:
use MVN to handle small negative constants
---
Diffs of the changes: (+32 -0)
ARMISelDAGToDAG.cpp | 21 +
ARMInstrInfo.td |
Changes in directory llvm/test/Regression/CodeGen/ARM:
mvn.ll added (r1.1)
---
Log message:
add mvn
---
Diffs of the changes: (+55 -0)
mvn.ll | 55 +++
1 files changed, 55 insertions(+)
Index: llvm/test/Regression/CodeGen/ARM/mvn.ll
d
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.76 -> 1.77
---
Log message:
add mvn
---
Diffs of the changes: (+3 -0)
ARMInstrInfo.td |3 +++
1 files changed, 3 insertions(+)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1
Changes in directory llvm/lib/Target/ARM:
README.txt updated: 1.8 -> 1.9
---
Log message:
add note
---
Diffs of the changes: (+13 -0)
README.txt | 13 +
1 files changed, 13 insertions(+)
Index: llvm/lib/Target/ARM/README.txt
diff -u llvm/lib/Target/ARM/README.txt:1.8 llvm/l
Changes in directory llvm/test/Regression/CodeGen/ARM:
constants.ll updated: 1.4 -> 1.5
---
Log message:
.align is in bits
.comm is in bytes
:-(
---
Diffs of the changes: (+1 -1)
constants.ll |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/A
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.38 -> 1.39
---
Log message:
.align is in bits
.comm is in bytes
:-(
---
Diffs of the changes: (+1 -1)
ARMAsmPrinter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/ARM/ARMAsmPrint
Changes in directory llvm/lib/Target/X86:
X86AsmPrinter.cpp updated: 1.220 -> 1.221
---
Log message:
fix test/Regression/CodeGen/X86/weak.ll
if a variable has no initialization, I->getInitializer() will fail
---
Diffs of the changes: (+1 -1)
X86AsmPrinter.cpp |2 +-
1 files changed, 1
Changes in directory llvm/test/Regression/CodeGen/X86:
weak.ll added (r1.1)
---
Log message:
fix test/Regression/CodeGen/X86/weak.ll
if a variable has no initialization, I->getInitializer() will fail
---
Diffs of the changes: (+3 -0)
weak.ll |3 +++
1 files changed, 3 insertions(+)
I
Changes in directory llvm/test/Regression/CodeGen/ARM:
section.ll updated: 1.4 -> 1.5
---
Log message:
use a . instead of a % in the grep expression
---
Diffs of the changes: (+1 -1)
section.ll |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen
Changes in directory llvm/test/Regression/CodeGen/ARM:
section.ll updated: 1.3 -> 1.4
---
Log message:
%progbits not @progbits
---
Diffs of the changes: (+1 -1)
section.ll |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/ARM/section.ll
diff -u
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.37 -> 1.38
---
Log message:
%progbits not @progbits
---
Diffs of the changes: (+1 -1)
ARMAsmPrinter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff -u ll
Changes in directory llvm/test/Regression/CodeGen/ARM:
section.ll updated: 1.2 -> 1.3
---
Log message:
add missing &&
---
Diffs of the changes: (+1 -1)
section.ll |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/ARM/section.ll
diff -u llvm/tes
Changes in directory llvm/test/Regression/CodeGen/ARM:
section.ll updated: 1.1 -> 1.2
---
Log message:
add \"aw\",@progbits" to ctors and dtors
---
Diffs of the changes: (+1 -0)
section.ll |1 +
1 files changed, 1 insertion(+)
Index: llvm/test/Regression/CodeGen/ARM/section.ll
diff -
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.36 -> 1.37
---
Log message:
add \"aw\",@progbits" to ctors and dtors
---
Diffs of the changes: (+11 -4)
ARMAsmPrinter.cpp | 15 +++
1 files changed, 11 insertions(+), 4 deletions(-)
Index: llvm/lib/Targe
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.75 -> 1.76
---
Log message:
fix truncstorei1
---
Diffs of the changes: (+1 -3)
ARMInstrInfo.td |4 +---
1 files changed, 1 insertion(+), 3 deletions(-)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Tar
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.35 -> 1.36
---
Log message:
fix alignment
---
Diffs of the changes: (+3 -3)
ARMAsmPrinter.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff -u llvm/l
Changes in directory llvm/test/Regression/CodeGen/ARM:
align.ll added (r1.1)
constants.ll updated: 1.3 -> 1.4
---
Log message:
fix alignment
---
Diffs of the changes: (+13 -1)
align.ll | 12
constants.ll |2 +-
2 files changed, 13 insertions(+), 1 deletion(-)
Index
Changes in directory llvm/test/Regression/CodeGen/ARM:
section.ll added (r1.1)
---
Log message:
make sure that we don't use a common symbol if a section was specified
---
Diffs of the changes: (+4 -0)
section.ll |4
1 files changed, 4 insertions(+)
Index: llvm/test/Regression/Co
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.33 -> 1.34
---
Log message:
make sure that we don't use a common symbol if a section was specified
---
Diffs of the changes: (+1 -0)
ARMAsmPrinter.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/A
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.31 -> 1.32
ARMTargetAsmInfo.cpp updated: 1.1 -> 1.2
---
Log message:
print weak references
---
Diffs of the changes: (+14 -1)
ARMAsmPrinter.cpp| 14 +-
ARMTargetAsmInfo.cpp |1 +
2 files changed, 1
Changes in directory llvm/test/Regression/CodeGen/ARM:
weak.ll updated: 1.1 -> 1.2
---
Log message:
print weak references
---
Diffs of the changes: (+10 -1)
weak.ll | 11 ++-
1 files changed, 10 insertions(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/ARM/weak.ll
diff -
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.86 -> 1.87
---
Log message:
expand memmove and memcpy
---
Diffs of the changes: (+2 -0)
ARMISelDAGToDAG.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib
Changes in directory llvm/test/Regression/CodeGen/ARM:
memfunc.ll added (r1.1)
---
Log message:
expand memmove and memcpy
---
Diffs of the changes: (+13 -0)
memfunc.ll | 13 +
1 files changed, 13 insertions(+)
Index: llvm/test/Regression/CodeGen/ARM/memfunc.ll
diff -c /dev/
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.85 -> 1.86
---
Log message:
add support for the "r" asm constraint
patch by Lauro Ramos Venancio
---
Diffs of the changes: (+27 -0)
ARMISelDAGToDAG.cpp | 27 +++
1 files changed, 27 insertion
Changes in directory llvm/test/Regression/CodeGen/ARM:
arm-asm.ll added (r1.1)
---
Log message:
add support for the "r" asm constraint
patch by Lauro Ramos Venancio
---
Diffs of the changes: (+7 -0)
arm-asm.ll |7 +++
1 files changed, 7 insertions(+)
Index: llvm/test/Regression/C
Changes in directory llvm/test/Regression/CodeGen/ARM:
weak.ll added (r1.1)
---
Log message:
add support for weak linkage
---
Diffs of the changes: (+9 -0)
weak.ll |9 +
1 files changed, 9 insertions(+)
Index: llvm/test/Regression/CodeGen/ARM/weak.ll
diff -c /dev/null llvm/te
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.29 -> 1.30
---
Log message:
add support for weak linkage
---
Diffs of the changes: (+1 -1)
ARMAsmPrinter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.28 -> 1.29
ARMISelDAGToDAG.cpp updated: 1.84 -> 1.85
ARMInstrInfo.td updated: 1.74 -> 1.75
ARMRegisterInfo.cpp updated: 1.25 -> 1.26
---
Log message:
implement load effective address similar to the alpha backend
remove lea_a
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.27 -> 1.28
ARMISelDAGToDAG.cpp updated: 1.82 -> 1.83
ARMInstrInfo.td updated: 1.73 -> 1.74
ARMRegisterInfo.cpp updated: 1.24 -> 1.25
---
Log message:
initial implementation of addressing mode 2
TODO: fix lea_addri
---
Diff
Changes in directory llvm/lib/Target/ARM:
ARMTargetMachine.cpp updated: 1.12 -> 1.13
---
Log message:
revert previous patch
---
Diffs of the changes: (+0 -2)
ARMTargetMachine.cpp |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/Target/ARM/ARMTargetMachine.cpp
diff -u llvm/lib/T
Changes in directory llvm/lib/Support:
FoldingSet.cpp updated: 1.10 -> 1.11
---
Log message:
assert.h -> cassert
---
Diffs of the changes: (+1 -1)
FoldingSet.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Support/FoldingSet.cpp
diff -u llvm/lib/Support/Fold
Changes in directory llvm/lib/Target/ARM:
ARMTargetMachine.cpp updated: 1.11 -> 1.12
---
Log message:
add createCFGSimplificationPass to ARMTargetMachine::addInstSelector
---
Diffs of the changes: (+2 -0)
ARMTargetMachine.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Ta
Changes in directory llvm/lib/Support:
FoldingSet.cpp updated: 1.9 -> 1.10
---
Log message:
#include
---
Diffs of the changes: (+1 -0)
FoldingSet.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Support/FoldingSet.cpp
diff -u llvm/lib/Support/FoldingSet.cpp:1.9 llvm/lib/Sup
Changes in directory llvm/lib/Target/ARM:
ARM.h updated: 1.6 -> 1.7
ARMAsmPrinter.cpp updated: 1.26 -> 1.27
ARMISelDAGToDAG.cpp updated: 1.81 -> 1.82
---
Log message:
move ARMCondCodeToString to ARMAsmPrinter.cpp
remove unused variables from lowerCall
---
Diffs of the changes: (+21 -23)
AR
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.25 -> 1.26
---
Log message:
print null values in bss
---
Diffs of the changes: (+4 -2)
ARMAsmPrinter.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
dif
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.71 -> 1.72
---
Log message:
implement zextload bool and truncstore bool
---
Diffs of the changes: (+10 -0)
ARMInstrInfo.td | 10 ++
1 files changed, 10 insertions(+)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
1 - 100 of 290 matches
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