[llvm-commits] CVS: llvm/lib/Target/X86/X86Subtarget.cpp

Changes in directory llvm/lib/Target/X86: X86Subtarget.cpp updated: 1.37 -> 1.38 --- Log message: Proper fix. --- Diffs of the changes: (+4 -5) X86Subtarget.cpp |9 - 1 files changed, 4 insertions(+), 5 deletions(-) Index: llvm/lib/Target/X86/X86Subtarget.cpp diff -u llvm/lib/

[llvm-commits] CVS: llvm/lib/Target/X86/X86JITInfo.cpp

Changes in directory llvm/lib/Target/X86: X86JITInfo.cpp updated: 1.29 -> 1.30 --- Log message: One more try. --- Diffs of the changes: (+6 -4) X86JITInfo.cpp | 10 ++ 1 files changed, 6 insertions(+), 4 deletions(-) Index: llvm/lib/Target/X86/X86JITInfo.cpp diff -u llvm/lib/Tar

[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp

Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.519 -> 1.520 --- Log message: Undo Chris' last patch, it caused a regression. --- Diffs of the changes: (+2 -2) InstructionCombining.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Inde

[llvm-commits] CVS: llvm/lib/Target/X86/X86JITInfo.cpp

Changes in directory llvm/lib/Target/X86: X86JITInfo.cpp updated: 1.28 -> 1.29 --- Log message: Unbreak x86-64 build. --- Diffs of the changes: (+9 -2) X86JITInfo.cpp | 11 +-- 1 files changed, 9 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86JITInfo.cpp diff -u ll

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.225 -> 1.226 --- Log message: Be careful when looking through a vbit_convert. Optimizing this: (vector_shuffle (vbitconvert (vbuildvector (copyfromreg v4f32), 1, v4f32), 4, f32), (undef, undef, undef, undef), (0,

[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/fparith.ll

Changes in directory llvm/test/Regression/CodeGen/ARM: fparith.ll updated: 1.3 -> 1.4 --- Log message: add fdivs e fdivd --- Diffs of the changes: (+15 -1) fparith.ll | 16 +++- 1 files changed, 15 insertions(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/ARM/fparith

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td

Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.57 -> 1.58 --- Log message: add fdivs e fdivd --- Diffs of the changes: (+2 -1) ARMInstrInfo.td |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Tar

[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/longarith.ll

Changes in directory llvm/test/Regression/CodeGen/ARM: longarith.ll added (r1.1) --- Log message: expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS --- Diffs of the changes: (+24 -0) longarith.ll | 24 1 files changed, 24 insertions(+) Index: llvm/test/

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp ARMISelDAGToDAG.cpp ARMInstrInfo.td

Changes in directory llvm/lib/Target/ARM: ARMAsmPrinter.cpp updated: 1.22 -> 1.23 ARMISelDAGToDAG.cpp updated: 1.70 -> 1.71 ARMInstrInfo.td updated: 1.56 -> 1.57 --- Log message: expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS --- Diffs of the changes: (+20 -8) ARMAsmPrinter.cpp

[llvm-commits] CVS: llvm/lib/Target/X86/X86JITInfo.cpp

Changes in directory llvm/lib/Target/X86: X86JITInfo.cpp updated: 1.27 -> 1.28 --- Log message: Added a X86CompilationCallback variant which saves XMM argument registers for targets with SSE. --- Diffs of the changes: (+58 -1) X86JITInfo.cpp | 59 +

[llvm-commits] CVS: llvm/lib/Target/X86/X86Subtarget.cpp X86Subtarget.h

Changes in directory llvm/lib/Target/X86: X86Subtarget.cpp updated: 1.36 -> 1.37 X86Subtarget.h updated: 1.19 -> 1.20 --- Log message: Proper fix for rdar://problem/4770604 Thanks to Stuart Hastings! --- Diffs of the changes: (+21 -12) X86Subtarget.cpp | 25 +

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.224 -> 1.225 SelectionDAGISel.cpp updated: 1.288 -> 1.289 --- Log message: Pass AliasAnalysis thru to DAGCombiner. --- Diffs of the changes: (+18 -6) DAGCombiner.cpp | 15 +++ SelectionDAGISel.

[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h

Changes in directory llvm/include/llvm/CodeGen: SelectionDAG.h updated: 1.137 -> 1.138 --- Log message: Pass AliasAnalysis thru to DAGCombiner. --- Diffs of the changes: (+2 -1) SelectionDAG.h |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/include/llvm/CodeGen/Sel

[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineJumpTableInfo.h

Changes in directory llvm/include/llvm/CodeGen: MachineJumpTableInfo.h updated: 1.3 -> 1.4 --- Log message: add a ReplaceMBBInJumpTables method --- Diffs of the changes: (+12 -0) MachineJumpTableInfo.h | 12 1 files changed, 12 insertions(+) Index: llvm/include/llvm/CodeGe

[llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp

Changes in directory llvm/lib/CodeGen: DwarfWriter.cpp updated: 1.79 -> 1.80 --- Log message: Global name regression. --- Diffs of the changes: (+5 -1) DwarfWriter.cpp |6 +- 1 files changed, 5 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/DwarfWriter.cpp diff -u llvm/lib/C

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td

Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.54 -> 1.55 --- Log message: add the FPBinOp class --- Diffs of the changes: (+8 -9) ARMInstrInfo.td | 17 - 1 files changed, 8 insertions(+), 9 deletions(-) Index: llvm/lib/Target/ARM/ARMInstrInfo.td d

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td

Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.55 -> 1.56 --- Log message: define the DFPBinOp class --- Diffs of the changes: (+10 -15) ARMInstrInfo.td | 25 ++--- 1 files changed, 10 insertions(+), 15 deletions(-) Index: llvm/lib/Target/ARM/A

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td

Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.53 -> 1.54 --- Log message: define the Addr1BinOp class --- Diffs of the changes: (+14 -34) ARMInstrInfo.td | 48 ++-- 1 files changed, 14 insertions(+), 34 deletions(-) Ind

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td

Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.52 -> 1.53 --- Log message: define the IntBinOp class and use it to implement the multiply instructions --- Diffs of the changes: (+13 -12) ARMInstrInfo.td | 25 + 1 files changed, 13 insertions(

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td

Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.51 -> 1.52 --- Log message: fix assembly syntax --- Diffs of the changes: (+4 -4) ARMInstrInfo.td |8 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm

[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/load.ll

Changes in directory llvm/test/Regression/CodeGen/ARM: load.ll added (r1.1) --- Log message: implement LDRB, LDRSB, LDRH and LDRSH --- Diffs of the changes: (+33 -0) load.ll | 33 + 1 files changed, 33 insertions(+) Index: llvm/test/Regression/CodeGen/AR

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td README.txt

Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.50 -> 1.51 README.txt updated: 1.6 -> 1.7 --- Log message: implement LDRB, LDRSB, LDRH and LDRSH --- Diffs of the changes: (+20 -0) ARMInstrInfo.td | 16 README.txt |4 2 files changed, 20

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td ARMMul.cpp README.txt

Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.49 -> 1.50 ARMMul.cpp updated: 1.2 -> 1.3 README.txt updated: 1.5 -> 1.6 --- Log message: implement smull and umull --- Diffs of the changes: (+24 -5) ARMInstrInfo.td | 10 ++ ARMMul.cpp | 14 +---

[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/long.ll

Changes in directory llvm/test/Regression/CodeGen/ARM: long.ll updated: 1.5 -> 1.6 --- Log message: implement smull and umull --- Diffs of the changes: (+19 -1) long.ll | 20 +++- 1 files changed, 19 insertions(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/ARM/l