Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.146 -> 1.147
---
Log message:
Use a multiclass to simplify 'SSE2 Integer comparison'
---
Diffs of the changes: (+19 -61)
X86InstrSSE.td | 80 +
1 files changed, 19
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.145 -> 1.146
---
Log message:
move class defns close to uses to make it easier to read
---
Diffs of the changes: (+18 -17)
X86InstrSSE.td | 35 ++-
1 files changed, 18 insertions(+), 17 de
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.144 -> 1.145
---
Log message:
simplify horizontal op definitions
---
Diffs of the changes: (+21 -26)
X86InstrSSE.td | 47 +--
1 files changed, 21 insertions(+), 26 deletions(-)
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.143 -> 1.144
---
Log message:
remove more unneeded type info
---
Diffs of the changes: (+51 -51)
X86InstrSSE.td | 102 -
1 files changed, 51 insertions(+), 51 deleti
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.142 -> 1.143
---
Log message:
remove unneeded definitions and type info
---
Diffs of the changes: (+0 -3)
X86InstrSSE.td |3 ---
1 files changed, 3 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.141 -> 1.142
---
Log message:
remove some unneeded type info
---
Diffs of the changes: (+28 -30)
X86InstrSSE.td | 58 +++--
1 files changed, 28 insertions(+), 30 deleti
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.140 -> 1.141
---
Log message:
simplify patterns by merging in operand info
---
Diffs of the changes: (+30 -34)
X86InstrSSE.td | 64 ++---
1 files changed, 30 insertions
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.139 -> 1.140
---
Log message:
Factor operands into packed unary classes
---
Diffs of the changes: (+21 -25)
X86InstrSSE.td | 46 +-
1 files changed, 21 insertions(+), 25 deleti
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.138 -> 1.139
---
Log message:
remove dead/duplicate instructions
---
Diffs of the changes: (+0 -21)
X86InstrSSE.td | 21 -
1 files changed, 21 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.137 -> 1.138
---
Log message:
Pull operand info up into parent class for scalar sse intrinsics.
---
Diffs of the changes: (+41 -61)
X86InstrSSE.td | 102 ++---
1 files c
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.136 -> 1.137
---
Log message:
convert the sole sd unary intrinsic to a multiclass for consistency
---
Diffs of the changes: (+9 -19)
X86InstrSSE.td | 28 +---
1 files changed, 9 insertions(+), 19
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.135 -> 1.136
---
Log message:
pull operand string into the multiclass
---
Diffs of the changes: (+9 -10)
X86InstrSSE.td | 19 +--
1 files changed, 9 insertions(+), 10 deletions(-)
Index: llvm/lib/Targe
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.134 -> 1.135
---
Log message:
Remove RSQRTSS[rm] RCPSS[rm], which are dead.
Introduce SS_IntUnary, a multiclass to replace SS_Int[rm].
---
Diffs of the changes: (+16 -21)
X86InstrSSE.td | 37 ---
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.133 -> 1.134
---
Log message:
eliminate redundancy
---
Diffs of the changes: (+32 -60)
X86InstrSSE.td | 92 +++--
1 files changed, 32 insertions(+), 60 deletions(-)
I
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.404 -> 1.405
---
Log message:
Fix a bug legalizing zero-extending i64 loads into 32-bit loads. The bottom
part was always forced to be sextload, even when we needed an zextload.
---
Diffs of the changes: (+2 -3)
Changes in directory llvm/lib/Target/Alpha:
AlphaTargetAsmInfo.cpp updated: 1.3 -> 1.4
---
Log message:
Set the jt section
---
Diffs of the changes: (+1 -0)
AlphaTargetAsmInfo.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/Alpha/AlphaTargetAsmInfo.cpp
diff -u llvm/l
Changes in directory llvm/lib/CodeGen/SelectionDAG:
TargetLowering.cpp updated: 1.73 -> 1.74
---
Log message:
initialize ivar
---
Diffs of the changes: (+1 -0)
TargetLowering.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff -u llv
Changes in directory llvm/lib/CodeGen:
AsmPrinter.cpp updated: 1.107 -> 1.108
---
Log message:
If a target uses a GOT, put it in the jt data section, not the text
section. This will fix alpha when Andrew implements
AlphaTargetMachine::getTargetLowering().
---
Diffs of the changes: (+12 -4
Changes in directory llvm/lib/Target/Alpha:
AlphaISelLowering.cpp updated: 1.64 -> 1.65
---
Log message:
Alpha uses a got
---
Diffs of the changes: (+2 -0)
AlphaISelLowering.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/li
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.79 -> 1.80
---
Log message:
Add support for targets to declare that they use a GOT
---
Diffs of the changes: (+11 -0)
TargetLowering.h | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/include/llvm
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.283 -> 1.284
---
Log message:
jump tables handle pic
---
Diffs of the changes: (+0 -5)
SelectionDAGISel.cpp |5 -
1 files changed, 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGI
This fixes the build on mingw. Anton K wrote this patch:
dwarf.diff
Description: Binary data
-Chris___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Changes in directory llvm/lib/CodeGen:
MachineBasicBlock.cpp updated: 1.31 -> 1.32
---
Log message:
print labels even if a MBB doesn't have a corresponding LLVM BB, just don't
print the LLVM BB label.
---
Diffs of the changes: (+4 -3)
MachineBasicBlock.cpp |7 ---
1 files changed,
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.56 -> 1.57
ARMInstrInfo.td updated: 1.32 -> 1.33
---
Log message:
add optional input flag to FMRRD
---
Diffs of the changes: (+4 -3)
ARMISelDAGToDAG.cpp |4 ++--
ARMInstrInfo.td |3 ++-
2 files changed, 4
Changes in directory llvm-test/External/SPEC/CFP2006/459.GemsFDTD:
Makefile updated: 1.2 -> 1.3
---
Log message:
Added dependencies so that things build properly
---
Diffs of the changes: (+15 -0)
Makefile | 15 +++
1 files changed, 15 insertions(+)
Index: llvm-test/Externa
Changes in directory llvm-test/External/SPEC/CFP2006/454.calculix:
Makefile updated: 1.4 -> 1.5
---
Log message:
Another fix for the caluculix test. It was getting header files from the
wrong place. Blast!
---
Diffs of the changes: (+1 -1)
Makefile |2 +-
1 files changed, 1 insertion(+
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.55 -> 1.56
---
Log message:
add support for calling functions that return double
---
Diffs of the changes: (+19 -8)
ARMISelDAGToDAG.cpp | 27 +++
1 files changed, 19 insertions(+), 8 deletion
Changes in directory llvm/test/Regression/CodeGen/ARM:
fp.ll updated: 1.5 -> 1.6
---
Log message:
add support for calling functions that return double
---
Diffs of the changes: (+7 -3)
fp.ll | 10 +++---
1 files changed, 7 insertions(+), 3 deletions(-)
Index: llvm/test/Regression/C
Changes in directory llvm/lib/Target/X86:
X86Subtarget.cpp updated: 1.35 -> 1.36
---
Log message:
80 col violation.
---
Diffs of the changes: (+4 -3)
X86Subtarget.cpp |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86Subtarget.cpp
diff -u llvm/
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.140 -> 1.141
---
Log message:
ugly codegen
---
Diffs of the changes: (+22 -0)
README.txt | 22 ++
1 files changed, 22 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/READ
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.403 -> 1.404
---
Log message:
Fix a miscompilation of:
long long foo(long long X) {
return (long long)(signed char)(int)X;
}
Instead of:
_foo:
extsb r2, r4
srawi r3, r4, 31
mr r4, r2
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.54 -> 1.55
---
Log message:
fix some bugs affecting functions with no arguments
---
Diffs of the changes: (+4 -2)
ARMISelDAGToDAG.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/T
Changes in directory llvm/test/Regression/CodeGen/ARM:
call.ll updated: 1.1 -> 1.2
---
Log message:
fix some bugs affecting functions with no arguments
---
Diffs of the changes: (+2 -0)
call.ll |2 ++
1 files changed, 2 insertions(+)
Index: llvm/test/Regression/CodeGen/ARM/call.ll
di
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.19 -> 1.20
---
Log message:
fix the stack alignment
---
Diffs of the changes: (+3 -0)
ARMRegisterInfo.cpp |3 +++
1 files changed, 3 insertions(+)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/
Changes in directory llvm/test/Regression/CodeGen/ARM:
fp.ll updated: 1.4 -> 1.5
---
Log message:
add support for calling functions that have double arguments
---
Diffs of the changes: (+8 -2)
fp.ll | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
Index: llvm/test/Regr
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.53 -> 1.54
---
Log message:
add support for calling functions that have double arguments
---
Diffs of the changes: (+22 -7)
ARMISelDAGToDAG.cpp | 29 ++---
1 files changed, 22 insertions(+),
Changes in directory llvm/lib/Target/X86:
Makefile updated: 1.28 -> 1.29
X86.td updated: 1.27 -> 1.28
X86Subtarget.cpp updated: 1.34 -> 1.35
X86Subtarget.h updated: 1.18 -> 1.19
---
Log message:
Still need to support -mcpu=<> or cross compilation will fail. Doh.
---
Diffs of the changes: (+19
Changes in directory llvm/lib/Target/X86:
Makefile updated: 1.27 -> 1.28
README.txt updated: 1.139 -> 1.140
X86.td updated: 1.26 -> 1.27
X86Subtarget.cpp updated: 1.33 -> 1.34
X86Subtarget.h updated: 1.17 -> 1.18
---
Log message:
Do away with CPU feature list. Just use CPUID to detect MMX, SSE,
Changes in directory llvm/lib/Target/X86:
X86Subtarget.cpp updated: 1.32 -> 1.33
---
Log message:
It appears the inline asm in GetCpuIDAndInfo() may clobbers some registers if
it isn't inlined (at < -O3). Force it to be inlined.
---
Diffs of the changes: (+3 -3)
X86Subtarget.cpp |6 +++
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