[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMISelDAGToDAG.cpp updated: 1.53 -> 1.54
---
Log message:

add support for calling functions that have double arguments


---
Diffs of the changes:  (+22 -7)

 ARMISelDAGToDAG.cpp |   29 ++++++++++++++++++++++-------
 1 files changed, 22 insertions(+), 7 deletions(-)


Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.53 
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.54
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.53        Thu Oct  5 17:59:31 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp     Fri Oct  6 07:50:22 2006
@@ -265,16 +265,31 @@
   // and flag operands which copy the outgoing args into the appropriate regs.
   SDOperand InFlag;
   for (unsigned i = 0, e = Layout.lastRegArg(); i <= e; ++i) {
-    SDOperand Arg = Op.getOperand(5+2*i);
-    unsigned  Reg = regs[Layout.getRegisterNum(i)];
-    assert(Layout.getType(i) == Arg.getValueType());
-    assert(Layout.getType(i) == MVT::i32);
-    Chain         = DAG.getCopyToReg(Chain, Reg, Arg, InFlag);
-    InFlag        = Chain.getValue(1);
+    SDOperand     Arg = Op.getOperand(5+2*i);
+    unsigned   RegNum = Layout.getRegisterNum(i);
+    unsigned     Reg1 = regs[RegNum];
+    MVT::ValueType VT = Layout.getType(i);
+    assert(VT == Arg.getValueType());
+    assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64);
 
     // Add argument register to the end of the list so that it is known live
     // into the call.
-    Ops.push_back(DAG.getRegister(Reg, Arg.getValueType()));
+    Ops.push_back(DAG.getRegister(Reg1, MVT::i32));
+    if (VT == MVT::f64) {
+      unsigned    Reg2 = regs[RegNum + 1];
+      SDOperand SDReg1 = DAG.getRegister(Reg1, MVT::i32);
+      SDOperand SDReg2 = DAG.getRegister(Reg2, MVT::i32);
+
+      Ops.push_back(DAG.getRegister(Reg2, MVT::i32));
+      SDVTList    VTs = DAG.getVTList(MVT::Other, MVT::Flag);
+      SDOperand Ops[] = {Chain, SDReg1, SDReg2, Arg}; //missing flag
+      Chain = DAG.getNode(ARMISD::FMRRD, VTs, Ops, 4);
+    } else {
+      if (VT == MVT::f32)
+        Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg);
+      Chain = DAG.getCopyToReg(Chain, Reg1, Arg, InFlag);
+    }
+    InFlag = Chain.getValue(1);
   }
 
   std::vector<MVT::ValueType> NodeTys;



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