Changes in directory llvm/tools/gccas:
gccas.cpp updated: 1.114 -> 1.115
---
Log message:
Turn on loop unswitching tonight
---
Diffs of the changes: (+1 -0)
gccas.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/tools/gccas/gccas.cpp
diff -u llvm/tools/gccas/gccas.cpp:1.114 llvm
Changes in directory llvm/lib/Transforms/Scalar:
LoopUnswitch.cpp updated: 1.33 -> 1.34
---
Log message:
Add some comments, simplify some code, and fix a bug that caused rewriting
to rewrite with the wrong value.
---
Diffs of the changes: (+26 -34)
LoopUnswitch.cpp | 60 +
Changes in directory llvm/lib/Target/X86:
X86ATTAsmPrinter.h updated: 1.7 -> 1.8
X86ISelLowering.cpp updated: 1.92 -> 1.93
X86InstrInfo.td updated: 1.246 -> 1.247
X86InstrSSE.td updated: 1.4 -> 1.5
X86IntelAsmPrinter.h updated: 1.8 -> 1.9
---
Log message:
Added MMX, SSE1, and SSE2 vector instru
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.89 -> 1.90
PPCISelLowering.h updated: 1.22 -> 1.23
---
Log message:
split register class handling from explicit physreg handling.
---
Diffs of the changes: (+5 -6)
PPCISelLowering.cpp |7 +++
PPCISelLoweri
Changes in directory llvm/tools/opt:
Makefile updated: 1.53 -> 1.54
---
Log message:
reorder some libraries
---
Diffs of the changes: (+1 -1)
Makefile |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/tools/opt/Makefile
diff -u llvm/tools/opt/Makefile:1.53 llvm/tools/
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.52 -> 1.53
---
Log message:
split register class handling from explicit physreg handling.
---
Diffs of the changes: (+16 -6)
TargetLowering.h | 22 --
1 files changed, 16 insertions(+), 6 delet
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.34 -> 1.35
---
Log message:
split register class handling from explicit physreg handling.
---
Diffs of the changes: (+21 -11)
TargetLowering.cpp | 32 +---
1 files changed, 21 insertions(+), 1
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.91 -> 1.92
X86ISelLowering.h updated: 1.29 -> 1.30
---
Log message:
split register class handling from explicit physreg handling.
---
Diffs of the changes: (+5 -6)
X86ISelLowering.cpp |7 +++
X86ISelLowering.h
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.165 -> 1.166
---
Log message:
split register class handling from explicit physreg handling.
---
Diffs of the changes: (+77 -34)
SelectionDAGISel.cpp | 111 +++---
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.68 -> 1.69
---
Log message:
expose the set of values types holdable in a regclass to clients
---
Diffs of the changes: (+17 -1)
MRegisterInfo.h | 18 +-
1 files changed, 17 insertions(+), 1 deletion
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.164 -> 1.165
---
Log message:
Adjust to changes in getRegForInlineAsmConstraint prototype
---
Diffs of the changes: (+18 -18)
SelectionDAGISel.cpp | 36 ++--
1 files change
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.90 -> 1.91
X86ISelLowering.h updated: 1.28 -> 1.29
---
Log message:
Updates to match change of getRegForInlineAsmConstraint prototype
---
Diffs of the changes: (+5 -3)
X86ISelLowering.cpp |5 +++--
X86ISelLowering
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.33 -> 1.34
---
Log message:
Updates to match change of getRegForInlineAsmConstraint prototype
---
Diffs of the changes: (+2 -1)
TargetLowering.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/l
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.88 -> 1.89
PPCISelLowering.h updated: 1.21 -> 1.22
---
Log message:
Updates to match change of getRegForInlineAsmConstraint prototype
---
Diffs of the changes: (+5 -3)
PPCISelLowering.cpp |5 +++--
PPCISelLowe
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.51 -> 1.52
---
Log message:
Pass in a value type to getRegForInlineAsmConstraint, allowing targets to
select different sets of registers depending on the type requested.
---
Diffs of the changes: (+2 -1)
TargetLower
Changes in directory llvm/lib/Target/X86:
X86InstrFPStack.td updated: 1.2 -> 1.3
X86InstrInfo.td updated: 1.245 -> 1.246
X86InstrMMX.td updated: 1.1 -> 1.2
X86InstrSSE.td updated: 1.3 -> 1.4
---
Log message:
One more round of reorg so sabre doesn't freak out. :-)
---
Diffs of the changes: (+
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.244 -> 1.245
X86InstrSSE.td updated: 1.2 -> 1.3
---
Log message:
A big more cleaning up.
---
Diffs of the changes: (+18 -23)
X86InstrInfo.td | 37 ++---
X86InstrSSE.td |4
2 fil
Changes in directory llvm/lib/Target/X86:
X86InstrFPStack.td updated: 1.1 -> 1.2
X86InstrInfo.td updated: 1.243 -> 1.244
X86InstrSSE.td updated: 1.1 -> 1.2
---
Log message:
Moving things to their proper places.
---
Diffs of the changes: (+303 -303)
X86InstrFPStack.td | 101 ---
Changes in directory llvm/lib/Target:
README.txt updated: 1.7 -> 1.8
---
Log message:
missed optzn
---
Diffs of the changes: (+11 -0)
README.txt | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/lib/Target/README.txt
diff -u llvm/lib/Target/README.txt:1.7 llvm/lib/Target/
Changes in directory llvm/lib/Target/Sparc:
SparcInstrInfo.td updated: 1.122 -> 1.123
---
Log message:
The HasNoV9 hack isn't needed here, now that tblgen knows that
CustomDAGSchedInserter
instructions are expensive.
---
Diffs of the changes: (+2 -3)
SparcInstrInfo.td |5 ++---
1 fil
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