Changes in directory llvm/lib/Target/SparcV8:
README.txt updated: 1.47 -> 1.48
---
Log message:
okay, one more
---
Diffs of the changes: (+2 -0)
README.txt |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/SparcV8/README.txt
diff -u llvm/lib/Target/SparcV8/README.txt:1.4
Changes in directory llvm/lib/Target/SparcV8:
README.txt updated: 1.46 -> 1.47
---
Log message:
another note
---
Diffs of the changes: (+2 -1)
README.txt |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/SparcV8/README.txt
diff -u llvm/lib/Target/SparcV8/
Changes in directory llvm/lib/Target/SparcV8:
README.txt updated: 1.45 -> 1.46
---
Log message:
More notes
---
Diffs of the changes: (+15 -1)
README.txt | 16 +++-
1 files changed, 15 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/SparcV8/README.txt
diff -u llvm/lib/Ta
Changes in directory llvm/lib/Target/SparcV8:
README.txt updated: 1.44 -> 1.45
---
Log message:
another one
---
Diffs of the changes: (+1 -0)
README.txt |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/SparcV8/README.txt
diff -u llvm/lib/Target/SparcV8/README.txt:1.44
ll
Changes in directory llvm/lib/Target/SparcV8:
README.txt updated: 1.43 -> 1.44
---
Log message:
add a note
---
Diffs of the changes: (+29 -0)
README.txt | 29 +
1 files changed, 29 insertions(+)
Index: llvm/lib/Target/SparcV8/README.txt
diff -u llvm/lib/Targ
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.114 -> 1.115
---
Log message:
add conditional moves of float and double values on int/fp condition codes.
---
Diffs of the changes: (+27 -6)
SparcV8InstrInfo.td | 33 +++--
1 files ch
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.49 -> 1.50
---
Log message:
example nate pointed out
---
Diffs of the changes: (+33 -0)
README.txt | 33 +
1 files changed, 33 insertions(+)
Index: llvm/lib/Target/PowerPC/README.txt
dif
Changes in directory llvm/lib/Target/SparcV8:
SparcV8.h updated: 1.9 -> 1.10
SparcV8ISelDAGToDAG.cpp updated: 1.72 -> 1.73
SparcV8InstrInfo.td updated: 1.113 -> 1.114
---
Log message:
treat conditional branches the same way as conditional moves (giving them
an operand that contains the condcode
Changes in directory llvm/lib/Target/SparcV8:
SparcV8.h updated: 1.8 -> 1.9
SparcV8AsmPrinter.cpp updated: 1.51 -> 1.52
SparcV8ISelDAGToDAG.cpp updated: 1.71 -> 1.72
SparcV8InstrInfo.td updated: 1.112 -> 1.113
---
Log message:
compactify all of the integer conditional moves into one instruction
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.111 -> 1.112
---
Log message:
Add immediate forms of integer cmovs
---
Diffs of the changes: (+49 -6)
SparcV8InstrInfo.td | 55 ++--
1 files changed, 49 insertions
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.110 -> 1.111
---
Log message:
Shrinkify
---
Diffs of the changes: (+86 -143)
SparcV8InstrInfo.td | 229 +++-
1 files changed, 86 insertions(+), 143 deletions(-)
I
Changes in directory llvm/test/Regression/TableGen:
DagIntSubst.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+10 -0)
DagIntSubst.ll | 10 ++
1 files changed, 10 insertions(+)
Index: llvm/test/Regression/TableGen/DagIntSubst.ll
diff -c /dev/null llvm/
Changes in directory llvm/utils/TableGen:
FileParser.y updated: 1.39 -> 1.40
Record.cpp updated: 1.49 -> 1.50
Record.h updated: 1.54 -> 1.55
---
Log message:
implement test/Regression/TableGen/DagIntSubst.ll
---
Diffs of the changes: (+19 -2)
FileParser.y |2 +-
Record.cpp | 11 +++
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.109 -> 1.110
---
Log message:
Add the full complement of conditional moves of integer registers.
---
Diffs of the changes: (+115 -7)
SparcV8InstrInfo.td | 122 +---
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.70 -> 1.71
---
Log message:
Compile this:
void %X(int %A) {
%C = setlt int %A, 123 ; [#uses=1]
br bool %C, label %T, label %F
T: ; preds = %0
call int %main( int 0 )
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.297 -> 1.298
---
Log message:
Only insert an AND when converting from BR_COND to BRCC if needed.
---
Diffs of the changes: (+3 -1)
LegalizeDAG.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
I
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.h updated: 1.21 -> 1.22
X86ISelLowering.cpp updated: 1.69 -> 1.70
X86InstrInfo.td updated: 1.223 -> 1.224
---
Log message:
Added custom lowering of fabs
---
Diffs of the changes: (+49 -4)
X86ISelLowering.cpp | 13 +++--
X86
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.48 -> 1.49
---
Log message:
add the 'lucas' optimization
---
Diffs of the changes: (+25 -0)
README.txt | 25 +
1 files changed, 25 insertions(+)
Index: llvm/lib/Target/PowerPC/README.txt
diff -u
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.69 -> 1.70
---
Log message:
I don't see why this optimization isn't safe, but it isn't, so disable it
---
Diffs of the changes: (+2 -1)
SparcV8ISelDAGToDAG.cpp |3 ++-
1 files changed, 2 insertions(+), 1 d
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.32 -> 1.33
---
Log message:
Another high-prio selection performance bug
---
Diffs of the changes: (+46 -0)
README.txt | 46 ++
1 files changed, 46 insertions(+)
Index: llvm/lib/T
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.60 -> 1.61
SelectionDAGISel.cpp updated: 1.142 -> 1.143
---
Log message:
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = al
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.31 -> 1.32
---
Log message:
more mumbling
---
Diffs of the changes: (+4 -0)
README.txt |4
1 files changed, 4 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.31 llvm/lib/
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.30 -> 1.31
---
Log message:
add some notes
---
Diffs of the changes: (+24 -0)
README.txt | 24
1 files changed, 24 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/RE
Changes in directory llvm/test/Regression/CodeGen/X86:
setuge.ll added (r1.1)
---
Log message:
Don't generate (or setp, setae) for SETUGE. Simply flip the operands around and
generate SETULT instead.
---
Diffs of the changes: (+12 -0)
setuge.ll | 12
1 files changed, 12 inse
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.68 -> 1.69
---
Log message:
Don't generate complex sequence for SETOLE, SETOLT, SETULT, and SETUGT. Flip
the order of the compare operands and generate SETOGT, SETOGE, SETUGE, and
SETULE instead.
---
Diffs of the changes
Changes in directory llvm/lib/CodeGen:
AsmPrinter.cpp updated: 1.41 -> 1.42
---
Log message:
Print the most trivial inline asms.
---
Diffs of the changes: (+12 -1)
AsmPrinter.cpp | 13 -
1 files changed, 12 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/AsmPrinter.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.296 -> 1.297
---
Log message:
Fix a bug in my legalizer reworking that caused the X86 backend to not get
a chance to custom legalize setcc, which broke a bunch of C++ Codes.
Testcase here: CodeGen/X86/2006-01-30-Lo
Changes in directory llvm/test/Regression/CodeGen/X86:
2006-01-30-LongSetcc.ll added (r1.1)
---
Log message:
new testcase for the 'C++' failures last night.
---
Diffs of the changes: (+6 -0)
2006-01-30-LongSetcc.ll |6 ++
1 files changed, 6 insertions(+)
Index: llvm/test/Regressi
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.68 -> 1.69
---
Log message:
Fix FP constants, and the SparcV8/2006-01-22-BitConvertLegalize.ll failure from
last night
---
Diffs of the changes: (+3 -0)
SparcV8ISelDAGToDAG.cpp |3 +++
1 files changed, 3
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.67 -> 1.68
---
Log message:
i64 -> f32, f32 -> i64 and some clean up.
---
Diffs of the changes: (+27 -31)
X86ISelLowering.cpp | 58
1 files changed, 27 insertions
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.66 -> 1.67
X86ISelLowering.h updated: 1.20 -> 1.21
X86InstrInfo.td updated: 1.222 -> 1.223
---
Log message:
Always use FP stack instructions to perform i64 to f64 as well as f64 to i64
conversions. SSE does not have instru
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