[llvm-branch-commits] [llvm] AMDGPU: Fold 64-bit immediate into copy to AV class (PR #155615)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/155615 >From 05821956deebe21b8dd2bdd0a5962a0987d42775 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 26 Aug 2025 23:53:57 +0900 Subject: [PATCH] AMDGPU: Fold 64-bit immediate into copy to AV class This is in

[llvm-branch-commits] [llvm] AMDGPU: Refactor isImmOperandLegal (PR #155607)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/155607 >From 20442f6adbd765db0493edabef85228b56b0a1ef Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 27 Aug 2025 15:35:53 +0900 Subject: [PATCH] AMDGPU: Refactor isImmOperandLegal The goal is to expose more v

[llvm-branch-commits] [llvm] AMDGPU: Add agpr variants of multi-data DS instructions (PR #156420)

https://github.com/rampitec edited https://github.com/llvm/llvm-project/pull/156420 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Add agpr variants of multi-data DS instructions (PR #156420)

https://github.com/rampitec approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/156420 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [ARM] Remove most post-decoding instruction adjustments (PR #156540)

https://github.com/s-barannikov created https://github.com/llvm/llvm-project/pull/156540 None >From 8b97be91ca096874b6fb44e8e48566631d4d0735 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Tue, 2 Sep 2025 10:26:16 +0300 Subject: [PATCH] [ARM] Remove most post-decoding instruction adjust

[llvm-branch-commits] [llvm] [ARM] Remove most post-decoding instruction adjustments (PR #156540)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/156540 >From 8e6e8dd7ff743523e55c7d3bb60c0f521980d6d0 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Tue, 2 Sep 2025 10:26:16 +0300 Subject: [PATCH] [ARM] Remove most post-decoding instruction adjustments

[llvm-branch-commits] [llvm] AMDGPU: Fix DPP combiner using isOperandLegal on incomplete inst (PR #155595)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/155595 >From a6e2e0d83c2724f04313372df0deda5d1f889ed6 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 27 Aug 2025 19:39:38 +0900 Subject: [PATCH 1/2] AMDGPU: Fix DPP combiner using isOperandLegal on incomplete

[llvm-branch-commits] [libcxx] release/21.x: [libc++][AIX] Fixup problems with ABI list checking (#155643) (PR #156502)

https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/156502 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Add agpr variants of multi-data DS instructions (PR #156420)

@@ -1510,16 +1549,16 @@ defm DS_WRXCHG2ST64_RTN_B64 : DS_Real_gfx11_gfx12<0x06f, "ds_storexchg_2addr_str defm DS_READ_B64: DS_Real_gfx11_gfx12<0x076, "ds_load_b64">; defm DS_READ2_B64 : DS_Real_gfx11_gfx12<0x077, "ds_load_2addr_b64">; defm DS_READ2ST64_B6

[llvm-branch-commits] [llvm] Add deactivation symbol operand to ConstantPtrAuth. (PR #133537)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133537 >From e728f3444624a5f47f0af84c21fb3a584f3e05b7 Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Fri, 1 Aug 2025 17:27:41 -0700 Subject: [PATCH] Add verifier check Created using spr 1.3.6-beta.1 --- llvm/lib

[llvm-branch-commits] CodeGen: Optionally emit PAuth relocations as IRELATIVE relocations. (PR #133533)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133533 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] Add IR and codegen support for deactivation symbols. (PR #133536)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133536 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] Add IR and codegen support for deactivation symbols. (PR #133536)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133536 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Refactor isImmOperandLegal (PR #155607)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/155607 >From 2ee13abfc257a65f5723039c3419371a6cb50ad6 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 27 Aug 2025 15:35:53 +0900 Subject: [PATCH] AMDGPU: Refactor isImmOperandLegal The goal is to expose more v

[llvm-branch-commits] [llvm] AMDGPU: Fix DPP combiner using isOperandLegal on incomplete inst (PR #155595)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/155595 >From 814ecb8e45394a379adff0a992fa989476145fee Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 27 Aug 2025 19:39:38 +0900 Subject: [PATCH 1/2] AMDGPU: Fix DPP combiner using isOperandLegal on incomplete

[llvm-branch-commits] [llvm] AMDGPU: Fix fixme for out of bounds indexing in usesConstantBus check (PR #155603)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/155603 >From a5a742a691fba41cf607a0ce20382a20d8719777 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 27 Aug 2025 16:19:23 +0900 Subject: [PATCH 1/2] AMDGPU: Fix fixme for out of bounds indexing in usesConstan

[llvm-branch-commits] [llvm] AMDGPU: Fold 64-bit immediate into copy to AV class (PR #155615)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/155615 >From 8961a0c7eb2c5fc7f93ad2d79e8dd2b6b3eab03a Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 26 Aug 2025 23:53:57 +0900 Subject: [PATCH] AMDGPU: Fold 64-bit immediate into copy to AV class This is in

[llvm-branch-commits] [llvm] AMDGPU: Fix DPP combiner using isOperandLegal on incomplete inst (PR #155595)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/155595 >From 814ecb8e45394a379adff0a992fa989476145fee Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 27 Aug 2025 19:39:38 +0900 Subject: [PATCH 1/2] AMDGPU: Fix DPP combiner using isOperandLegal on incomplete

[llvm-branch-commits] [llvm] AMDGPU: Add version of isImmOperandLegal for MCInstrDesc (PR #155560)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/155560 >From f1272175f9c0f695e7c3182ddebd0a1fa03b5cc0 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 27 Aug 2025 15:17:00 +0900 Subject: [PATCH] AMDGPU: Add version of isImmOperandLegal for MCInstrDesc This a

[llvm-branch-commits] [llvm] AMDGPU: Refactor isImmOperandLegal (PR #155607)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/155607 >From 96904665ffd481eab0087e1a7c2edcc6ef0bb915 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 27 Aug 2025 15:35:53 +0900 Subject: [PATCH] AMDGPU: Refactor isImmOperandLegal The goal is to expose more v

[llvm-branch-commits] [llvm] AMDGPU: Add version of isImmOperandLegal for MCInstrDesc (PR #155560)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/155560 >From f1272175f9c0f695e7c3182ddebd0a1fa03b5cc0 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 27 Aug 2025 15:17:00 +0900 Subject: [PATCH] AMDGPU: Add version of isImmOperandLegal for MCInstrDesc This a

[llvm-branch-commits] [llvm] AMDGPU: Handle true16 disassembly of ds_write_b8/b16 (PR #156406)

https://github.com/arsenm closed https://github.com/llvm/llvm-project/pull/156406 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [LifetimeSafety] Mark all DeclRefExpr as usages of the corresp. origin (PR #154316)

https://github.com/usx95 updated https://github.com/llvm/llvm-project/pull/154316 >From 3d27d8f76b16174d9805dc11592f4bb488585644 Mon Sep 17 00:00:00 2001 From: Utkarsh Saxena Date: Tue, 19 Aug 2025 12:00:53 + Subject: [PATCH] Identify DeclRefExpr as a use of an origin --- clang/lib/Analys

[llvm-branch-commits] [llvm] [AArch64] Remove post-decoding instruction mutations (PR #156364)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/156364 >From 098f8871d685efa2584b5cf09f3bd2bf26504c15 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Mon, 1 Sep 2025 20:30:01 +0300 Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations Th

[llvm-branch-commits] [llvm] [AArch64] Correctly disassemble TSB instruction (PR #156362)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/156362 >From f7326baa3158219a469914736abdad645631cab4 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Mon, 1 Sep 2025 20:22:53 +0300 Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction TSB ins

[llvm-branch-commits] [llvm] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA (PR #156363)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/156363 >From 71128901168ab0fc338c45a3484ec1bf57570ac0 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Mon, 1 Sep 2025 20:27:48 +0300 Subject: [PATCH] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA Th

[llvm-branch-commits] [llvm] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA (PR #156363)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/156363 >From 71128901168ab0fc338c45a3484ec1bf57570ac0 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Mon, 1 Sep 2025 20:27:48 +0300 Subject: [PATCH] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA Th

[llvm-branch-commits] [llvm] [AArch64] Correctly disassemble TSB instruction (PR #156362)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/156362 >From f7326baa3158219a469914736abdad645631cab4 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Mon, 1 Sep 2025 20:22:53 +0300 Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction TSB ins

[llvm-branch-commits] [llvm] [Hexagon] Remove post-decoding instruction adjustments (PR #156359)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/156359 >From b48ce40ecfc85e67b35e7521bf4e185e5471761c Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Mon, 1 Sep 2025 20:16:14 +0300 Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments

[llvm-branch-commits] Frontend: Adopt llvm::vfs::OutputBackend in CompilerInstance (PR #113364)

aganea wrote: This seems good, perhaps after https://github.com/llvm/llvm-project/pull/113363 lands, it'd be interesting to rebase and run some build-time tests, just to ensure it doesn't introduce regressions. https://github.com/llvm/llvm-project/pull/113364 __

[llvm-branch-commits] [llvm] AMDGPU: Fix fixme for out of bounds indexing in usesConstantBus check (PR #155603)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/155603 >From a5a742a691fba41cf607a0ce20382a20d8719777 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 27 Aug 2025 16:19:23 +0900 Subject: [PATCH 1/2] AMDGPU: Fix fixme for out of bounds indexing in usesConstan

[llvm-branch-commits] [llvm] [LoongArch] Use xvperm.w for cross-lane access within a single vector (PR #151634)

@@ -1832,6 +1832,48 @@ static SDValue lowerVECTOR_SHUFFLE_XVSHUF4I(const SDLoc &DL, ArrayRef Mask, return lowerVECTOR_SHUFFLE_VSHUF4I(DL, Mask, VT, V1, V2, DAG); } +/// Lower VECTOR_SHUFFLE into XVPERM (if possible). +static SDValue lowerVECTOR_SHUFFLE_XVPERM(const SDLoc &D

[llvm-branch-commits] [llvm] [LoongArch] Use xvperm.w for cross-lane access within a single vector (PR #151634)

@@ -1832,6 +1832,48 @@ static SDValue lowerVECTOR_SHUFFLE_XVSHUF4I(const SDLoc &DL, ArrayRef Mask, return lowerVECTOR_SHUFFLE_VSHUF4I(DL, Mask, VT, V1, V2, DAG); } +/// Lower VECTOR_SHUFFLE into XVPERM (if possible). +static SDValue lowerVECTOR_SHUFFLE_XVPERM(const SDLoc &D

[llvm-branch-commits] [llvm] AMDGPU: Fix true16 d16 entry table for DS pseudos (PR #156419)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/156419 This should be trying to use the _gfx9 variants of DS pseudos, not the base form with m0 uses. >From 849b10bdde864ad87389594fa063fcb8ea7a25ee Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 2 Sep 2025 1

[llvm-branch-commits] [llvm] AMDGPU: Fix true16 d16 entry table for DS pseudos (PR #156419)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156419?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Fix true16 d16 entry table for DS pseudos (PR #156419)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/156419 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Add agpr variants of multi-data DS instructions (PR #156420)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156420?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] [LoongArch] Use xvperm.w for cross-lane access within a single vector (PR #151634)

@@ -1832,6 +1832,48 @@ static SDValue lowerVECTOR_SHUFFLE_XVSHUF4I(const SDLoc &DL, ArrayRef Mask, return lowerVECTOR_SHUFFLE_VSHUF4I(DL, Mask, VT, V1, V2, DAG); } +/// Lower VECTOR_SHUFFLE into XVPERM (if possible). +static SDValue lowerVECTOR_SHUFFLE_XVPERM(const SDLoc &D

[llvm-branch-commits] [flang] [flang][OpenMP] Extend `do concurrent` mapping to device (PR #155987)

ergawy wrote: Ping! Please have a look when you have time. https://github.com/llvm/llvm-project/pull/155987 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Fix adding m0 uses to gfx94/gfx12 ds atomics (PR #156402)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/156402 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [LoongArch] Use xvperm.w for cross-lane access within a single vector (PR #151634)

@@ -1832,6 +1832,48 @@ static SDValue lowerVECTOR_SHUFFLE_XVSHUF4I(const SDLoc &DL, ArrayRef Mask, return lowerVECTOR_SHUFFLE_VSHUF4I(DL, Mask, VT, V1, V2, DAG); } +/// Lower VECTOR_SHUFFLE into XVPERM (if possible). +static SDValue lowerVECTOR_SHUFFLE_XVPERM(const SDLoc &D

[llvm-branch-commits] [mlir] [mlir][ptr] Add `gather`, `masked_load`, `masked_store`, and `scatter` ops (PR #156368)

@@ -56,6 +96,58 @@ def Ptr_FromPtrOp : Pointer_Op<"from_ptr", [ let hasVerifier = 1; } +//===--===// +// GatherOp +//===--===// + +def Ptr_

[llvm-branch-commits] [lld] ELF: Introduce R_AARCH64_FUNCINIT64 relocation type. (PR #133531)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133531 >From 96e7da9a083888683c2ba00d97f886fd748ea10b Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Wed, 9 Apr 2025 20:30:57 -0700 Subject: [PATCH 1/2] Undo unnecessary change Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [llvm] [AArch64] Remove post-decoding instruction mutations (PR #156364)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/156364 >From 098f8871d685efa2584b5cf09f3bd2bf26504c15 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Mon, 1 Sep 2025 20:30:01 +0300 Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations Th

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