https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From f7326baa3158219a469914736abdad645631cab4 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <baranniko...@gmail.com>
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB instruction has one operand, but the generated disassembler didn't
decode this operand. AArch64InstPrinter had a workaround for this.
This instruction can now be disassembled correctly.
---
llvm/lib/Target/AArch64/AArch64SystemOperands.td | 2 +-
llvm/lib/Target/AArch64/CMakeLists.txt | 3 +--
.../lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp | 7 -------
3 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 1b0e90b0e0dc3..65b752ed40c90 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -362,7 +362,7 @@ def lookupTSBByName : SearchIndex {
let Key = ["Name"];
}
-def : TSB<"csync", 0>;
+def : TSB<"csync", 2>;
//===----------------------------------------------------------------------===//
// PRFM (prefetch) instruction options.
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt
b/llvm/lib/Target/AArch64/CMakeLists.txt
index 833ce48ea1d7a..79b56ea9cf850 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -8,8 +8,7 @@ tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer
-asmwriternum=1)
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands
- -ignore-fully-defined-operands)
+ -ignore-non-decodable-operands)
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index 54b58e948daf2..2552ee3009338 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -365,13 +365,6 @@ void AArch64InstPrinter::printInst(const MCInst *MI,
uint64_t Address,
return;
}
- // Instruction TSB is specified as a one operand instruction, but 'csync' is
- // not encoded, so for printing it is treated as a special case here:
- if (Opcode == AArch64::TSB) {
- O << "\ttsb\tcsync";
- return;
- }
-
if (!PrintAliases || !printAliasInstr(MI, Address, STI, O))
printInstruction(MI, Address, STI, O);
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