[llvm-branch-commits] AlwaysInliner: A new inlining algorithm to interleave alloca promotion with inlines. (PR #145613)

aemerson wrote: > ⚠️ undef deprecator found issues in your code. ⚠️ This looks to be just the IR output containing undef, not the input. https://github.com/llvm/llvm-project/pull/145613 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.ll

[llvm-branch-commits] AlwaysInliner: A new inlining algorithm to interleave alloca promotion with inlines. (PR #145613)

aemerson wrote: I managed to reduce down the original SME test to `Transforms/PhaseOrdering/always-inline-alloca-promotion.ll`. Compiling that to assembly with clang with and without the change shows the differences in codegen quality, but the IR shows the kind of scenario this patch is meant

[llvm-branch-commits] AlwaysInliner: A new inlining algorithm to interleave alloca promotion with inlines. (PR #145613)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/145613 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] AlwaysInliner: A new inlining algorithm to interleave alloca promotion with inlines. (PR #145613)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/145613 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] AlwaysInliner: A new inlining algorithm to interleave alloca promotion with inlines. (PR #145613)

aemerson wrote: ping https://github.com/llvm/llvm-project/pull/145613 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] AlwaysInliner: A new inlining algorithm to interleave alloca promotion with inlines. (PR #145613)

https://github.com/aemerson edited https://github.com/llvm/llvm-project/pull/145613 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] AlwaysInliner: A new inlining algorithm to interleave alloca promotion with inlines. (PR #145613)

@@ -129,6 +147,245 @@ bool AlwaysInlineImpl( return Changed; } +/// Promote allocas to registers if possible. +static void promoteAllocas( +Function *Caller, SmallPtrSetImpl &AllocasToPromote, +function_ref &GetAssumptionCache) { + if (AllocasToPromote.empty()) +

[llvm-branch-commits] AlwaysInliner: A new inlining algorithm to interleave alloca promotion with inlines. (PR #145613)

@@ -129,6 +147,245 @@ bool AlwaysInlineImpl( return Changed; } +/// Promote allocas to registers if possible. +static void promoteAllocas( +Function *Caller, SmallPtrSetImpl &AllocasToPromote, +function_ref &GetAssumptionCache) { + if (AllocasToPromote.empty()) +

[llvm-branch-commits] AlwaysInliner: A new inlining algorithm to interleave alloca promotion with inlines. (PR #145613)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/145613 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] AlwaysInliner: A new inlining algorithm to interleave alloca promotion with inlines. (PR #145613)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/145613 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] AlwaysInliner: A new inlining algorithm to interleave alloca promotion with inlines. (PR #145613)

https://github.com/aemerson edited https://github.com/llvm/llvm-project/pull/145613 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] AlwaysInliner: A new inlining algorithm to interleave alloca promotion with inlines. (PR #145613)

@@ -129,6 +147,245 @@ bool AlwaysInlineImpl( return Changed; } +/// Promote allocas to registers if possible. +static void promoteAllocas( +Function *Caller, SmallPtrSetImpl &AllocasToPromote, +function_ref &GetAssumptionCache) { + if (AllocasToPromote.empty()) +

[llvm-branch-commits] [clang] release/20.x: [AArch64] Enable vscale_range with +sme (#124466) (PR #125386)

https://github.com/aemerson approved this pull request. https://github.com/llvm/llvm-project/pull/125386 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Add support for lowering trunc stores of vector bools. (PR #121169)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121169 >From a1c545bab55b0e9329044f469507149718a1d36f Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Thu, 26 Dec 2024 23:50:07 -0800 Subject: [PATCH 1/2] Add -aarch64-enable-collect-loh torun line to remove unnec

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Fix legalization for <4 x i1> vector stores. (PR #121185)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121185 >From 3efe80b9457a33c68362489fc8c946d51113856a Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Fri, 27 Dec 2024 00:06:30 -0800 Subject: [PATCH] Fix remark checks in test. Created using spr 1.3.5 --- .../AA

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Fix legalization for <4 x i1> vector stores. (PR #121185)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121185 >From 3efe80b9457a33c68362489fc8c946d51113856a Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Fri, 27 Dec 2024 00:06:30 -0800 Subject: [PATCH] Fix remark checks in test. Created using spr 1.3.5 --- .../AA

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Add support for lowering trunc stores of vector bools. (PR #121169)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121169 >From a1c545bab55b0e9329044f469507149718a1d36f Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Thu, 26 Dec 2024 23:50:07 -0800 Subject: [PATCH 1/2] Add -aarch64-enable-collect-loh torun line to remove unnec

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Fix legalization for <4 x i1> vector stores. (PR #121185)

aemerson wrote: > I think this sounds OK. LGTM > > (Which of bitcast or load/store is considered the most fundamental for > v4i1/v8i1? I think I would have expected in GISel the loads to be converted > to a i4/i8 load with bitcast, and the bitcast legalizes however it does. It > could obvious

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Legalize vector boolean bitcasts to scalars by lowering via stack. (PR #121171)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121171 >From 0be38ccf5c865b4fddc357b33c378c70a20532b9 Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Thu, 26 Dec 2024 16:13:55 -0800 Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20ch?= =?

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Add support for lowering trunc stores of vector bools. (PR #121169)

aemerson wrote: Ok, should be fixed now. The factoring out change is now in this PR where it belongs. https://github.com/llvm/llvm-project/pull/121169 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-b

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Fix legalization for <4 x i1> vector stores. (PR #121185)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121185 >From 3efe80b9457a33c68362489fc8c946d51113856a Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Fri, 27 Dec 2024 00:06:30 -0800 Subject: [PATCH] Fix remark checks in test. Created using spr 1.3.5 --- .../AA

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Fix legalization for <4 x i1> vector stores. (PR #121185)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121185 >From 3efe80b9457a33c68362489fc8c946d51113856a Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Fri, 27 Dec 2024 00:06:30 -0800 Subject: [PATCH] Fix remark checks in test. Created using spr 1.3.5 --- .../AA

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Add support for lowering trunc stores of vector bools. (PR #121169)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121169 >From a1c545bab55b0e9329044f469507149718a1d36f Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Thu, 26 Dec 2024 23:50:07 -0800 Subject: [PATCH 1/2] Add -aarch64-enable-collect-loh torun line to remove unnec

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Add support for lowering trunc stores of vector bools. (PR #121169)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121169 >From a1c545bab55b0e9329044f469507149718a1d36f Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Thu, 26 Dec 2024 23:50:07 -0800 Subject: [PATCH] Add -aarch64-enable-collect-loh torun line to remove unnecessa

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Fix legalization for <4 x i1> vector stores. (PR #121185)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121185 >From 3efe80b9457a33c68362489fc8c946d51113856a Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Fri, 27 Dec 2024 00:06:30 -0800 Subject: [PATCH] Fix remark checks in test. Created using spr 1.3.5 --- .../AA

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Fix legalization for <4 x i1> vector stores. (PR #121185)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121185 >From 3efe80b9457a33c68362489fc8c946d51113856a Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Fri, 27 Dec 2024 00:06:30 -0800 Subject: [PATCH] Fix remark checks in test. Created using spr 1.3.5 --- .../AA

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Add support for lowering trunc stores of vector bools. (PR #121169)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121169 >From a1c545bab55b0e9329044f469507149718a1d36f Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Thu, 26 Dec 2024 23:50:07 -0800 Subject: [PATCH] Add -aarch64-enable-collect-loh torun line to remove unnecessa

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Legalize vector boolean bitcasts to scalars by lowering via stack. (PR #121171)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121171 >From b9214baba592d4c7860d714b6d0dffd519a48400 Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Fri, 27 Dec 2024 17:34:25 -0800 Subject: [PATCH 1/2] Factor out into funct. Created using spr 1.3.5 --- .../ll

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Add support for lowering trunc stores of vector bools. (PR #121169)

aemerson wrote: Ehthe heck... I ended up somehow folding in the factoring out change from this PR into #121171 ... some weird `spr` bug? https://github.com/llvm/llvm-project/pull/121169 ___ llvm-branch-commits mailing list llvm-branch-commits@l

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Fix legalization for <4 x i1> vector stores. (PR #121185)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121185 >From 3efe80b9457a33c68362489fc8c946d51113856a Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Fri, 27 Dec 2024 00:06:30 -0800 Subject: [PATCH] Fix remark checks in test. Created using spr 1.3.5 --- .../AA

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Fix legalization for <4 x i1> vector stores. (PR #121185)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121185 >From 3efe80b9457a33c68362489fc8c946d51113856a Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Fri, 27 Dec 2024 00:06:30 -0800 Subject: [PATCH] Fix remark checks in test. Created using spr 1.3.5 --- .../AA

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Legalize vector boolean bitcasts to scalars by lowering via stack. (PR #121171)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121171 >From b9214baba592d4c7860d714b6d0dffd519a48400 Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Fri, 27 Dec 2024 17:34:25 -0800 Subject: [PATCH] Factor out into funct. Created using spr 1.3.5 --- .../llvm/C

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Add support for lowering trunc stores of vector bools. (PR #121169)

https://github.com/aemerson edited https://github.com/llvm/llvm-project/pull/121169 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Add support for lowering trunc stores of vector bools. (PR #121169)

@@ -4142,9 +4142,40 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerStore(GStore &StoreMI) { } if (MemTy.isVector()) { -// TODO: Handle vector trunc stores -if (MemTy != SrcTy) +LLT MemScalarTy = MemTy.getElementType(); +if (MemTy != SrcTy) { +

[llvm-branch-commits] [AArch64][GlobalISel] Legalize vector boolean bitcasts to scalars by lowering via stack. (PR #121171)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121171 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [AArch64][GlobalISel] Legalize vector boolean bitcasts to scalars by lowering via stack. (PR #121171)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121171 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Fix legalization for <4 x i1> vector stores. (PR #121185)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121185 >From 3efe80b9457a33c68362489fc8c946d51113856a Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Fri, 27 Dec 2024 00:06:30 -0800 Subject: [PATCH] Fix remark checks in test. Created using spr 1.3.5 --- .../AA

[llvm-branch-commits] [AArch64][GlobalISel] Fix legalization for <4 x i1> vector stores. (PR #121185)

aemerson wrote: Depends on #121169 https://github.com/llvm/llvm-project/pull/121185 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [AArch64][GlobalISel] Fix legalization for <4 x i1> vector stores. (PR #121185)

https://github.com/aemerson created https://github.com/llvm/llvm-project/pull/121185 This case is different from the earlier <8 x i1> case handled because it triggers a legalization failure in lowerStore() that's intended for scalar code. It also was triggering incorrect bitcast actions in the

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Add support for lowering trunc stores of vector bools. (PR #121169)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/121169 >From a1c545bab55b0e9329044f469507149718a1d36f Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Thu, 26 Dec 2024 23:50:07 -0800 Subject: [PATCH] Add -aarch64-enable-collect-loh torun line to remove unnecessa

[llvm-branch-commits] [AArch64][GlobalISel] Add support for lowering trunc stores of vector bools. (PR #121169)

aemerson wrote: Depends on #121171 https://github.com/llvm/llvm-project/pull/121169 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [AArch64][GlobalISel] Legalize vector boolean bitcasts to scalars by lowering via stack. (PR #121171)

aemerson wrote: Depends on #121170 https://github.com/llvm/llvm-project/pull/121171 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [AArch64][GlobalISel] Legalize vector boolean bitcasts to scalars by lowering via stack. (PR #121171)

https://github.com/aemerson created https://github.com/llvm/llvm-project/pull/121171 None ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [AArch64][GlobalISel] Add support for lowering trunc stores of vector bools. (PR #121169)

https://github.com/aemerson created https://github.com/llvm/llvm-project/pull/121169 This is essentially a port of TargetLowering::scalarizeVectorStore(), which is used for the case where we have something like a store of <8 x s8> truncating to <8 x s1> in memory. The naive lowering is a sequenc

[llvm-branch-commits] [llvm] GlobalISel: Fix combine duplicating atomic loads (PR #111730)

https://github.com/aemerson approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/111730 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [AArch64] Remove redundant COPY from loadRegFromStackSlot (#107396) (PR #107435)

aemerson wrote: To justify this for the 19 release: this is easily triggered by small IR so we should take this. https://github.com/llvm/llvm-project/pull/107435 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llv

[llvm-branch-commits] [llvm] release/19.x: [AArch64] Remove redundant COPY from loadRegFromStackSlot (#107396) (PR #107435)

https://github.com/aemerson approved this pull request. https://github.com/llvm/llvm-project/pull/107435 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AArch64] Disable SVE paired ld1/st1 for callee-saves. (PR #107406)

https://github.com/aemerson approved this pull request. https://github.com/llvm/llvm-project/pull/107406 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [AArch64][GlobalISel] Disable fixed-point iteration in all Combiners (PR #102167)

https://github.com/aemerson approved this pull request. These are some very nice improvements, thanks for working on this. None of the test output changes look to be exposing problems with this patch, so LGTM. https://github.com/llvm/llvm-project/pull/102167

[llvm-branch-commits] [GlobalISel] Combiner: Observer-based DCE and retrying of combines (PR #102163)

@@ -45,61 +45,189 @@ cl::OptionCategory GICombinerOptionCategory( ); } // end namespace llvm -/// This class acts as the glue the joins the CombinerHelper to the overall +/// This class acts as the glue that joins the CombinerHelper to the overall /// Combine algorithm. The C

[llvm-branch-commits] [GlobalISel] Combiner: Observer-based DCE and retrying of combines (PR #102163)

https://github.com/aemerson edited https://github.com/llvm/llvm-project/pull/102163 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [GlobalISel] Combiner: Observer-based DCE and retrying of combines (PR #102163)

https://github.com/aemerson approved this pull request. LGTM with nit. https://github.com/llvm/llvm-project/pull/102163 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-

[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT - manual merge (PR #91672)

aemerson wrote: @tstellar could we merge this now? https://github.com/llvm/llvm-project/pull/91672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT - manual merge (PR #91672)

https://github.com/aemerson milestoned https://github.com/llvm/llvm-project/pull/91672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT - manual merge (PR #91672)

aemerson wrote: Test has been changed from original commit due to a fallback in a G_BITCAST. Added abort=2 so we can see partial legalization and check no crash. https://github.com/llvm/llvm-project/pull/91672 ___ llvm-branch-commits mailing list llvm

[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT (PR #90827)

aemerson wrote: New PR: https://github.com/llvm/llvm-project/pull/91672 https://github.com/llvm/llvm-project/pull/90827 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-

[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT (PR #90827)

https://github.com/aemerson closed https://github.com/llvm/llvm-project/pull/90827 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT - manual merge (PR #91672)

https://github.com/aemerson ready_for_review https://github.com/llvm/llvm-project/pull/91672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT - manual merge (PR #91672)

https://github.com/aemerson edited https://github.com/llvm/llvm-project/pull/91672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT - manual merge (PR #91672)

https://github.com/aemerson edited https://github.com/llvm/llvm-project/pull/91672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT (PR #90827)

aemerson wrote: > @aemerson Did you submit a new pull request with a fix? I have not yet, will do so now... https://github.com/llvm/llvm-project/pull/90827 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/

[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT (PR #90827)

aemerson wrote: @nikic do you know the procedure here? https://github.com/llvm/llvm-project/pull/90827 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT (PR #90827)

aemerson wrote: @tstellar It looks like this cherry-pick has a test failure, what's the recommended way to resolve this? Make a new PR or modify this one (if that's possible?) https://github.com/llvm/llvm-project/pull/90827 ___ llvm-branch-commits ma

[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT (PR #90827)

https://github.com/aemerson approved this pull request. https://github.com/llvm/llvm-project/pull/90827 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [GlobalISel] Don't form anyextending atomic loads. (PR #90435)

https://github.com/aemerson approved this pull request. https://github.com/llvm/llvm-project/pull/90435 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [GlobalISel] Fix store merging incorrectly classifying an unknown index expr as 0. (#90375) (PR #90673)

https://github.com/aemerson approved this pull request. https://github.com/llvm/llvm-project/pull/90673 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [compiler-rt] [llvm] [clang] [GlobalISel] Always direct-call IFuncs and Aliases (PR #74902)

https://github.com/aemerson approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/74902 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] fa0971b - GlobalISel: check type size before getZExtValue()ing it.

Author: Tim Northover Date: 2021-04-09T11:19:39-07:00 New Revision: fa0971b87fb2c9d14d1bba2551e61f02f18f329b URL: https://github.com/llvm/llvm-project/commit/fa0971b87fb2c9d14d1bba2551e61f02f18f329b DIFF: https://github.com/llvm/llvm-project/commit/fa0971b87fb2c9d14d1bba2551e61f02f18f329b.diff

[llvm-branch-commits] [llvm] bd64ad3 - Recommit "[AArch64][GlobalISel] Make G_USUBO legal and select it."

Author: Cassie Jones Date: 2021-01-22T17:29:54-08:00 New Revision: bd64ad3fe17506933ac2971dcc900271d6ae5969 URL: https://github.com/llvm/llvm-project/commit/bd64ad3fe17506933ac2971dcc900271d6ae5969 DIFF: https://github.com/llvm/llvm-project/commit/bd64ad3fe17506933ac2971dcc900271d6ae5969.diff

[llvm-branch-commits] [llvm] 2bb92bf - [GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method

Author: Cassie Jones Date: 2021-01-22T14:08:46-08:00 New Revision: 2bb92bf451d7eb2c817f3e5403353e7c0c14d350 URL: https://github.com/llvm/llvm-project/commit/2bb92bf451d7eb2c817f3e5403353e7c0c14d350 DIFF: https://github.com/llvm/llvm-project/commit/2bb92bf451d7eb2c817f3e5403353e7c0c14d350.diff

[llvm-branch-commits] [llvm] 541d98e - [AArch64][GlobalISel] Implement widenScalar for signed overflow

Author: Cassie Jones Date: 2021-01-21T22:55:42-08:00 New Revision: 541d98efa222b00e16c67348810898c2fa11f398 URL: https://github.com/llvm/llvm-project/commit/541d98efa222b00e16c67348810898c2fa11f398 DIFF: https://github.com/llvm/llvm-project/commit/541d98efa222b00e16c67348810898c2fa11f398.diff

[llvm-branch-commits] [llvm] 3dedad4 - [AArch64][GlobalISel] Make G_USUBO legal and select it.

Author: Cassie Jones Date: 2021-01-21T18:53:33-08:00 New Revision: 3dedad475da45c05bc4f66cd14e9f44581edf0bc URL: https://github.com/llvm/llvm-project/commit/3dedad475da45c05bc4f66cd14e9f44581edf0bc DIFF: https://github.com/llvm/llvm-project/commit/3dedad475da45c05bc4f66cd14e9f44581edf0bc.diff

[llvm-branch-commits] [llvm] 8456c3a - AArch64: fix regression introduced by fcmp immediate selection.

Author: Amara Emerson Date: 2021-01-15T22:53:25-08:00 New Revision: 8456c3a789285079ad35d146e487436b5a27b027 URL: https://github.com/llvm/llvm-project/commit/8456c3a789285079ad35d146e487436b5a27b027 DIFF: https://github.com/llvm/llvm-project/commit/8456c3a789285079ad35d146e487436b5a27b027.diff

[llvm-branch-commits] [llvm] aa8a2d8 - [AArch64][GlobalISel] Select immediate fcmp if the zero is on the LHS.

Author: Amara Emerson Date: 2021-01-15T14:31:39-08:00 New Revision: aa8a2d8a3da3704f82ba4ea3a6e7b463737597e1 URL: https://github.com/llvm/llvm-project/commit/aa8a2d8a3da3704f82ba4ea3a6e7b463737597e1 DIFF: https://github.com/llvm/llvm-project/commit/aa8a2d8a3da3704f82ba4ea3a6e7b463737597e1.diff

[llvm-branch-commits] [llvm] 89e84de - [AArch64][GlobalISel] Fix fallbacks introduced for G_SITOFP in 8f283cafddfa8d6d01a94b48cdc5d25817569e91

Author: Amara Emerson Date: 2021-01-15T01:10:49-08:00 New Revision: 89e84dec1879417fb7eb96edaa55dac7eca204ab URL: https://github.com/llvm/llvm-project/commit/89e84dec1879417fb7eb96edaa55dac7eca204ab DIFF: https://github.com/llvm/llvm-project/commit/89e84dec1879417fb7eb96edaa55dac7eca204ab.diff

[llvm-branch-commits] [llvm] 8f283ca - [AArch64][GlobalISel] Add selection support for fpr bank source variants of G_SITOFP and G_UITOFP.

Author: Amara Emerson Date: 2021-01-14T19:31:19-08:00 New Revision: 8f283cafddfa8d6d01a94b48cdc5d25817569e91 URL: https://github.com/llvm/llvm-project/commit/8f283cafddfa8d6d01a94b48cdc5d25817569e91 DIFF: https://github.com/llvm/llvm-project/commit/8f283cafddfa8d6d01a94b48cdc5d25817569e91.diff

[llvm-branch-commits] [llvm] 036bc79 - [AArch64][GlobalISel] Assign FPR banks to loads which are used by integer->float conversions.

Author: Amara Emerson Date: 2021-01-14T16:33:34-08:00 New Revision: 036bc798f2ae4d266fe01e70778afe0b3381c088 URL: https://github.com/llvm/llvm-project/commit/036bc798f2ae4d266fe01e70778afe0b3381c088 DIFF: https://github.com/llvm/llvm-project/commit/036bc798f2ae4d266fe01e70778afe0b3381c088.diff

[llvm-branch-commits] [llvm] bc3606d - [AArch64][GlobalISel] Assign FPR banks to loads which are used by integer->float conversions.

Author: Amara Emerson Date: 2021-01-14T16:14:59-08:00 New Revision: bc3606d0b27b2ba13a826b5c3fcba81f7e737387 URL: https://github.com/llvm/llvm-project/commit/bc3606d0b27b2ba13a826b5c3fcba81f7e737387 DIFF: https://github.com/llvm/llvm-project/commit/bc3606d0b27b2ba13a826b5c3fcba81f7e737387.diff

[llvm-branch-commits] [llvm] a126569 - Fix failing triple test for macOS 11 with non-zero minor versions.

Author: Amara Emerson Date: 2021-01-06T14:57:37-08:00 New Revision: a1265690cf614bde8a7fd1d503c5f13c184dc786 URL: https://github.com/llvm/llvm-project/commit/a1265690cf614bde8a7fd1d503c5f13c184dc786 DIFF: https://github.com/llvm/llvm-project/commit/a1265690cf614bde8a7fd1d503c5f13c184dc786.diff

[llvm-branch-commits] [llvm] 7df3544 - [GlobalISel] Fix assertion failures after "GlobalISel: Return APInt from getConstantVRegVal" landed.

Author: Amara Emerson Date: 2020-12-26T23:51:44-08:00 New Revision: 7df3544e80fb40c742707613cd39ca77f7fea558 URL: https://github.com/llvm/llvm-project/commit/7df3544e80fb40c742707613cd39ca77f7fea558 DIFF: https://github.com/llvm/llvm-project/commit/7df3544e80fb40c742707613cd39ca77f7fea558.diff

[llvm-branch-commits] [llvm] e0721a0 - [AArch64][GlobalISel] Notify observer of mutated instruction for shift custom legalization.

Author: Amara Emerson Date: 2020-12-25T00:31:47-08:00 New Revision: e0721a0992288122d62940f622b4c2127098a2da URL: https://github.com/llvm/llvm-project/commit/e0721a0992288122d62940f622b4c2127098a2da DIFF: https://github.com/llvm/llvm-project/commit/e0721a0992288122d62940f622b4c2127098a2da.diff

[llvm-branch-commits] [llvm] 43ff75f - [AArch64][GlobalISel] Promote scalar G_SHL constant shift amounts to s64.

Author: Amara Emerson Date: 2020-12-18T11:57:38-08:00 New Revision: 43ff75f2c3feef64f9d73328230d34dac8832a91 URL: https://github.com/llvm/llvm-project/commit/43ff75f2c3feef64f9d73328230d34dac8832a91 DIFF: https://github.com/llvm/llvm-project/commit/43ff75f2c3feef64f9d73328230d34dac8832a91.diff

[llvm-branch-commits] [llvm] 9caca72 - [AArch64][GlobalISel] Use the look-through constant helper for the shift s32->s64 custom legalization.

Author: Amara Emerson Date: 2020-12-18T11:57:24-08:00 New Revision: 9caca7241d447266a23a99ea0536f30faaf19694 URL: https://github.com/llvm/llvm-project/commit/9caca7241d447266a23a99ea0536f30faaf19694 DIFF: https://github.com/llvm/llvm-project/commit/9caca7241d447266a23a99ea0536f30faaf19694.diff

[llvm-branch-commits] [llvm] a69b76c - [GlobalISel][IRTranslator] Ensure branch probabilities are added when translating invoke edges.

Author: Amara Emerson Date: 2020-12-14T23:36:54-08:00 New Revision: a69b76c500849bacc0ba494df03b465e4bcff0ef URL: https://github.com/llvm/llvm-project/commit/a69b76c500849bacc0ba494df03b465e4bcff0ef DIFF: https://github.com/llvm/llvm-project/commit/a69b76c500849bacc0ba494df03b465e4bcff0ef.diff

[llvm-branch-commits] [llvm] 21de99d - [[GlobalISel][IRTranslator] Fix a crash when the use of an extractvalue is a non-dominated metadata use.

Author: Amara Emerson Date: 2020-12-12T14:58:54-08:00 New Revision: 21de99d43c88c00c007a2b3e350d56328f26660e URL: https://github.com/llvm/llvm-project/commit/21de99d43c88c00c007a2b3e350d56328f26660e DIFF: https://github.com/llvm/llvm-project/commit/21de99d43c88c00c007a2b3e350d56328f26660e.diff

[llvm-branch-commits] [llvm] c29af37 - [AArch64] Don't try to compress jump tables if there are any inline asm instructions.

Author: Amara Emerson Date: 2020-12-10T12:20:02-08:00 New Revision: c29af37c6c9d74ca330bd7f1d084f1f676ba2824 URL: https://github.com/llvm/llvm-project/commit/c29af37c6c9d74ca330bd7f1d084f1f676ba2824 DIFF: https://github.com/llvm/llvm-project/commit/c29af37c6c9d74ca330bd7f1d084f1f676ba2824.diff

[llvm-branch-commits] [llvm] 2ac4d0f - [AArch64] Fix some minor coding style issues in AArch64CompressJumpTables

Author: Amara Emerson Date: 2020-12-07T12:48:09-08:00 New Revision: 2ac4d0f45a2a301163ca53f3e23e675f4f5bdbd3 URL: https://github.com/llvm/llvm-project/commit/2ac4d0f45a2a301163ca53f3e23e675f4f5bdbd3 DIFF: https://github.com/llvm/llvm-project/commit/2ac4d0f45a2a301163ca53f3e23e675f4f5bdbd3.diff

[llvm-branch-commits] [llvm] 87ff156 - [AArch64][GlobalISel] Fix crash during legalization of a vector G_SELECT with scalar mask.

Author: Amara Emerson Date: 2020-11-30T16:37:49-08:00 New Revision: 87ff156414370043cf149e0c77513c5227b336b1 URL: https://github.com/llvm/llvm-project/commit/87ff156414370043cf149e0c77513c5227b336b1 DIFF: https://github.com/llvm/llvm-project/commit/87ff156414370043cf149e0c77513c5227b336b1.diff

[llvm-branch-commits] [llvm] 4ab45cc - [AArch64][GlobalISel] Add some more legal types for G_PHI, G_IMPLICIT_DEF, G_FREEZE.

Author: Amara Emerson Date: 2020-09-30T17:25:33-07:00 New Revision: 4ab45cc2260d87f18e1b05517d5d366b2e754b72 URL: https://github.com/llvm/llvm-project/commit/4ab45cc2260d87f18e1b05517d5d366b2e754b72 DIFF: https://github.com/llvm/llvm-project/commit/4ab45cc2260d87f18e1b05517d5d366b2e754b72.diff