https://github.com/aemerson updated
https://github.com/llvm/llvm-project/pull/121169
>From a1c545bab55b0e9329044f469507149718a1d36f Mon Sep 17 00:00:00 2001
From: Amara Emerson <am...@apple.com>
Date: Thu, 26 Dec 2024 23:50:07 -0800
Subject: [PATCH 1/2] Add -aarch64-enable-collect-loh torun line to remove
unnecessary LOH labels.
Created using spr 1.3.5
---
.../AArch64/vec-combine-compare-to-bitmask.ll | 627 +++++-------------
1 file changed, 172 insertions(+), 455 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
b/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
index 496f7ebf300e50..1fa96979f45530 100644
--- a/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
+++ b/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 2
-; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon -verify-machineinstrs <
%s | FileCheck %s --check-prefixes=CHECK,SDAG
-; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon -global-isel
-global-isel-abort=2 -verify-machineinstrs < %s 2>&1 | FileCheck %s
--check-prefixes=CHECK,GISEL
+; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon
-aarch64-enable-collect-loh=false -verify-machineinstrs < %s | FileCheck %s
--check-prefixes=CHECK,SDAG
+; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon
-aarch64-enable-collect-loh=false -global-isel -global-isel-abort=2
-verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,GISEL
; Basic tests from input vector to bitmask
; IR generated from clang for:
@@ -26,10 +26,8 @@ define i16 @convert_to_bitmask16(<16 x i8> %vec) {
; Bits used in mask
; SDAG-LABEL: convert_to_bitmask16:
; SDAG: ; %bb.0:
-; SDAG-NEXT: Lloh0:
; SDAG-NEXT: adrp x8, lCPI0_0@PAGE
; SDAG-NEXT: cmeq.16b v0, v0, #0
-; SDAG-NEXT: Lloh1:
; SDAG-NEXT: ldr q1, [x8, lCPI0_0@PAGEOFF]
; SDAG-NEXT: bic.16b v0, v1, v0
; SDAG-NEXT: ext.16b v1, v0, v0, #8
@@ -37,7 +35,6 @@ define i16 @convert_to_bitmask16(<16 x i8> %vec) {
; SDAG-NEXT: addv.8h h0, v0
; SDAG-NEXT: fmov w0, s0
; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh0, Lloh1
;
; GISEL-LABEL: convert_to_bitmask16:
; GISEL: ; %bb.0:
@@ -106,17 +103,14 @@ define i16 @convert_to_bitmask16(<16 x i8> %vec) {
define i16 @convert_to_bitmask8(<8 x i16> %vec) {
; SDAG-LABEL: convert_to_bitmask8:
; SDAG: ; %bb.0:
-; SDAG-NEXT: Lloh2:
; SDAG-NEXT: adrp x8, lCPI1_0@PAGE
; SDAG-NEXT: cmeq.8h v0, v0, #0
-; SDAG-NEXT: Lloh3:
; SDAG-NEXT: ldr q1, [x8, lCPI1_0@PAGEOFF]
; SDAG-NEXT: bic.16b v0, v1, v0
; SDAG-NEXT: addv.8h h0, v0
; SDAG-NEXT: fmov w8, s0
; SDAG-NEXT: and w0, w8, #0xff
; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh2, Lloh3
;
; GISEL-LABEL: convert_to_bitmask8:
; GISEL: ; %bb.0:
@@ -160,31 +154,15 @@ define i16 @convert_to_bitmask8(<8 x i16> %vec) {
}
define i4 @convert_to_bitmask4(<4 x i32> %vec) {
-; SDAG-LABEL: convert_to_bitmask4:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: Lloh4:
-; SDAG-NEXT: adrp x8, lCPI2_0@PAGE
-; SDAG-NEXT: cmeq.4s v0, v0, #0
-; SDAG-NEXT: Lloh5:
-; SDAG-NEXT: ldr q1, [x8, lCPI2_0@PAGEOFF]
-; SDAG-NEXT: bic.16b v0, v1, v0
-; SDAG-NEXT: addv.4s s0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh4, Lloh5
-;
-; GISEL-LABEL: convert_to_bitmask4:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: Lloh0:
-; GISEL-NEXT: adrp x8, lCPI2_0@PAGE
-; GISEL-NEXT: cmeq.4s v0, v0, #0
-; GISEL-NEXT: Lloh1:
-; GISEL-NEXT: ldr q1, [x8, lCPI2_0@PAGEOFF]
-; GISEL-NEXT: bic.16b v0, v1, v0
-; GISEL-NEXT: addv.4s s0, v0
-; GISEL-NEXT: fmov w0, s0
-; GISEL-NEXT: ret
-; GISEL-NEXT: .loh AdrpLdr Lloh0, Lloh1
+; CHECK-LABEL: convert_to_bitmask4:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: adrp x8, lCPI2_0@PAGE
+; CHECK-NEXT: cmeq.4s v0, v0, #0
+; CHECK-NEXT: ldr q1, [x8, lCPI2_0@PAGEOFF]
+; CHECK-NEXT: bic.16b v0, v1, v0
+; CHECK-NEXT: addv.4s s0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%cmp_result = icmp ne <4 x i32> %vec, zeroinitializer
@@ -193,33 +171,16 @@ define i4 @convert_to_bitmask4(<4 x i32> %vec) {
}
define i8 @convert_to_bitmask2(<2 x i64> %vec) {
-; SDAG-LABEL: convert_to_bitmask2:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: Lloh6:
-; SDAG-NEXT: adrp x8, lCPI3_0@PAGE
-; SDAG-NEXT: cmeq.2d v0, v0, #0
-; SDAG-NEXT: Lloh7:
-; SDAG-NEXT: ldr q1, [x8, lCPI3_0@PAGEOFF]
-; SDAG-NEXT: bic.16b v0, v1, v0
-; SDAG-NEXT: addp.2d d0, v0
-; SDAG-NEXT: fmov w8, s0
-; SDAG-NEXT: and w0, w8, #0x3
-; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh6, Lloh7
-;
-; GISEL-LABEL: convert_to_bitmask2:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: Lloh2:
-; GISEL-NEXT: adrp x8, lCPI3_0@PAGE
-; GISEL-NEXT: cmeq.2d v0, v0, #0
-; GISEL-NEXT: Lloh3:
-; GISEL-NEXT: ldr q1, [x8, lCPI3_0@PAGEOFF]
-; GISEL-NEXT: bic.16b v0, v1, v0
-; GISEL-NEXT: addp.2d d0, v0
-; GISEL-NEXT: fmov w8, s0
-; GISEL-NEXT: and w0, w8, #0x3
-; GISEL-NEXT: ret
-; GISEL-NEXT: .loh AdrpLdr Lloh2, Lloh3
+; CHECK-LABEL: convert_to_bitmask2:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: adrp x8, lCPI3_0@PAGE
+; CHECK-NEXT: cmeq.2d v0, v0, #0
+; CHECK-NEXT: ldr q1, [x8, lCPI3_0@PAGEOFF]
+; CHECK-NEXT: bic.16b v0, v1, v0
+; CHECK-NEXT: addp.2d d0, v0
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: and w0, w8, #0x3
+; CHECK-NEXT: ret
%cmp_result = icmp ne <2 x i64> %vec, zeroinitializer
@@ -230,31 +191,15 @@ define i8 @convert_to_bitmask2(<2 x i64> %vec) {
; Clang's __builtin_convertvector adds an undef vector concat for vectors with
<8 elements.
define i8 @clang_builtins_undef_concat_convert_to_bitmask4(<4 x i32> %vec) {
-; SDAG-LABEL: clang_builtins_undef_concat_convert_to_bitmask4:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: Lloh8:
-; SDAG-NEXT: adrp x8, lCPI4_0@PAGE
-; SDAG-NEXT: cmeq.4s v0, v0, #0
-; SDAG-NEXT: Lloh9:
-; SDAG-NEXT: ldr q1, [x8, lCPI4_0@PAGEOFF]
-; SDAG-NEXT: bic.16b v0, v1, v0
-; SDAG-NEXT: addv.4s s0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh8, Lloh9
-;
-; GISEL-LABEL: clang_builtins_undef_concat_convert_to_bitmask4:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: Lloh4:
-; GISEL-NEXT: adrp x8, lCPI4_0@PAGE
-; GISEL-NEXT: cmeq.4s v0, v0, #0
-; GISEL-NEXT: Lloh5:
-; GISEL-NEXT: ldr q1, [x8, lCPI4_0@PAGEOFF]
-; GISEL-NEXT: bic.16b v0, v1, v0
-; GISEL-NEXT: addv.4s s0, v0
-; GISEL-NEXT: fmov w0, s0
-; GISEL-NEXT: ret
-; GISEL-NEXT: .loh AdrpLdr Lloh4, Lloh5
+; CHECK-LABEL: clang_builtins_undef_concat_convert_to_bitmask4:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: adrp x8, lCPI4_0@PAGE
+; CHECK-NEXT: cmeq.4s v0, v0, #0
+; CHECK-NEXT: ldr q1, [x8, lCPI4_0@PAGEOFF]
+; CHECK-NEXT: bic.16b v0, v1, v0
+; CHECK-NEXT: addv.4s s0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%cmp_result = icmp ne <4 x i32> %vec, zeroinitializer
@@ -265,35 +210,17 @@ define i8
@clang_builtins_undef_concat_convert_to_bitmask4(<4 x i32> %vec) {
define i4 @convert_to_bitmask_no_compare(<4 x i32> %vec1, <4 x i32> %vec2) {
-; SDAG-LABEL: convert_to_bitmask_no_compare:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: and.16b v0, v0, v1
-; SDAG-NEXT: Lloh10:
-; SDAG-NEXT: adrp x8, lCPI5_0@PAGE
-; SDAG-NEXT: Lloh11:
-; SDAG-NEXT: ldr q1, [x8, lCPI5_0@PAGEOFF]
-; SDAG-NEXT: shl.4s v0, v0, #31
-; SDAG-NEXT: cmlt.4s v0, v0, #0
-; SDAG-NEXT: and.16b v0, v0, v1
-; SDAG-NEXT: addv.4s s0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh10, Lloh11
-;
-; GISEL-LABEL: convert_to_bitmask_no_compare:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: and.16b v0, v0, v1
-; GISEL-NEXT: Lloh6:
-; GISEL-NEXT: adrp x8, lCPI5_0@PAGE
-; GISEL-NEXT: Lloh7:
-; GISEL-NEXT: ldr q1, [x8, lCPI5_0@PAGEOFF]
-; GISEL-NEXT: shl.4s v0, v0, #31
-; GISEL-NEXT: cmlt.4s v0, v0, #0
-; GISEL-NEXT: and.16b v0, v0, v1
-; GISEL-NEXT: addv.4s s0, v0
-; GISEL-NEXT: fmov w0, s0
-; GISEL-NEXT: ret
-; GISEL-NEXT: .loh AdrpLdr Lloh6, Lloh7
+; CHECK-LABEL: convert_to_bitmask_no_compare:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: and.16b v0, v0, v1
+; CHECK-NEXT: adrp x8, lCPI5_0@PAGE
+; CHECK-NEXT: ldr q1, [x8, lCPI5_0@PAGEOFF]
+; CHECK-NEXT: shl.4s v0, v0, #31
+; CHECK-NEXT: cmlt.4s v0, v0, #0
+; CHECK-NEXT: and.16b v0, v0, v1
+; CHECK-NEXT: addv.4s s0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%cmp = and <4 x i32> %vec1, %vec2
@@ -303,35 +230,17 @@ define i4 @convert_to_bitmask_no_compare(<4 x i32> %vec1,
<4 x i32> %vec2) {
}
define i4 @convert_to_bitmask_with_compare_chain(<4 x i32> %vec1, <4 x i32>
%vec2) {
-; SDAG-LABEL: convert_to_bitmask_with_compare_chain:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: cmeq.4s v2, v0, #0
-; SDAG-NEXT: cmeq.4s v0, v0, v1
-; SDAG-NEXT: Lloh12:
-; SDAG-NEXT: adrp x8, lCPI6_0@PAGE
-; SDAG-NEXT: Lloh13:
-; SDAG-NEXT: ldr q1, [x8, lCPI6_0@PAGEOFF]
-; SDAG-NEXT: bic.16b v0, v0, v2
-; SDAG-NEXT: and.16b v0, v0, v1
-; SDAG-NEXT: addv.4s s0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh12, Lloh13
-;
-; GISEL-LABEL: convert_to_bitmask_with_compare_chain:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: cmeq.4s v2, v0, #0
-; GISEL-NEXT: cmeq.4s v0, v0, v1
-; GISEL-NEXT: Lloh8:
-; GISEL-NEXT: adrp x8, lCPI6_0@PAGE
-; GISEL-NEXT: Lloh9:
-; GISEL-NEXT: ldr q1, [x8, lCPI6_0@PAGEOFF]
-; GISEL-NEXT: bic.16b v0, v0, v2
-; GISEL-NEXT: and.16b v0, v0, v1
-; GISEL-NEXT: addv.4s s0, v0
-; GISEL-NEXT: fmov w0, s0
-; GISEL-NEXT: ret
-; GISEL-NEXT: .loh AdrpLdr Lloh8, Lloh9
+; CHECK-LABEL: convert_to_bitmask_with_compare_chain:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: cmeq.4s v2, v0, #0
+; CHECK-NEXT: cmeq.4s v0, v0, v1
+; CHECK-NEXT: adrp x8, lCPI6_0@PAGE
+; CHECK-NEXT: ldr q1, [x8, lCPI6_0@PAGEOFF]
+; CHECK-NEXT: bic.16b v0, v0, v2
+; CHECK-NEXT: and.16b v0, v0, v1
+; CHECK-NEXT: addv.4s s0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer
@@ -342,37 +251,18 @@ define i4 @convert_to_bitmask_with_compare_chain(<4 x
i32> %vec1, <4 x i32> %vec
}
define i4 @convert_to_bitmask_with_trunc_in_chain(<4 x i32> %vec1, <4 x i32>
%vec2) {
-; SDAG-LABEL: convert_to_bitmask_with_trunc_in_chain:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: cmeq.4s v0, v0, #0
-; SDAG-NEXT: Lloh14:
-; SDAG-NEXT: adrp x8, lCPI7_0@PAGE
-; SDAG-NEXT: bic.16b v0, v1, v0
-; SDAG-NEXT: Lloh15:
-; SDAG-NEXT: ldr q1, [x8, lCPI7_0@PAGEOFF]
-; SDAG-NEXT: shl.4s v0, v0, #31
-; SDAG-NEXT: cmlt.4s v0, v0, #0
-; SDAG-NEXT: and.16b v0, v0, v1
-; SDAG-NEXT: addv.4s s0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh14, Lloh15
-;
-; GISEL-LABEL: convert_to_bitmask_with_trunc_in_chain:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: cmeq.4s v0, v0, #0
-; GISEL-NEXT: Lloh10:
-; GISEL-NEXT: adrp x8, lCPI7_0@PAGE
-; GISEL-NEXT: bic.16b v0, v1, v0
-; GISEL-NEXT: Lloh11:
-; GISEL-NEXT: ldr q1, [x8, lCPI7_0@PAGEOFF]
-; GISEL-NEXT: shl.4s v0, v0, #31
-; GISEL-NEXT: cmlt.4s v0, v0, #0
-; GISEL-NEXT: and.16b v0, v0, v1
-; GISEL-NEXT: addv.4s s0, v0
-; GISEL-NEXT: fmov w0, s0
-; GISEL-NEXT: ret
-; GISEL-NEXT: .loh AdrpLdr Lloh10, Lloh11
+; CHECK-LABEL: convert_to_bitmask_with_trunc_in_chain:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: cmeq.4s v0, v0, #0
+; CHECK-NEXT: adrp x8, lCPI7_0@PAGE
+; CHECK-NEXT: bic.16b v0, v1, v0
+; CHECK-NEXT: ldr q1, [x8, lCPI7_0@PAGEOFF]
+; CHECK-NEXT: shl.4s v0, v0, #31
+; CHECK-NEXT: cmlt.4s v0, v0, #0
+; CHECK-NEXT: and.16b v0, v0, v1
+; CHECK-NEXT: addv.4s s0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer
@@ -383,61 +273,30 @@ define i4 @convert_to_bitmask_with_trunc_in_chain(<4 x
i32> %vec1, <4 x i32> %ve
}
define i4 @convert_to_bitmask_with_unknown_type_in_long_chain(<4 x i32> %vec1,
<4 x i32> %vec2) {
-; SDAG-LABEL: convert_to_bitmask_with_unknown_type_in_long_chain:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: cmeq.4s v0, v0, #0
-; SDAG-NEXT: cmeq.4s v1, v1, #0
-; SDAG-NEXT: Lloh16:
-; SDAG-NEXT: adrp x8, lCPI8_0@PAGE
-; SDAG-NEXT: movi d2, #0x000000ffffffff
-; SDAG-NEXT: movi d3, #0x00ffffffffffff
-; SDAG-NEXT: bic.16b v0, v1, v0
-; SDAG-NEXT: movi d1, #0xffff0000ffff0000
-; SDAG-NEXT: xtn.4h v0, v0
-; SDAG-NEXT: orr.8b v0, v0, v2
-; SDAG-NEXT: movi d2, #0x00ffffffff0000
-; SDAG-NEXT: eor.8b v1, v0, v1
-; SDAG-NEXT: eor.8b v0, v0, v2
-; SDAG-NEXT: mov.h v1[2], wzr
-; SDAG-NEXT: orr.8b v0, v0, v3
-; SDAG-NEXT: orr.8b v0, v1, v0
-; SDAG-NEXT: Lloh17:
-; SDAG-NEXT: ldr d1, [x8, lCPI8_0@PAGEOFF]
-; SDAG-NEXT: shl.4h v0, v0, #15
-; SDAG-NEXT: cmlt.4h v0, v0, #0
-; SDAG-NEXT: and.8b v0, v0, v1
-; SDAG-NEXT: addv.4h h0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh16, Lloh17
-;
-; GISEL-LABEL: convert_to_bitmask_with_unknown_type_in_long_chain:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: cmeq.4s v0, v0, #0
-; GISEL-NEXT: cmeq.4s v1, v1, #0
-; GISEL-NEXT: Lloh12:
-; GISEL-NEXT: adrp x8, lCPI8_0@PAGE
-; GISEL-NEXT: movi d2, #0x000000ffffffff
-; GISEL-NEXT: movi d3, #0x00ffffffffffff
-; GISEL-NEXT: bic.16b v0, v1, v0
-; GISEL-NEXT: movi d1, #0xffff0000ffff0000
-; GISEL-NEXT: xtn.4h v0, v0
-; GISEL-NEXT: orr.8b v0, v0, v2
-; GISEL-NEXT: movi d2, #0x00ffffffff0000
-; GISEL-NEXT: eor.8b v1, v0, v1
-; GISEL-NEXT: eor.8b v0, v0, v2
-; GISEL-NEXT: mov.h v1[2], wzr
-; GISEL-NEXT: orr.8b v0, v0, v3
-; GISEL-NEXT: orr.8b v0, v1, v0
-; GISEL-NEXT: Lloh13:
-; GISEL-NEXT: ldr d1, [x8, lCPI8_0@PAGEOFF]
-; GISEL-NEXT: shl.4h v0, v0, #15
-; GISEL-NEXT: cmlt.4h v0, v0, #0
-; GISEL-NEXT: and.8b v0, v0, v1
-; GISEL-NEXT: addv.4h h0, v0
-; GISEL-NEXT: fmov w0, s0
-; GISEL-NEXT: ret
-; GISEL-NEXT: .loh AdrpLdr Lloh12, Lloh13
+; CHECK-LABEL: convert_to_bitmask_with_unknown_type_in_long_chain:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: cmeq.4s v0, v0, #0
+; CHECK-NEXT: cmeq.4s v1, v1, #0
+; CHECK-NEXT: adrp x8, lCPI8_0@PAGE
+; CHECK-NEXT: movi d2, #0x000000ffffffff
+; CHECK-NEXT: movi d3, #0x00ffffffffffff
+; CHECK-NEXT: bic.16b v0, v1, v0
+; CHECK-NEXT: movi d1, #0xffff0000ffff0000
+; CHECK-NEXT: xtn.4h v0, v0
+; CHECK-NEXT: orr.8b v0, v0, v2
+; CHECK-NEXT: movi d2, #0x00ffffffff0000
+; CHECK-NEXT: eor.8b v1, v0, v1
+; CHECK-NEXT: eor.8b v0, v0, v2
+; CHECK-NEXT: mov.h v1[2], wzr
+; CHECK-NEXT: orr.8b v0, v0, v3
+; CHECK-NEXT: orr.8b v0, v1, v0
+; CHECK-NEXT: ldr d1, [x8, lCPI8_0@PAGEOFF]
+; CHECK-NEXT: shl.4h v0, v0, #15
+; CHECK-NEXT: cmlt.4h v0, v0, #0
+; CHECK-NEXT: and.8b v0, v0, v1
+; CHECK-NEXT: addv.4h h0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer
@@ -456,37 +315,18 @@ define i4
@convert_to_bitmask_with_unknown_type_in_long_chain(<4 x i32> %vec1, <
}
define i4 @convert_to_bitmask_with_different_types_in_chain(<4 x i16> %vec1,
<4 x i32> %vec2) {
-; SDAG-LABEL: convert_to_bitmask_with_different_types_in_chain:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: cmeq.4s v1, v1, #0
-; SDAG-NEXT: cmeq.4h v0, v0, #0
-; SDAG-NEXT: Lloh18:
-; SDAG-NEXT: adrp x8, lCPI9_0@PAGE
-; SDAG-NEXT: xtn.4h v1, v1
-; SDAG-NEXT: orn.8b v0, v1, v0
-; SDAG-NEXT: Lloh19:
-; SDAG-NEXT: ldr d1, [x8, lCPI9_0@PAGEOFF]
-; SDAG-NEXT: and.8b v0, v0, v1
-; SDAG-NEXT: addv.4h h0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh18, Lloh19
-;
-; GISEL-LABEL: convert_to_bitmask_with_different_types_in_chain:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: cmeq.4s v1, v1, #0
-; GISEL-NEXT: cmeq.4h v0, v0, #0
-; GISEL-NEXT: Lloh14:
-; GISEL-NEXT: adrp x8, lCPI9_0@PAGE
-; GISEL-NEXT: xtn.4h v1, v1
-; GISEL-NEXT: orn.8b v0, v1, v0
-; GISEL-NEXT: Lloh15:
-; GISEL-NEXT: ldr d1, [x8, lCPI9_0@PAGEOFF]
-; GISEL-NEXT: and.8b v0, v0, v1
-; GISEL-NEXT: addv.4h h0, v0
-; GISEL-NEXT: fmov w0, s0
-; GISEL-NEXT: ret
-; GISEL-NEXT: .loh AdrpLdr Lloh14, Lloh15
+; CHECK-LABEL: convert_to_bitmask_with_different_types_in_chain:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: cmeq.4s v1, v1, #0
+; CHECK-NEXT: cmeq.4h v0, v0, #0
+; CHECK-NEXT: adrp x8, lCPI9_0@PAGE
+; CHECK-NEXT: xtn.4h v1, v1
+; CHECK-NEXT: orn.8b v0, v1, v0
+; CHECK-NEXT: ldr d1, [x8, lCPI9_0@PAGEOFF]
+; CHECK-NEXT: and.8b v0, v0, v1
+; CHECK-NEXT: addv.4h h0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%cmp1 = icmp ne <4 x i16> %vec1, zeroinitializer
@@ -500,9 +340,7 @@ define i16 @convert_to_bitmask_without_knowing_type(<16 x
i1> %vec) {
; SDAG-LABEL: convert_to_bitmask_without_knowing_type:
; SDAG: ; %bb.0:
; SDAG-NEXT: shl.16b v0, v0, #7
-; SDAG-NEXT: Lloh20:
; SDAG-NEXT: adrp x8, lCPI10_0@PAGE
-; SDAG-NEXT: Lloh21:
; SDAG-NEXT: ldr q1, [x8, lCPI10_0@PAGEOFF]
; SDAG-NEXT: cmlt.16b v0, v0, #0
; SDAG-NEXT: and.16b v0, v0, v1
@@ -511,7 +349,6 @@ define i16 @convert_to_bitmask_without_knowing_type(<16 x
i1> %vec) {
; SDAG-NEXT: addv.8h h0, v0
; SDAG-NEXT: fmov w0, s0
; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh20, Lloh21
;
; GISEL-LABEL: convert_to_bitmask_without_knowing_type:
; GISEL: ; %bb.0:
@@ -573,31 +410,15 @@ define i16 @convert_to_bitmask_without_knowing_type(<16 x
i1> %vec) {
}
define i2 @convert_to_bitmask_2xi32(<2 x i32> %vec) {
-; SDAG-LABEL: convert_to_bitmask_2xi32:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: Lloh22:
-; SDAG-NEXT: adrp x8, lCPI11_0@PAGE
-; SDAG-NEXT: cmeq.2s v0, v0, #0
-; SDAG-NEXT: Lloh23:
-; SDAG-NEXT: ldr d1, [x8, lCPI11_0@PAGEOFF]
-; SDAG-NEXT: bic.8b v0, v1, v0
-; SDAG-NEXT: addp.2s v0, v0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh22, Lloh23
-;
-; GISEL-LABEL: convert_to_bitmask_2xi32:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: Lloh16:
-; GISEL-NEXT: adrp x8, lCPI11_0@PAGE
-; GISEL-NEXT: cmeq.2s v0, v0, #0
-; GISEL-NEXT: Lloh17:
-; GISEL-NEXT: ldr d1, [x8, lCPI11_0@PAGEOFF]
-; GISEL-NEXT: bic.8b v0, v1, v0
-; GISEL-NEXT: addp.2s v0, v0, v0
-; GISEL-NEXT: fmov w0, s0
-; GISEL-NEXT: ret
-; GISEL-NEXT: .loh AdrpLdr Lloh16, Lloh17
+; CHECK-LABEL: convert_to_bitmask_2xi32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: adrp x8, lCPI11_0@PAGE
+; CHECK-NEXT: cmeq.2s v0, v0, #0
+; CHECK-NEXT: ldr d1, [x8, lCPI11_0@PAGEOFF]
+; CHECK-NEXT: bic.8b v0, v1, v0
+; CHECK-NEXT: addp.2s v0, v0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%cmp_result = icmp ne <2 x i32> %vec, zeroinitializer
%bitmask = bitcast <2 x i1> %cmp_result to i2
@@ -605,33 +426,16 @@ define i2 @convert_to_bitmask_2xi32(<2 x i32> %vec) {
}
define i4 @convert_to_bitmask_4xi8(<4 x i8> %vec) {
-; SDAG-LABEL: convert_to_bitmask_4xi8:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: bic.4h v0, #255, lsl #8
-; SDAG-NEXT: Lloh24:
-; SDAG-NEXT: adrp x8, lCPI12_0@PAGE
-; SDAG-NEXT: Lloh25:
-; SDAG-NEXT: ldr d1, [x8, lCPI12_0@PAGEOFF]
-; SDAG-NEXT: cmeq.4h v0, v0, #0
-; SDAG-NEXT: bic.8b v0, v1, v0
-; SDAG-NEXT: addv.4h h0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh24, Lloh25
-;
-; GISEL-LABEL: convert_to_bitmask_4xi8:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: bic.4h v0, #255, lsl #8
-; GISEL-NEXT: Lloh18:
-; GISEL-NEXT: adrp x8, lCPI12_0@PAGE
-; GISEL-NEXT: Lloh19:
-; GISEL-NEXT: ldr d1, [x8, lCPI12_0@PAGEOFF]
-; GISEL-NEXT: cmeq.4h v0, v0, #0
-; GISEL-NEXT: bic.8b v0, v1, v0
-; GISEL-NEXT: addv.4h h0, v0
-; GISEL-NEXT: fmov w0, s0
-; GISEL-NEXT: ret
-; GISEL-NEXT: .loh AdrpLdr Lloh18, Lloh19
+; CHECK-LABEL: convert_to_bitmask_4xi8:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: bic.4h v0, #255, lsl #8
+; CHECK-NEXT: adrp x8, lCPI12_0@PAGE
+; CHECK-NEXT: ldr d1, [x8, lCPI12_0@PAGEOFF]
+; CHECK-NEXT: cmeq.4h v0, v0, #0
+; CHECK-NEXT: bic.8b v0, v1, v0
+; CHECK-NEXT: addv.4h h0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%cmp_result = icmp ne <4 x i8> %vec, zeroinitializer
%bitmask = bitcast <4 x i1> %cmp_result to i4
@@ -639,35 +443,17 @@ define i4 @convert_to_bitmask_4xi8(<4 x i8> %vec) {
}
define i8 @convert_to_bitmask_8xi2(<8 x i2> %vec) {
-; SDAG-LABEL: convert_to_bitmask_8xi2:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: movi.8b v1, #3
-; SDAG-NEXT: Lloh26:
-; SDAG-NEXT: adrp x8, lCPI13_0@PAGE
-; SDAG-NEXT: and.8b v0, v0, v1
-; SDAG-NEXT: Lloh27:
-; SDAG-NEXT: ldr d1, [x8, lCPI13_0@PAGEOFF]
-; SDAG-NEXT: cmeq.8b v0, v0, #0
-; SDAG-NEXT: bic.8b v0, v1, v0
-; SDAG-NEXT: addv.8b b0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh26, Lloh27
-;
-; GISEL-LABEL: convert_to_bitmask_8xi2:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: movi.8b v1, #3
-; GISEL-NEXT: Lloh20:
-; GISEL-NEXT: adrp x8, lCPI13_0@PAGE
-; GISEL-NEXT: and.8b v0, v0, v1
-; GISEL-NEXT: Lloh21:
-; GISEL-NEXT: ldr d1, [x8, lCPI13_0@PAGEOFF]
-; GISEL-NEXT: cmeq.8b v0, v0, #0
-; GISEL-NEXT: bic.8b v0, v1, v0
-; GISEL-NEXT: addv.8b b0, v0
-; GISEL-NEXT: fmov w0, s0
-; GISEL-NEXT: ret
-; GISEL-NEXT: .loh AdrpLdr Lloh20, Lloh21
+; CHECK-LABEL: convert_to_bitmask_8xi2:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: movi.8b v1, #3
+; CHECK-NEXT: adrp x8, lCPI13_0@PAGE
+; CHECK-NEXT: and.8b v0, v0, v1
+; CHECK-NEXT: ldr d1, [x8, lCPI13_0@PAGEOFF]
+; CHECK-NEXT: cmeq.8b v0, v0, #0
+; CHECK-NEXT: bic.8b v0, v1, v0
+; CHECK-NEXT: addv.8b b0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%cmp_result = icmp ne <8 x i2> %vec, zeroinitializer
%bitmask = bitcast <8 x i1> %cmp_result to i8
@@ -675,35 +461,17 @@ define i8 @convert_to_bitmask_8xi2(<8 x i2> %vec) {
}
define i4 @convert_to_bitmask_float(<4 x float> %vec) {
-; SDAG-LABEL: convert_to_bitmask_float:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: fcmgt.4s v1, v0, #0.0
-; SDAG-NEXT: fcmlt.4s v0, v0, #0.0
-; SDAG-NEXT: Lloh28:
-; SDAG-NEXT: adrp x8, lCPI14_0@PAGE
-; SDAG-NEXT: orr.16b v0, v0, v1
-; SDAG-NEXT: Lloh29:
-; SDAG-NEXT: ldr q1, [x8, lCPI14_0@PAGEOFF]
-; SDAG-NEXT: and.16b v0, v0, v1
-; SDAG-NEXT: addv.4s s0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh28, Lloh29
-;
-; GISEL-LABEL: convert_to_bitmask_float:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: fcmgt.4s v1, v0, #0.0
-; GISEL-NEXT: fcmlt.4s v0, v0, #0.0
-; GISEL-NEXT: Lloh22:
-; GISEL-NEXT: adrp x8, lCPI14_0@PAGE
-; GISEL-NEXT: orr.16b v0, v0, v1
-; GISEL-NEXT: Lloh23:
-; GISEL-NEXT: ldr q1, [x8, lCPI14_0@PAGEOFF]
-; GISEL-NEXT: and.16b v0, v0, v1
-; GISEL-NEXT: addv.4s s0, v0
-; GISEL-NEXT: fmov w0, s0
-; GISEL-NEXT: ret
-; GISEL-NEXT: .loh AdrpLdr Lloh22, Lloh23
+; CHECK-LABEL: convert_to_bitmask_float:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: fcmgt.4s v1, v0, #0.0
+; CHECK-NEXT: fcmlt.4s v0, v0, #0.0
+; CHECK-NEXT: adrp x8, lCPI14_0@PAGE
+; CHECK-NEXT: orr.16b v0, v0, v1
+; CHECK-NEXT: ldr q1, [x8, lCPI14_0@PAGEOFF]
+; CHECK-NEXT: and.16b v0, v0, v1
+; CHECK-NEXT: addv.4s s0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%cmp_result = fcmp one <4 x float> %vec, zeroinitializer
@@ -720,10 +488,8 @@ define i8 @convert_large_vector(<8 x i32> %vec) {
; SDAG-NEXT: .cfi_def_cfa_offset 16
; SDAG-NEXT: cmeq.4s v1, v1, #0
; SDAG-NEXT: cmeq.4s v0, v0, #0
-; SDAG-NEXT: Lloh30:
; SDAG-NEXT: adrp x8, lCPI15_0@PAGE
; SDAG-NEXT: uzp1.8h v0, v0, v1
-; SDAG-NEXT: Lloh31:
; SDAG-NEXT: ldr q1, [x8, lCPI15_0@PAGEOFF]
; SDAG-NEXT: bic.16b v0, v1, v0
; SDAG-NEXT: addv.8h h0, v0
@@ -731,7 +497,6 @@ define i8 @convert_large_vector(<8 x i32> %vec) {
; SDAG-NEXT: and w0, w8, #0xff
; SDAG-NEXT: add sp, sp, #16
; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh30, Lloh31
;
; GISEL-LABEL: convert_large_vector:
; GISEL: ; %bb.0:
@@ -777,35 +542,17 @@ define i8 @convert_large_vector(<8 x i32> %vec) {
}
define i4 @convert_legalized_illegal_element_size(<4 x i22> %vec) {
-; SDAG-LABEL: convert_legalized_illegal_element_size:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: movi.4s v1, #63, msl #16
-; SDAG-NEXT: Lloh32:
-; SDAG-NEXT: adrp x8, lCPI16_0@PAGE
-; SDAG-NEXT: cmtst.4s v0, v0, v1
-; SDAG-NEXT: Lloh33:
-; SDAG-NEXT: ldr d1, [x8, lCPI16_0@PAGEOFF]
-; SDAG-NEXT: xtn.4h v0, v0
-; SDAG-NEXT: and.8b v0, v0, v1
-; SDAG-NEXT: addv.4h h0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh32, Lloh33
-;
-; GISEL-LABEL: convert_legalized_illegal_element_size:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: movi.4s v1, #63, msl #16
-; GISEL-NEXT: Lloh24:
-; GISEL-NEXT: adrp x8, lCPI16_0@PAGE
-; GISEL-NEXT: cmtst.4s v0, v0, v1
-; GISEL-NEXT: Lloh25:
-; GISEL-NEXT: ldr d1, [x8, lCPI16_0@PAGEOFF]
-; GISEL-NEXT: xtn.4h v0, v0
-; GISEL-NEXT: and.8b v0, v0, v1
-; GISEL-NEXT: addv.4h h0, v0
-; GISEL-NEXT: fmov w0, s0
-; GISEL-NEXT: ret
-; GISEL-NEXT: .loh AdrpLdr Lloh24, Lloh25
+; CHECK-LABEL: convert_legalized_illegal_element_size:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: movi.4s v1, #63, msl #16
+; CHECK-NEXT: adrp x8, lCPI16_0@PAGE
+; CHECK-NEXT: cmtst.4s v0, v0, v1
+; CHECK-NEXT: ldr d1, [x8, lCPI16_0@PAGEOFF]
+; CHECK-NEXT: xtn.4h v0, v0
+; CHECK-NEXT: and.8b v0, v0, v1
+; CHECK-NEXT: addv.4h h0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%cmp_result = icmp ne <4 x i22> %vec, zeroinitializer
%bitmask = bitcast <4 x i1> %cmp_result to i4
@@ -814,53 +561,26 @@ define i4 @convert_legalized_illegal_element_size(<4 x
i22> %vec) {
; This may still be converted as a v8i8 after the vector concat (but not as
v4iX).
define i8 @no_direct_convert_for_bad_concat(<4 x i32> %vec) {
-; SDAG-LABEL: no_direct_convert_for_bad_concat:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: cmtst.4s v0, v0, v0
-; SDAG-NEXT: Lloh34:
-; SDAG-NEXT: adrp x8, lCPI17_0@PAGE
-; SDAG-NEXT: xtn.4h v0, v0
-; SDAG-NEXT: umov.h w9, v0[0]
-; SDAG-NEXT: mov.b v1[4], w9
-; SDAG-NEXT: umov.h w9, v0[1]
-; SDAG-NEXT: mov.b v1[5], w9
-; SDAG-NEXT: umov.h w9, v0[2]
-; SDAG-NEXT: mov.b v1[6], w9
-; SDAG-NEXT: umov.h w9, v0[3]
-; SDAG-NEXT: mov.b v1[7], w9
-; SDAG-NEXT: shl.8b v0, v1, #7
-; SDAG-NEXT: Lloh35:
-; SDAG-NEXT: ldr d1, [x8, lCPI17_0@PAGEOFF]
-; SDAG-NEXT: cmlt.8b v0, v0, #0
-; SDAG-NEXT: and.8b v0, v0, v1
-; SDAG-NEXT: addv.8b b0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh34, Lloh35
-;
-; GISEL-LABEL: no_direct_convert_for_bad_concat:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: cmtst.4s v0, v0, v0
-; GISEL-NEXT: Lloh26:
-; GISEL-NEXT: adrp x8, lCPI17_0@PAGE
-; GISEL-NEXT: xtn.4h v0, v0
-; GISEL-NEXT: umov.h w9, v0[0]
-; GISEL-NEXT: mov.b v1[4], w9
-; GISEL-NEXT: umov.h w9, v0[1]
-; GISEL-NEXT: mov.b v1[5], w9
-; GISEL-NEXT: umov.h w9, v0[2]
-; GISEL-NEXT: mov.b v1[6], w9
-; GISEL-NEXT: umov.h w9, v0[3]
-; GISEL-NEXT: mov.b v1[7], w9
-; GISEL-NEXT: shl.8b v0, v1, #7
-; GISEL-NEXT: Lloh27:
-; GISEL-NEXT: ldr d1, [x8, lCPI17_0@PAGEOFF]
-; GISEL-NEXT: cmlt.8b v0, v0, #0
-; GISEL-NEXT: and.8b v0, v0, v1
-; GISEL-NEXT: addv.8b b0, v0
-; GISEL-NEXT: fmov w0, s0
-; GISEL-NEXT: ret
-; GISEL-NEXT: .loh AdrpLdr Lloh26, Lloh27
+; CHECK-LABEL: no_direct_convert_for_bad_concat:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: cmtst.4s v0, v0, v0
+; CHECK-NEXT: adrp x8, lCPI17_0@PAGE
+; CHECK-NEXT: xtn.4h v0, v0
+; CHECK-NEXT: umov.h w9, v0[0]
+; CHECK-NEXT: mov.b v1[4], w9
+; CHECK-NEXT: umov.h w9, v0[1]
+; CHECK-NEXT: mov.b v1[5], w9
+; CHECK-NEXT: umov.h w9, v0[2]
+; CHECK-NEXT: mov.b v1[6], w9
+; CHECK-NEXT: umov.h w9, v0[3]
+; CHECK-NEXT: mov.b v1[7], w9
+; CHECK-NEXT: shl.8b v0, v1, #7
+; CHECK-NEXT: ldr d1, [x8, lCPI17_0@PAGEOFF]
+; CHECK-NEXT: cmlt.8b v0, v0, #0
+; CHECK-NEXT: and.8b v0, v0, v1
+; CHECK-NEXT: addv.8b b0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%cmp_result = icmp ne <4 x i32> %vec, zeroinitializer
%vector_pad = shufflevector <4 x i1> poison, <4 x i1> %cmp_result, <8 x i32>
<i32 undef, i32 undef, i32 undef, i32 undef, i32 4, i32 5, i32 6, i32 7>
@@ -929,9 +649,7 @@ define <2 x i8> @vector_to_vector_cast(<16 x i1> %arg)
nounwind {
; SDAG: ; %bb.0:
; SDAG-NEXT: sub sp, sp, #16
; SDAG-NEXT: shl.16b v0, v0, #7
-; SDAG-NEXT: Lloh36:
; SDAG-NEXT: adrp x8, lCPI20_0@PAGE
-; SDAG-NEXT: Lloh37:
; SDAG-NEXT: ldr q1, [x8, lCPI20_0@PAGEOFF]
; SDAG-NEXT: add x8, sp, #14
; SDAG-NEXT: cmlt.16b v0, v0, #0
@@ -946,7 +664,6 @@ define <2 x i8> @vector_to_vector_cast(<16 x i1> %arg)
nounwind {
; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0
; SDAG-NEXT: add sp, sp, #16
; SDAG-NEXT: ret
-; SDAG-NEXT: .loh AdrpLdr Lloh36, Lloh37
;
; GISEL-LABEL: vector_to_vector_cast:
; GISEL: ; %bb.0:
>From b6deb9aee8acb971d7a128823075186a50884983 Mon Sep 17 00:00:00 2001
From: Amara Emerson <am...@apple.com>
Date: Fri, 27 Dec 2024 21:00:22 -0800
Subject: [PATCH 2/2] Re-add removed test.
Created using spr 1.3.5
---
.../AArch64/GlobalISel/legalize-bitcast.mir | 70 +++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir
b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir
index e3a633c9e035d0..4d461c971d3320 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir
@@ -48,3 +48,73 @@ body: |
G_BR %bb.2
...
+---
+name: boolean_vector_to_scalar
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: boolean_vector_to_scalar
+ ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s8>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x
s8>), [[C]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s8)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x
s8>), [[C3]](s64)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC1]](s8)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x
s8>), [[C4]](s64)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC2]](s8)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C1]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C4]](s64)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x
s8>), [[C5]](s64)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC3]](s8)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C1]]
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C5]](s64)
+ ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x
s8>), [[C6]](s64)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC4]](s8)
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C1]]
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C6]](s64)
+ ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x
s8>), [[C7]](s64)
+ ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC5]](s8)
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C1]]
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C7]](s64)
+ ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x
s8>), [[C8]](s64)
+ ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC6]](s8)
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C1]]
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C8]](s64)
+ ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x
s8>), [[C9]](s64)
+ ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC7]](s8)
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C1]]
+ ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C9]](s64)
+ ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[OR7]](s32)
+ ; CHECK-NEXT: G_STORE [[TRUNC]](s8), [[FRAME_INDEX]](p0) :: (store (s8)
into %stack.0)
+ ; CHECK-NEXT: %bc:_(s8) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s8) from
%stack.0)
+ ; CHECK-NEXT: %ext:_(s32) = G_ANYEXT %bc(s8)
+ ; CHECK-NEXT: $w0 = COPY %ext(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
+ %vec:_(<8 x s1>) = G_IMPLICIT_DEF
+ %bc:_(s8) = G_BITCAST %vec(<8 x s1>)
+ %ext:_(s32) = G_ANYEXT %bc(s8)
+ $w0 = COPY %ext(s32)
+ RET_ReallyLR implicit $w0
+...
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