@@ -1144,42 +2872,116 @@ entry:
define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind {
; CHECK-ALIGNED-RV32-LABEL: memcmp_size_4:
; CHECK-ALIGNED-RV32: # %bb.0: # %entry
-; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16
-; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte
wangpc-pp wrote:
Ping, any comment for current scalar part? I'm working on vector expansion and
will post it in a few days.
https://github.com/llvm/llvm-project/pull/107548
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Author: c8ef
Date: 2024-11-01T09:25:43+08:00
New Revision: 8b1b4753ac16cba5a153536171a243d76300e4bb
URL:
https://github.com/llvm/llvm-project/commit/8b1b4753ac16cba5a153536171a243d76300e4bb
DIFF:
https://github.com/llvm/llvm-project/commit/8b1b4753ac16cba5a153536171a243d76300e4bb.diff
LOG: Rev
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/114438
>From d0ec41bcb8f0594b86336e45028d490dd4ebf6c4 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 31 Oct 2024 12:49:07 -0400
Subject: [PATCH] [WIP][AMDGPU][Attributor] Make `AAAMDWavesPerEU` honor
existing
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/114438
>From b48566210212165429e6a29665a4fefdf2695e61 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 31 Oct 2024 12:49:07 -0400
Subject: [PATCH] [WIP][AMDGPU][Attributor] Make `AAAMDWavesPerEU` honor
existing
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/114438
>From 25b1ec0e80072c70628da9d72be8969fd6bb3d87 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 31 Oct 2024 12:49:07 -0400
Subject: [PATCH] [WIP][AMDGPU][Attributor] Make `AAAMDWavesPerEU` honor
existing
@@ -424,6 +424,58 @@ AArch64RegisterInfo::explainReservedReg(const
MachineFunction &MF,
return {};
}
+static SmallVector ReservedHi = {
arsenm wrote:
This smells like an unrelated bug, this is not the kind of error I expected
https://github.com/llvm/llvm
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/114438
>From b7f1c2bd5d33a060ab2a8ee942874d208d42cac9 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 31 Oct 2024 12:49:07 -0400
Subject: [PATCH] [WIP][AMDGPU][Attributor] Make `AAAMDWavesPerEU` honor
existing
Author: gulfemsavrun
Date: 2024-10-31T13:19:56-07:00
New Revision: 4b61314fc83dfc9a8ec29dcc4c9ccfb0057b990a
URL:
https://github.com/llvm/llvm-project/commit/4b61314fc83dfc9a8ec29dcc4c9ccfb0057b990a
DIFF:
https://github.com/llvm/llvm-project/commit/4b61314fc83dfc9a8ec29dcc4c9ccfb0057b990a.diff
@@ -215,6 +215,19 @@ class AMDGPUInformationCache : public InformationCache {
return ST.getWavesPerEU(F, FlatWorkGroupSize);
}
+ std::optional>
+ getWavesPerEUAttr(const Function &F) {
+Attribute Attr = F.getFnAttribute("amdgpu-waves-per-eu");
+if (!Attr.isStri
@@ -215,6 +215,19 @@ class AMDGPUInformationCache : public InformationCache {
return ST.getWavesPerEU(F, FlatWorkGroupSize);
}
+ std::optional>
+ getWavesPerEUAttr(const Function &F) {
+Attribute Attr = F.getFnAttribute("amdgpu-waves-per-eu");
+if (!Attr.isStri
arsenm wrote:
### Merge activity
* **Oct 31, 2:43 PM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/109409).
https://github.com/llvm/llvm-project/pull/109409
_
@@ -404,21 +404,20 @@ attributes #19 = { "amdgpu-waves-per-eu"="8,9" }
; CHECK: attributes #[[ATTR2]] = { "amdgpu-flat-work-group-size"="1,64"
"amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue"
"amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-he
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/114438
>From 66264a1254c322fc0d3aa464125370886ad7da7c Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 31 Oct 2024 12:49:07 -0400
Subject: [PATCH] [WIP][AMDGPU][Attributor] Make `AAAMDWavesPerEU` honor
existing
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/114438
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@@ -404,21 +404,20 @@ attributes #19 = { "amdgpu-waves-per-eu"="8,9" }
; CHECK: attributes #[[ATTR2]] = { "amdgpu-flat-work-group-size"="1,64"
"amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue"
"amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-he
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Shilei Tian (shiltian)
Changes
---
Patch is 25.38 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/114438.diff
2 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUAttributor.
shiltian wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/114438?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/114438
None
>From 687d29af2f79b07cdc8b8b0044a8c1f828745cfd Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 31 Oct 2024 12:49:07 -0400
Subject: [PATCH] [WIP][AMDGPU][Attributor] Make `AAAMDWavesPerEU` honor
exi
@@ -424,6 +424,58 @@ AArch64RegisterInfo::explainReservedReg(const
MachineFunction &MF,
return {};
}
+static SmallVector ReservedHi = {
sdesmalen-arm wrote:
Without marking the registers as reserved, then for the example below:
```
---
name:sv2
Author: Mehdi Amini
Date: 2024-10-31T18:28:41+01:00
New Revision: d0422f6d72d84dbf78d248fa9665d2aaf50dd1fa
URL:
https://github.com/llvm/llvm-project/commit/d0422f6d72d84dbf78d248fa9665d2aaf50dd1fa
DIFF:
https://github.com/llvm/llvm-project/commit/d0422f6d72d84dbf78d248fa9665d2aaf50dd1fa.diff
L
@@ -424,6 +424,58 @@ AArch64RegisterInfo::explainReservedReg(const
MachineFunction &MF,
return {};
}
+static SmallVector ReservedHi = {
arsenm wrote:
But what are the actual failures, messages, location? If the high half of
register isn't allocatable / a
@@ -66,9 +73,215 @@ FunctionPass *llvm::createAMDGPURegBankSelectPass() {
return new AMDGPURegBankSelect();
}
+class RegBankSelectHelper {
+ MachineIRBuilder &B;
+ MachineRegisterInfo &MRI;
+ AMDGPU::IntrinsicLaneMaskAnalyzer &ILMA;
+ const MachineUniformityInfo &MUI;
+
@@ -424,6 +424,57 @@ AArch64RegisterInfo::explainReservedReg(const
MachineFunction &MF,
return {};
}
+static MCPhysReg ReservedHi[] = {
arsenm wrote:
missing const
https://github.com/llvm/llvm-project/pull/114263
_
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/109410
>From 834ff3b40bd82cb54bb33532a54ad36870ea2b24 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 14 Aug 2024 13:57:14 +0400
Subject: [PATCH 1/2] AMDGPU: Custom expand flat cmpxchg which may access
private
@@ -821,6 +826,152 @@ AAAMDFlatWorkGroupSize::createForPosition(const
IRPosition &IRP,
"AAAMDFlatWorkGroupSize is only valid for function position");
}
+struct TupleDecIntegerRangeState : public AbstractState {
+ DecIntegerState X, Y, Z;
+
+ bool isValidState() const
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From a269e8da1b872b3f2390037a594757940cf8369b Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/skatrak approved this pull request.
Ah, I see. Then this LGTM, thanks for explaining!
https://github.com/llvm/llvm-project/pull/113556
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@@ -424,6 +424,58 @@ AArch64RegisterInfo::explainReservedReg(const
MachineFunction &MF,
return {};
}
+static SmallVector ReservedHi = {
arsenm wrote:
What kind of failures? AMDGPU also has synthetic 16-bit high sub registers and
they are not explicitly re
https://github.com/NimishMishra approved this pull request.
This looks okay to me, given the PR stack.
There is still https://github.com/llvm/llvm-project/pull/113682 pending a
merge; I'll take a look at that PR tomorrow. Thanks for the work on this.
https://github.com/llvm/llvm-project/pull/1
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/114392
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https://github.com/skatrak updated
https://github.com/llvm/llvm-project/pull/113683
>From cf57ecd0984bcb2335e8ecfaffdca600a5c7cf1b Mon Sep 17 00:00:00 2001
From: Sergio Afonso
Date: Fri, 25 Oct 2024 12:07:22 +0100
Subject: [PATCH] Revert "[Flang][OpenMP] Disable lowering of omp.simd
reductions
arsenm wrote:
### Merge activity
* **Oct 31, 10:38 AM EDT**: A user started a stack merge that includes this
pull request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/111730).
https://github.com/llvm/llvm-project/pull/111730
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From eb6a8fc2973ad31f607af56c61a4c6ba6f30d982 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:37:59 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
@@ -294,7 +294,11 @@ class Triple {
PAuthTest,
-LastEnvironmentType = PAuthTest
+GNUT64,
+GNUEABIT64,
+GNUEABIHFT64,
+
+LastEnvironmentType = GNUEABIHFT64
tru wrote:
Let's continue the discussion and the next steps on discourse, I pos
@@ -294,7 +294,11 @@ class Triple {
PAuthTest,
-LastEnvironmentType = PAuthTest
+GNUT64,
+GNUEABIT64,
+GNUEABIHFT64,
+
+LastEnvironmentType = GNUEABIHFT64
tstellar wrote:
> This patch doesn't break ABI/API compatibility. The Zig check
@@ -66,9 +73,215 @@ FunctionPass *llvm::createAMDGPURegBankSelectPass() {
return new AMDGPURegBankSelect();
}
+class RegBankSelectHelper {
+ MachineIRBuilder &B;
+ MachineRegisterInfo &MRI;
+ AMDGPU::IntrinsicLaneMaskAnalyzer &ILMA;
+ const MachineUniformityInfo &MUI;
+
@@ -66,9 +73,215 @@ FunctionPass *llvm::createAMDGPURegBankSelectPass() {
return new AMDGPURegBankSelect();
}
+class RegBankSelectHelper {
+ MachineIRBuilder &B;
+ MachineRegisterInfo &MRI;
+ AMDGPU::IntrinsicLaneMaskAnalyzer &ILMA;
+ const MachineUniformityInfo &MUI;
+
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From 6ec049db2a5572c4cb0514b9ca44c7ff215b461f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From e6285ef8415e03337a080fa13456a2495023a8e6 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:37:59 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
https://github.com/agozillon updated
https://github.com/llvm/llvm-project/pull/113556
>From 70265b81b3e8ab7b6d04ed3d019861abd0b0e4aa Mon Sep 17 00:00:00 2001
From: agozillon
Date: Fri, 4 Oct 2024 13:03:22 -0500
Subject: [PATCH] [OpenMP][MLIR] Descriptor explicit member map lowering
changes
Th
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
https://github.com/sdesmalen-arm edited
https://github.com/llvm/llvm-project/pull/114263
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jplehr wrote:
I tested this locally and it appears that it requires are more modern CMake
version than what was installed (`3.22`).
According to the LLVM docs
(https://releases.llvm.org/12.0.0/docs/GettingStarted.html#id8) currently CMake
3.20 is the minimum required version.
https://github.c
Author: Ryosuke Niwa
Date: 2024-10-31T00:27:46-07:00
New Revision: ab286462f15736a6e86f0113eab473fb859744be
URL:
https://github.com/llvm/llvm-project/commit/ab286462f15736a6e86f0113eab473fb859744be
DIFF:
https://github.com/llvm/llvm-project/commit/ab286462f15736a6e86f0113eab473fb859744be.diff
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