================
@@ -66,9 +73,215 @@ FunctionPass *llvm::createAMDGPURegBankSelectPass() {
return new AMDGPURegBankSelect();
}
+class RegBankSelectHelper {
+ MachineIRBuilder &B;
+ MachineRegisterInfo &MRI;
+ AMDGPU::IntrinsicLaneMaskAnalyzer &ILMA;
+ const MachineUniformityInfo &MUI;
+ const SIRegisterInfo &TRI;
+ const RegisterBank *SgprRB;
+ const RegisterBank *VgprRB;
+ const RegisterBank *VccRB;
+
+public:
+ RegBankSelectHelper(MachineIRBuilder &B,
+ AMDGPU::IntrinsicLaneMaskAnalyzer &ILMA,
+ const MachineUniformityInfo &MUI,
+ const SIRegisterInfo &TRI, const RegisterBankInfo &RBI)
+ : B(B), MRI(*B.getMRI()), ILMA(ILMA), MUI(MUI), TRI(TRI),
+ SgprRB(&RBI.getRegBank(AMDGPU::SGPRRegBankID)),
+ VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
+ VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {}
+
+ bool shouldRegBankSelect(MachineInstr &MI) {
+ return MI.isPreISelOpcode() || MI.isCopy();
+ }
+
+ // Temporal divergence copy: COPY to vgpr with implicit use of $exec inside
of
+ // the cycle
+ // Note: uniformity analysis does not consider that registers with vgpr def
+ // are divergent (you can have uniform value in vgpr).
+ // - TODO: implicit use of $exec could be implemented as indicator that
+ // instruction is divergent
+ bool isTemporalDivergenceCopy(Register Reg) {
+ MachineInstr *MI = MRI.getVRegDef(Reg);
+ if (!MI->isCopy())
+ return false;
+
+ for (auto Op : MI->implicit_operands()) {
+ if (!Op.isReg())
+ continue;
+
+ if (Op.getReg() == TRI.getExec()) {
+ return true;
+ }
+ }
+
+ return false;
+ }
+
+ void setRBDef(MachineInstr &MI, MachineOperand &DefOP,
+ const RegisterBank *RB) {
+ Register Reg = DefOP.getReg();
+ // Register that already has Register class got it during pre-inst
selection
+ // of another instruction. Maybe cross bank copy was required so we insert
a
+ // copy that can be removed later. This simplifies post regbanklegalize
+ // combiner and avoids need to special case some patterns.
+ if (MRI.getRegClassOrNull(Reg)) {
+ LLT Ty = MRI.getType(Reg);
+ Register NewReg = MRI.createVirtualRegister({RB, Ty});
+ DefOP.setReg(NewReg);
----------------
petar-avramovic wrote:
Why? I intend for new regbankselect be simple and not use observers.
https://github.com/llvm/llvm-project/pull/112863
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