[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

DavidSpickett added a comment. > Could you offer higher abstractions? Show me the current SVME vector length? > Show me the current SVME mode? Adding it to `process status` is along those lines, we have stuff like the number of addressable bits there right now. Overall I prefer the registers r

[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

tschuett added a comment. I would never question giving low-level access to the registers. As you mentioned less experienced users could accidentally switch between the modes with knowing. Comment at: lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_d

[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

DavidSpickett added a comment. > I would never question giving low-level access to the registers. Well in your defense, both `svg` and `svcr` will actually be pseudo registers. So the user isn't getting access to the "real" ones either way, we're emulating the behaviour with ptrace commands. >

[Lldb-commits] [PATCH] D155256: Add fs_base/gs_base support for Linux

DavidSpickett added a comment. Caveat: I have 0 prior knowledge about these registers. What's the testing story here? I see one for fs_base on a live process but none for gs_base and neither for core files. If one test can hit all the code paths those would hit, then fine, but otherwise this ne

[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

jasonmolenda added a comment. In D155269#4509130 , @DavidSpickett wrote: > > Ideally we would have as few routes to mode switch via the debugger as > possible. Writing to the streaming vector control register is the single > route I'd support given

[Lldb-commits] [PATCH] D155107: Add support for llvm::MCInstPrinter::setPrintBranchImmAsAddress

DavidSpickett added a comment. Also you can test it as long as you put the right skipif annotations on it as it'll be architecture specific. Or use a corefile and just check that the backend for that architecture is enabled. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION ht

[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

DavidSpickett added a comment. I think in https://reviews.llvm.org/D154926, `lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py` addresses this. If what you mean is you are stopped in streaming mode, you evaluate an expression that may cal

[Lldb-commits] [lldb] b71ac7e - [lldb/test] Fix command-disassemble-mixed.c

Author: Pavel Labath Date: 2023-07-18T10:17:09+02:00 New Revision: b71ac7eea4c5851203432dde94241d56301a9398 URL: https://github.com/llvm/llvm-project/commit/b71ac7eea4c5851203432dde94241d56301a9398 DIFF: https://github.com/llvm/llvm-project/commit/b71ac7eea4c5851203432dde94241d56301a9398.diff

[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

jasonmolenda added a comment. In D155269#4509364 , @DavidSpickett wrote: > I think in https://reviews.llvm.org/D154926, > `lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py` > addresses this. If

[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

DavidSpickett added a comment. > As a simplification of all of this, and to avoid using g/G, we added > QSaveRegisterState which tells the stub (debugserver etc) to save the current > register context, and then after the inferior function call has completed, > QRestoreRegisterState to restore t

[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

DavidSpickett added a comment. > I suspect that it may be the case that for example, writing to the bottom 128 > bits of streaming mode z0 may not be reflected in the SIMD unit's v0. Or at > least, one could build a core that acted that way. But the user would be very confused by this given tha

[Lldb-commits] [PATCH] D155117: Platform qemu-user: Build path to qemu automatically if not specified

ted added a comment. In D155117#4505538 , @labath wrote: > I am wondering if we actually need the second step (the architecture setting) > here. The main reason it exists is the usage in `GetSupportedArchitectures` > (which is called before a target is

[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

DavidSpickett added a comment. > I am talking to our kernel folks to understand the background to that. The result is that yes cores an implement it as separate state but as mentioned here, taking that into account in lldb would be rather confusing in 99% of situations. If we simply want to rea

[Lldb-commits] [PATCH] D155107: Add support for llvm::MCInstPrinter::setPrintBranchImmAsAddress

ted added a comment. In D155107#4504667 , @jasonmolenda wrote: > Isn't it better to print branches within a function as an offset, given that > our disassembly format by default lists the offset of each instruction. So > instead of looking for a 6-dig

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett updated this revision to Diff 541520. DavidSpickett added a comment. Turns out I was misinterpreting this setence from the kernel docs: Note that when SME is present and streaming SVE mode is in use the FPSIMD subset of registers will be read via NT_ARM_SVE and NT_ARM_SVE writes

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett updated this revision to Diff 541526. DavidSpickett added a comment. Address some comments from the previous version. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154926/new/ https://reviews.llvm.org/D154926 Files: lldb/source/Plu

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett marked 3 inline comments as done. DavidSpickett added inline comments. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:422 +m_sve_state = SVEState::Unknown; +m_sve_state_data.Invalidate(); +m_ssve_state_dat

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett marked 4 inline comments as done. DavidSpickett added inline comments. Comment at: lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py:1 +""" +Test that LLDB correctly reads and writes AArch64 SIMD registers in SVE, -

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett added a comment. On the off chance anyone was going to try and run this, you'll need a kernel that includes https://lore.kernel.org/lkml/20230713-arm64-fix-sve-sme-vl-change-v1-3-129dd8611...@kernel.org/T/. This fixes a bug found while writing these tests. Repository: rG LLVM

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

DavidSpickett updated this revision to Diff 541540. DavidSpickett added a comment. Rebase, fix typo. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154927/new/ https://reviews.llvm.org/D154927 Files: lldb/source/Plugins/Process/Linux/NativeRegist

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

DavidSpickett marked an inline comment as done. DavidSpickett added inline comments. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:1003 + // Bit 2 indicates whether the array storage is active (not yet implemented). + m_sme_ctrl_reg = m_sve

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

DavidSpickett updated this revision to Diff 541542. DavidSpickett marked an inline comment as done. DavidSpickett added a comment. Add missing newline. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154927/new/ https://reviews.llvm.org/D154927 File

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

DavidSpickett added inline comments. Comment at: lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py:30 +"0x000" + expected_value]) + p_reg_size = int(z_reg_size / 8) Thi

[Lldb-commits] [PATCH] D154930: [lldb][AArch64] Add the tpidr2 TLS register that comes with SME

DavidSpickett updated this revision to Diff 541548. DavidSpickett added a comment. Add "Buffer" to method names. enabled -> present in skipped messages. I realised that "enabled" is ambiguous does it mean enabled in the CPU or in the process, present is more clearly meaning is it on the CPU at al

[Lldb-commits] [PATCH] D154930: [lldb][AArch64] Add the tpidr2 TLS register that comes with SME

DavidSpickett updated this revision to Diff 541570. DavidSpickett added a comment. Note the behaviour of tpidr2 on a system without SME. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154930/new/ https://reviews.llvm.org/D154930 Files: lldb/sourc

[Lldb-commits] [PATCH] D154930: [lldb][AArch64] Add the tpidr2 TLS register that comes with SME

DavidSpickett added inline comments. Comment at: lldb/test/API/linux/aarch64/tls_registers/TestAArch64LinuxTLSRegisters.py:73 + +@skipUnlessArch("aarch64") +@skipUnlessPlatform(["linux"]) DavidSpickett wrote: > omjavaid wrote: > > These three tests have

[Lldb-commits] [PATCH] D155256: Add fs_base/gs_base support for Linux

yinghuitan updated this revision to Diff 541597. yinghuitan added a comment. Address review comments: - clang-format - Add coredump tests - Add test against gs_base register Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155256/new/ https://reviews

[Lldb-commits] [PATCH] D155107: Add support for llvm::MCInstPrinter::setPrintBranchImmAsAddress

clayborg added a comment. In D155107#4510539 , @ted wrote: > In D155107#4504667 , @jasonmolenda > wrote: > >> Isn't it better to print branches within a function as an offset, given that >> our disassembly forma

[Lldb-commits] [PATCH] D155117: Platform qemu-user: Build path to qemu automatically if not specified

ted added a comment. As for the GetSupportedArchitectures case, downstream I left in the code that checks the property, but changed the return {}; to return {ArchSpec(llvm::Triple("riscv32-unknown-linux")), ArchSpec(llvm::Triple("riscv64-unknown-linux"))}; I don't think we want that

[Lldb-commits] [PATCH] D155248: [lldb-vscode] Creating a new flag for adjusting the behavior of evaluation repl expressions to allow users to more easily invoke lldb commands.

ashgti updated this revision to Diff 541728. ashgti added a comment. Updating patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155248/new/ https://reviews.llvm.org/D155248 Files: lldb/packages/Python/lldbsuite/test/tools/lldb-vscode/vscode.p

[Lldb-commits] [PATCH] D155107: Add support for llvm::MCInstPrinter::setPrintBranchImmAsAddress

ted added a comment. In D155107#4511967 , @clayborg wrote: > Looks like other disassemblers already show full addresses for the branches > and calls (at least arm64 does from my output above), so not sure why RISCV > would require this setting, but x86_

[Lldb-commits] [PATCH] D155653: [lldb][NFCI] Add some missing SB class forward declarations

bulbazord created this revision. bulbazord added reviewers: JDevlieghere, mib, jingham. Herald added a project: All. bulbazord requested review of this revision. Herald added a project: LLDB. Herald added a subscriber: lldb-commits. I noticed these were missing. Repository: rG LLVM Github Mono

[Lldb-commits] [PATCH] D155653: [lldb][NFCI] Add some missing SB class forward declarations

mib accepted this revision. mib added a comment. This revision is now accepted and ready to land. LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155653/new/ https://reviews.llvm.org/D155653 ___ lldb