From: Tang Yuantian
Freescale introduced new ARM core-based SoCs which support dynamic
frequency switch feature. DFS on new SoCs are compatible with current
PowerPC CoreNet platforms. In order to support those new platforms,
this driver needs to be slightly adjusted. The main changes include:
1.
From: Tang Yuantian
PowerPC E500MC serial SoCs, like T2080 T1040 and T4240, use RCPM
to manage power consumption. This patch adds hot plug feature to
RCPM driver.
Signed-off-by: Chenhui Zhao
Signed-off-by: Tang Yuantian
---
arch/powerpc/include/asm/fsl_pm.h | 2 ++
arch/powerpc/sysdev/fsl_rc
From: Tang Yuantian
P2020RDB-PC Board shares the same design(PCB) as P102x RDB style platforms.
The difference between this platform and the already existing P2020RDB
is mainly with respect to DDR. The P2020RDB-PC has a DDR3 memory.
The P2020RDB-PC also has a CPLD device connected to local bus.
From: Tang Yuantian
The p1024rdb has the similar feature as the p1020rdb. Therefore, p1024rdb use
the same platform file as the p1/p2 rdb board.
Overview of P2020RDB platform
- DDR3 1G
- NOR flash 16M
- 3 Ethernet interfaces
- NAND Flash 32M
- SPI EEPROM 16
From: Tang Yuantian
Signed-off-by: Jin Qing
Signed-off-by: Li Yang
Signed-off-by: Tang Yuantian
---
arch/powerpc/boot/dts/fsl/p1024si-pre.dtsi| 68
arch/powerpc/boot/dts/p1024rdb.dts| 87 ++
arch/powerpc/boot/dts/p1024rdb.dtsi | 228
From: Tang Yuantian
The following platforms are supported:
mpc8544, mpc8572, mpc8536, p1021, p1025, p1024, p1010.
Signed-off-by: Tang Yuantian
---
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_85
From: Tang Yuantian
Signed-off-by: Tang Yuantian
---
arch/powerpc/boot/dts/p2020rdb-pc_32b.dts |4 ++--
arch/powerpc/boot/dts/p2020rdb-pc_36b.dts |4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
b/arch/powerpc/boot/dts/p2
From: crazytyt
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Poonam Aggrwal
Signed-off-by: Tang Yuantian
---
V1 vs V2:
-rename dts from .dts to _32b.dts
-remove amp dts
arch/powerpc/boot/dts/p2020rdb-pc.dtsi| 241 +
arch/powerpc/boot/dts/p2
From: crazytyt
Signed-off-by: Jin Qing
Signed-off-by: Li Yang
Signed-off-by: Tang Yuantian
---
v1 vs v2:
-remove amp dts
-rename the dts from .dts to _32b.dts
-remove p1024si-pre.dtsi
arch/powerpc/boot/dts/p1024rdb.dtsi| 228
arch
From: Tang Yuantian
Signed-off-by: Jin Qing
Signed-off-by: Li Yang
Signed-off-by: Tang Yuantian
---
v3:
-correct the patch author
arch/powerpc/boot/dts/p1024rdb.dtsi| 228
arch/powerpc/boot/dts/p1024rdb_32b.dts | 87
arch/powerpc/b
From: Tang Yuantian
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Poonam Aggrwal
Signed-off-by: Tang Yuantian
---
v3:
-correct the patch author
arch/powerpc/boot/dts/p2020rdb-pc.dtsi| 241 +
arch/powerpc/boot/dts/p2020rdb-pc_32b.dts | 96
From: Tang Yuantian
Signed-off-by: Jin Qing
Signed-off-by: Li Yang
Signed-off-by: Tang Yuantian
---
arch/powerpc/boot/dts/p1024rdb.dtsi| 228
arch/powerpc/boot/dts/p1024rdb_32b.dts | 87
arch/powerpc/boot/dts/p1024rdb_36b.dts | 87 +++
From: Tang Yuantian
The p1024rdb has the similar feature as the p1020rdb. Therefore, p1024rdb use
the same platform file as the p1/p2 rdb board.
Overview of P2020RDB platform
- DDR3 1G
- NOR flash 16M
- 3 Ethernet interfaces
- NAND Flash 32M
- SPI EEPROM 16
From: Tang Yuantian
In SMP mode, the kernel would produce call trace when resumed
from hibernation. The reason is when the function destroy_context
is called to drop the resuming mm context, the mm->context.active
is 1 which is wrong and should be zero.
We
> >
> > clockgen: global-utilities@e1000 {
> > - compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
> > + compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0",
> > + "fixed-clock";
> > + clock-output-names = "sysclk";
>
> > > > + };
> > > > + pll1: pll1@820 {
> > > > + #clock-cells = <1>;
> > > > + reg = <0x820>;
> > > > + compatible = "fsl,core-pll-clock";
> > > > + clocks = <&clockgen>;
> > > > +
Hi,
These eeproms are never used by kernel. So no need to add them.
Thanks,
Yuantian
> -Original Message-
> From: Linuxppc-dev [mailto:linuxppc-dev-
> bounces+b29983=freescale@lists.ozlabs.org] On Behalf Of Yang,Wei
> Sent: 2013年9月4日 星期三 9:27
> To: Jia Hongtao-B3
Hi,
I noticed that there are already some nodes in i2c bus.
You should at least move the existing node into PCA9547.
Thanks,
Yuantian
> -Original Message-
> From: Linuxppc-dev [mailto:linuxppc-dev-
> bounces+b29983=freescale@lists.ozlabs.org] On Behalf Of Jia Hongtao-
> -Original Message-
> From: Wood Scott-B07421
> Sent: 2013年9月6日 星期五 2:41
> To: Tang Yuantian-B29983
> Cc: Yang,Wei; Jia Hongtao-B38951; Wood Scott-B07421; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: [PATCH] powerpc: Add I2C bus multiplexer node for B4 and
&
OK, will update per your suggestions.
Thanks,
Yuantian
> -Original Message-
> From: Wood Scott-B07421
> Sent: 2013年9月11日 星期三 5:47
> To: Tang Yuantian-B29983
> Cc: Wood Scott-B07421; ga...@kernel.crashing.org;
> devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.o
> -Original Message-
> From: Wood Scott-B07421
> Sent: 2013年9月12日 星期四 9:10
> To: Tang Yuantian-B29983
> Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
> devicet...@vger.kernel.org; Li Yang-Leo-R58472
> Subject: Re: [PATCH v4] powerpc/mpc85xx: Update
> -Original Message-
> From: Wood Scott-B07421
> Sent: 2013年9月12日 星期四 22:44
> To: Tang Yuantian-B29983
> Cc: Wood Scott-B07421; ga...@kernel.crashing.org; linuxppc-
> d...@lists.ozlabs.org; devicet...@vger.kernel.org; Li Yang-Leo-R58472
> Subject: Re: [PATCH v4] po
> > > On Wed, 2013-09-11 at 20:31 -0500, Tang Yuantian-B29983 wrote:
> > > > > -Original Message-
> > > > > From: Wood Scott-B07421
> > > > > Sent: 2013年9月12日 星期四 9:10
> > > > > To: Tang Yuantian-B29983
&
Thanks for your review.
See my reply inline
> -Original Message-
> From: Mark Rutland [mailto:mark.rutl...@arm.com]
> Sent: 2013年10月10日 星期四 18:04
> To: Tang Yuantian-B29983
> Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
> devicet...@vger.kernel.org;
Thanks for your review.
> -Original Message-
> From: Wood Scott-B07421
> Sent: 2013年10月12日 星期六 3:07
> To: Mark Rutland
> Cc: Tang Yuantian-B29983; devicet...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org; Li Yang-Leo-R58472
> Subject: Re: [PATCH v5] powerpc/mpc8
Thanks for your review.
> -Original Message-
> From: Wood Scott-B07421
> Sent: 2013年10月12日 星期六 3:08
> To: Tang Yuantian-B29983
> Cc: ga...@kernel.crashing.org; devicet...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: [PATCH v5] powerpc/mpc85xx: U
Thanks for your review.
>
> >
> > > > +- reg: Offset and length of the clock register set
> > > > +- clock-frequency: Indicates input clock frequency of clock block.
> > > > + Will be set by u-boot
> > >
> > > Why does the fact this is set by u-boot matter to the binding?
> > >
> > OK, I wi
> -Original Message-
> From: Wood Scott-B07421
> Sent: 2013年10月15日 星期二 6:13
> To: Tang Yuantian-B29983
> Cc: Wood Scott-B07421; Mark Rutland; devicet...@vger.kernel.org;
> linuxppc-dev@lists.ozlabs.org; Li Yang-Leo-R58472
> Subject: Re: [PATCH v5] powerpc/mpc85xx: U
> > > > >
> > > > The device tree makes that quite clear.
> > >
> > > You chose to model it that way in the device tree; that doesn't make
> > > it clear that the hardware works that way or that it's a good way to
> > > model it.
> > >
> > > > Each PLL has several output which MUX node can take fro
> > > That shows the dividers as being somewhere in between the PLL and the
> MUX.
> > > The MUX is where the divider is selected. There's nothing in the
> > > PLL's programming interface that relates to the dividers. As such
> > > it's simpler to model it as being part of the MUX.
> > >
> > > -S
> On Wed, 2013-10-16 at 21:08 -0500, Tang Yuantian-B29983 wrote:
> > > > > That shows the dividers as being somewhere in between the PLL
> > > > > and the
> > > MUX.
> > > > > The MUX is where the divider is selected. There's nothin
> > > > >
> > > > > It's still selecting from multiple PLLs.
> > > > >
> > > > > > I don't know whether "divider" module exists or not. If it
> > > > > > exists, it should be part of PLL or between PLL and MUX.
> > > > > > wherever it was, the
> > > > > device tree binding is appropriate.
> > > > >
Thanks for your review.
> -Original Message-
> From: Mark Rutland [mailto:mark.rutl...@arm.com]
> Sent: 2013年10月21日 星期一 17:15
> To: Tang Yuantian-B29983
> Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
> devicet...@vger.kernel.org; Li Yang-Leo-R58472
>
> > +1. Clock Block Binding
> > +
> > +Required properties:
> > +- compatible: Should include one or more of the following:
> > + - "fsl,-clockgen": for chip specific clock block
> > + - "fsl,qoriq-clockgen-[1,2].x": for chassis 1.x and 2.x clock
> > +- reg: Offset and length of the clock regis
Thanks for your review.
> -Original Message-
> From: Wood Scott-B07421
> Sent: 2013年10月29日 星期二 11:26
> To: Tang Yuantian-B29983
> Cc: Wood Scott-B07421; Mark Rutland; devicet...@vger.kernel.org;
> linuxppc-dev@lists.ozlabs.org; Li Yang-Leo-R58472
> Subject: Re: [PATC
> Subject: Re: [PATCH][V2] powerpc: remove the PPC_CLOCK dependency
>
>
> On Mar 6, 2013, at 3:16 AM,
> wrote:
>
> > From: Tang Yuantian
> >
> > config FSL_SOC and CPM do not really depend on PPC_CLOCK. So remove it.
> > PPC_CLOCK also keeps powerpc archtecture from supporting COMMON_CLK.
> >
> > + return ret;
> > +
> > + pr_info("Freescale PowerPC corenet CPU frequency scaling driver\n");
> > +
> > + return ret;
> > +}
> > +
> > +static void __exit ppc_corenet_cpufreq_exit(void) {
> > + cpufreq_unregister_driver(&ppc_corenet_cpufreq_driver);
> > +}
> > +
> > +module_ini
> > +static int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy) {
> > + unsigned int cpu = policy->cpu;
> > + struct device_node *np;
> > + int i, count;
> > + struct clk *clk;
> > + struct cpufreq_frequency_table *table;
> > + struct cpu_data *data;
> >
> -Original Message-
> From: Viresh Kumar [mailto:viresh.ku...@linaro.org]
> Sent: 2013年3月29日 11:17
> To: Tang Yuantian-B29983
> Cc: r...@sisk.pl; cpuf...@vger.kernel.org; linux...@vger.kernel.org;
> linuxppc-dev@lists.ozlabs.org; Li Yang-R58472
> Subject: Re: [PATCH
> -Original Message-
> From: cpufreq-ow...@vger.kernel.org [mailto:cpufreq-ow...@vger.kernel.org]
> On Behalf Of Viresh Kumar
> Sent: 2013年3月30日 21:52
> To: Tang Yuantian-B29983
> Cc: Rafael J. Wysocki; cpuf...@vger.kernel.org; Linux PM list; linuxppc-
> d...@list
Also send this patch to cpuf...@vger.kernel.org and linux...@vger.kernel.org
And better to rebase it on
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git
Thanks,
Yuantian
> -Original Message-
> From: Linuxppc-dev [mailto:linuxppc-dev-
> bounces+b29983=
Thanks, you make my code look better each review.
Thanks,
Yuantian
> -Original Message-
> From: Viresh Kumar [mailto:viresh.ku...@linaro.org]
> Sent: 2013年4月9日 17:47
> To: Tang Yuantian-B29983
> Cc: r...@sisk.pl; cpuf...@vger.kernel.org; linux...@vger.kernel.o
> -Original Message-
> From: Stephen Rothwell [mailto:s...@canb.auug.org.au]
> Sent: 2013年4月10日 17:03
> To: Tang Yuantian-B29983
> Cc: grant.lik...@secretlab.ca; devicetree-disc...@lists.ozlabs.org;
> linuxppc-dev@lists.ozlabs.org; linux-ker...@vger.kernel.org;
> ro
Hi Grant.likely,
I really preciate if you can spend some times to review this patch.
Thanks,
Yuantian
> -Original Message-
> From: Tang Yuantian-B29983
> Sent: 2013年4月10日 11:37
> To: grant.lik...@secretlab.ca
> Cc: rob.herr...@calxeda.com; devicetree-disc...@lists.oz
Hi Mike,
I really appreciate if you can spend some times to review this patch.
Thanks,
Yuantian
> -Original Message-
> From: Tang Yuantian-B29983
> Sent: 2013年4月9日 16:46
> To: mturque...@linaro.org
> Cc: linus.wall...@linaro.org; viresh.ku...@linaro.org;
> sh
OK, thanks.
Thanks,
Yuantian
> -Original Message-
> From: Mike Turquette [mailto:mturque...@linaro.org]
> Sent: 2013年4月17日 6:27
> To: Tang Yuantian-B29983; Tang Yuantian-B29983
> Cc: linus.wall...@linaro.org; viresh.ku...@linaro.org;
> shawn@linaro.org; ulf.hans...
> -Original Message-
> From: Timur Tabi [mailto:ti...@tabi.org]
> Sent: 2013年4月16日 19:37
> To: Tang Yuantian-B29983
> Cc: Grant Likely; devicetree-discuss; linuxppc-dev@lists.ozlabs.org; lkml;
> Rob Herring
> Subject: Re: [PATCH v2] of/base: release
> -Original Message-
> From: Timur Tabi [mailto:ti...@tabi.org]
> Sent: 2013年4月17日 11:31
> To: Tang Yuantian-B29983
> Cc: Grant Likely; devicetree-discuss; linuxppc-dev@lists.ozlabs.org; lkml;
> Rob Herring
> Subject: Re: [PATCH v2] of/base: release
> On 01/09/2012 02:37 AM, b29...@freescale.com wrote:
> > +/include/ "p1024rdb.dtsi"
> > +/include/ "fsl/p1020si-post.dtsi"
>
> Is p1024 100% software-compatible with p1020?
>
> They have different manuals...
>
> -Scott
P1020rdb has vitesse-7385 switch.
fsl/p1020si-post.dtsi can be used for bo
> >
> > P1020rdb has vitesse-7385 switch.
>
> I'm talking about the SoC, not the board.
>
> > fsl/p1020si-post.dtsi can be used for both boards.
>
> What are you basing this on? Has someone looked over both manuals in
> detail and concluded that every device described is 100% compatible?
>
I
> I'm curious how fsl_pq_mdio_probe returns successfully when probing the
> phys on the first pass (mdio@24000). I don't have a P1024 to test with,
> but I believe it has the same ETSEC configuration as the P1010 that I
> work with.
>
> Inside the fsl_pq_mdio_probe routine (fsl_pq_mdio.c), a su
Hi Cedric MAUSSIRE,
P2020RDB-PCA Board gets supported since kernel 3.3 in mainline code.
Are you sure the board works on kernel 2.6.35?
Regards,
Yuantian
From: linuxppc-dev-bounces+b29983=freescale@lists.ozlabs.org
[mailto:linuxppc-dev-bounces+b29983=freescale@lists.ozlabs.org] On
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