I am looking for info on when and how we are able to disable power saving
features of current (P7, P7+) chips in order to reduce latency. This is often
done in latency sensitive applications when power consumption is not an issue.
On Intel boxes we can disable P-state frequency changes as well a
On 01/14/2014 10:10 AM, Preeti U Murthy wrote:
> Hi Steven,
>
> On 01/14/2014 08:06 PM, Steven Pratt wrote:
>> I am looking for info on when and how we are able to disable power saving
>> features of current (P7, P7+) chips in order to reduce latency. This is
>> ofte
