I am looking for info on when and how we are able to disable power saving 
features of current (P7, P7+) chips in order to reduce latency. This is often 
done in latency sensitive applications when power consumption is not an issue. 
On Intel boxes we can disable P-state frequency changes as well as disabling 
C-State or sleep state changes. In fact we can control how deep a sleep the 
processor can go into.  I know we have control Dynamic Processor Scaling and 
Idle Power Savings, but what states do these really affect?  Can I really 
disable Nap mode of a processor? If so how?  Can I disable even the lightest 
winkle mode?  Looking for current information (read RHEL 6 and SLES11), future 
changes are interesting.

Steve

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