Bhushan Bharat-R65777 wrote:
>
>
> > -Original Message-
> > From: Michael Neuling [mailto:mi...@neuling.org]
> > Sent: Tuesday, February 12, 2013 9:16 AM
> > To: Bhushan Bharat-R65777
> > Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.or
Scott Wood wrote:
> On 02/12/2013 03:01:07 AM, Bhushan Bharat-R65777 wrote:
> >
> >
> > > -Original Message-----
> > > From: Michael Neuling [mailto:mi...@neuling.org]
> > > Sent: Tuesday, February 12, 2013 9:46 AM
> > > To: Bhushan Bhar
POWER8 implements hardware transactional memory support. This patch series
adds kernel support so that user programs can use this hardware transactional
memory and the new state is properly context switched. It is not currently
used by the kernel itself.
This patch series was originally develope
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/cputable.h |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 5f1938f..3636081 100644
--- a/arch/powerpc/include/asm
ns
an abort reason.
trecheckpoint allows us to inject into the checkpointed state as if it were at
the tbegin. It does this by copying the current architected state into the
checkpointed state.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/ppc-opcode.h |
Set of new archtected state for saving away on context switch.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/processor.h | 28
1 file changed, 28 insertions(+)
diff --git a/arch/powerpc/include/asm/processor.h
b/arch
This adds new macros for saving and restoring checkpointed architected state
from and to the thread_struct.
It also adds some debugging macros for when your brain explodes trying to debug
your transactional memory enabled kernel.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
Defines for MSR bits and transactional memory related SPRs TFIAR, TEXASR and
TEXASRU.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/reg.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b
Add transactional memory paca scratch register to show_regs. This is useful
for debugging.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/paca.h |1 +
arch/powerpc/kernel/asm-offsets.c |1 +
arch/powerpc/kernel/entry_64.S|4
arch
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/reg.h |2 +-
arch/powerpc/include/asm/tm.h | 20 +++
arch/powerpc/kernel/Makefile |2 +
arch/powerpc/kernel/tm.S | 388
4 files changed, 411 insertions(+), 1 deletion
d for VMX registers.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/fpu.S| 54 ++
arch/powerpc/kernel/vector.S | 51 +++
2 files changed, 105 insertions(+)
diff --git a/arch/po
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/process.c | 112 +
1 file changed, 112 insertions(+)
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 1cc4053..48a9875 100644
--- a/arch/powe
These should never happen since we always turn on MSR TM when in userspace. We
don't do lazy TM.
Hence if we hit this, we barf and kill the task as something's gone horribly
wrong.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/exceptions-64
P, VMX and VSX. It doesn't
hook them into the rest of the code yet.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/traps.c | 83 +++
1 file changed, 83 insertions(+)
diff --git a/arch/powerpc/kernel/traps.c b/arch
This hooks the new transactional memory code into context switching, FP/VMX/VMX
unavailable and exception return.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/exceptions-64s.S | 56 --
arch/powerpc/kernel/process.c
This adds the new transactional memory archtected state to the signal context
in both 32 and 64 bit.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/reg.h |1 +
arch/powerpc/kernel/signal.h|8 +
arch/powerpc/kernel/signal_32.c | 500
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/cputable.h |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 3636081..fb3245e 100644
--- a/arch/powerpc
Kconfig option for transactional memory on powerpc.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/Kconfig |8
1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 4b27edb..fbeb6d2 100644
--- a/arch/powerpc
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/configs/ppc64_defconfig |2 ++
arch/powerpc/configs/pseries_defconfig |2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/powerpc/configs/ppc64_defconfig
b/arch/powerpc/configs/ppc64_defconfig
index
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
Documentation/powerpc/transactional_memory.txt | 175
1 file changed, 175 insertions(+)
create mode 100644 Documentation/powerpc/transactional_memory.txt
diff --git a/Documentation/powerpc
Kumar Gala wrote:
>
> On Feb 12, 2013, at 10:31 PM, Michael Neuling wrote:
>
> > Kconfig option for transactional memory on powerpc.
> >
> > Signed-off-by: Matt Evans
> > Signed-off-by: Michael Neuling
> > ---
> > arch/powerpc/Kconfig |
> > +/* void do_load_up_fpu(struct thread_struct *thread)
>
> Comment is wrong, should be void do_load_up_transact_fpu(...)
Ooops, thanks for the catch.
> > +/* void do_load_up_altivec(struct thread_struct *thread)
>
> comment wrong.
Ooops again.
FYI I'm in Austin next week if you wanna grab
Kumar Gala wrote:
>
> On Feb 12, 2013, at 10:31 PM, Michael Neuling wrote:
>
> > Add transactional memory paca scratch register to show_regs. This is useful
> > for debugging.
> >
> > Signed-off-by: Matt Evans
> > Signed-off-by: Michael Neuling
>
POWER8 implements hardware transactional memory support. This patch series
adds kernel support so that user programs can use this hardware transactional
memory and the new state is properly context switched. It is not currently
used by the kernel itself.
This patch series was originally develope
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/cputable.h |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 5f1938f..3636081 100644
--- a/arch/powerpc/include/asm
ns
an abort reason.
trecheckpoint allows us to inject into the checkpointed state as if it were at
the tbegin. It does this by copying the current architected state into the
checkpointed state.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/ppc-opcode.h |
Set of new archtected state for saving away on context switch.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/processor.h | 28
1 file changed, 28 insertions(+)
diff --git a/arch/powerpc/include/asm/processor.h
b/arch
This adds new macros for saving and restoring checkpointed architected state
from and to the thread_struct.
It also adds some debugging macros for when your brain explodes trying to debug
your transactional memory enabled kernel.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
Defines for MSR bits and transactional memory related SPRs TFIAR, TEXASR and
TEXASRU.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/reg.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b
Add transactional memory paca scratch register to show_regs. This is useful
for debugging.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/paca.h |3 +++
arch/powerpc/kernel/asm-offsets.c |1 +
arch/powerpc/kernel/entry_64.S|4
arch
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/reg.h |2 +-
arch/powerpc/include/asm/tm.h | 20 +++
arch/powerpc/kernel/Makefile |2 +
arch/powerpc/kernel/tm.S | 388
4 files changed, 411 insertions(+), 1 deletion
d for VMX registers.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/fpu.S| 54 ++
arch/powerpc/kernel/vector.S | 51 +++
2 files changed, 105 insertions(+)
diff --git a/arch/po
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/process.c | 112 +
1 file changed, 112 insertions(+)
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 1cc4053..48a9875 100644
--- a/arch/powe
These should never happen since we always turn on MSR TM when in userspace. We
don't do lazy TM.
Hence if we hit this, we barf and kill the task as something's gone horribly
wrong.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/exceptions-64
P, VMX and VSX. It doesn't
hook them into the rest of the code yet.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/traps.c | 83 +++
1 file changed, 83 insertions(+)
diff --git a/arch/powerpc/kernel/traps.c b/arch
This hooks the new transactional memory code into context switching, FP/VMX/VMX
unavailable and exception return.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/exceptions-64s.S | 56 --
arch/powerpc/kernel/process.c
This adds the new transactional memory archtected state to the signal context
in both 32 and 64 bit.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/reg.h |1 +
arch/powerpc/kernel/signal.h|8 +
arch/powerpc/kernel/signal_32.c | 500
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/cputable.h |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 3636081..fb3245e 100644
--- a/arch/powerpc
Kconfig option for transactional memory on powerpc.
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/Kconfig |8
1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 4b27edb..85ff3a0 100644
--- a/arch/powerpc
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/configs/ppc64_defconfig |2 ++
arch/powerpc/configs/pseries_defconfig |2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/powerpc/configs/ppc64_defconfig
b/arch/powerpc/configs/ppc64_defconfig
index
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
Documentation/powerpc/transactional_memory.txt | 175
1 file changed, 175 insertions(+)
create mode 100644 Documentation/powerpc/transactional_memory.txt
diff --git a/Documentation/powerpc
Benjamin Herrenschmidt wrote:
> On Thu, 2013-02-21 at 15:52 +1100, Stephen Rothwell wrote:
> > Hi Al,
> >
> > Today's linux-next merge of the signal tree got conflicts in
> > arch/powerpc/kernel/signal_32.c and arch/powerpc/kernel/signal_64.c
> > between commit 2b0a576d15e0 ("powerpc: Add new tr
.c
Signed-off-by: Michael Neuling
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index a8a5361..87ef8f5 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -74,13 +74,13 @@ END_FTR_SECTION_IFSET(CPU_F
Benh,
Here are a few fixes for the POWER8 FSCR.
First patch changes the FSCR so that it's set on secondary CPUs as well as when
MSR HV=0.
Second two patches make sure that the FSCR DSCR bit is set so that we don't
trap on DSCR accesses.
These are aimed to fix issues in 3.9.
Mikey
Currently we only set the FSCR when HV=1 but this feature is available when
HV=0 also. This patch sets FSCR when HV=0.
Also, we currently only set the FSCR on the master CPU. This patch also sets
the FSCR on secondary CPUs.
Signed-off-by: Michael Neuling
cc: Ian Munsie
---
arch/powerpc
Also harmonise TAR bit definition too.
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/reg.h |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index e665861..a43cd2d 100644
--- a/arch/powerpc
We support DSCR so we should make sure we set it in the FSCR incase some
firmwares don't set it.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/cpu_setup_power.S |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/cpu_setup_power.S
b/arch/po
Benh,
Here are a few fixes for the POWER8 (Performance Optimization With Enhanced
RISC Eight) FSCR (Facility Status & Control Register).
First patch changes the FSCR so that it's set on secondary CPUs as well as when
MSR HV=0.
Second two patches make sure that the FSCR DSCR (Data Stream Control
Currently we only set the FSCR (Facility Status and Control Register) when HV=1
but this feature is available when HV=0 also. This patch sets FSCR when HV=0.
Also, we currently only set the FSCR on the master CPU. This patch also sets
the FSCR on secondary CPUs.
Signed-off-by: Michael Neuling
This sets the DSCR (Data Stream Control Register) in the FSCR (Facility Status
& Control Register).
Also harmonise TAR (Target Address Register) FSCR bit definition too.
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/reg.h |3 ++-
1 file changed, 2 insertions(+), 1 dele
We support DSCR (Data Stream Control Register) so we should make sure we set it
in the FSCR (Facility Status & Control Register) incase some firmwares don't
set it. If we don't set this, we'll take a facility unavailable exception when
using the DSCR.
Signed-off-by: Michael
Benh,
This small series adds support for the HFSCR (Hypervisor Facility Status &
Control Register) in POWER8. It just sets the bits we know about at this
stage. This is useful only when MSR HV=1.
Mikey
___
Linuxppc-dev mailing list
Linuxppc-dev@lists
Add SPR number and bit definitions for the HFSCR (Hypervisor Facility Status
and Control Register).
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/reg.h |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
Setup the HFSCR (Hypervisor Facility Status and Control Register) for POWER8
when running HV=1. The HFSCR is the same as the FSCR except but for
hypervisors.
This patch sets the facilities Linux knows about incase the firmware doesn't.
Signed-off-by: Michael Neuling
---
arch/powerpc/k
Benh,
This small series adds support for the HFSCR (Hypervisor Facility Status &
Control Register) in POWER8. It just sets the bits we know about at this
stage. This is useful only when MSR HV=1.
The HFSCR is the same as the FSCR except it's for hypervisors. It controls the
available of vario
Add SPR number and bit definitions for the HFSCR (Hypervisor Facility Status
and Control Register).
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/reg.h |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
ility
unavailable interrupt (although we are not using this here).
This patch sets the facilities Linux knows about incase the firmware doesn't.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/cpu_setup_power.S |8
1 file changed, 8 insertions(+)
diff --git a/arch/powe
> bisect tells me that since your commit
> 9422de3e953d0e60eb95f5430a9dd803eec1c6d7
> "powerpc: Hardware breakpoints rewrite to handle non DABR breakpoint
> registers",
> compiling linux fails with :
>
> cc1: warnings being treated as errors
> arch/powerpc/kernel/ptrace.c: In function 'arch
Philippe De Muyter wrote:
> On Thu, Mar 07, 2013 at 09:09:48AM +1100, Michael Neuling wrote:
> > > bisect tells me that since your commit
> > > 9422de3e953d0e60eb95f5430a9dd803eec1c6d7
> > > "powerpc: Hardware breakpoints rewrite to handle non DABR breakpoint
Philippe De Muyter wrote:
> Hello Mikey,
>
> On Thu, Mar 07, 2013 at 10:14:30AM +1100, Michael Neuling wrote:
> > Philippe De Muyter wrote:
> >
> > > On Thu, Mar 07, 2013 at 09:09:48AM +1100, Michael Neuling wrote:
> > > >
Michael Neuling wrote:
> Philippe De Muyter wrote:
>
> > Hello Mikey,
> >
> > On Thu, Mar 07, 2013 at 10:14:30AM +1100, Michael Neuling wrote:
> > > Philippe De Muyter wrote:
> > >
> > > > On Thu, Mar 07, 2013 at 09:09:48AM +1100, M
arch/powerpc/kernel/ptrace.c:1381: note: 'brk.len' was declared here
This patch corrects this.
Signed-off-by: Michael Neuling
Reported-by: Philippe De Muyter
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 245c1b6..f9b30c6 100644
--- a/arch/powerpc/k
> do next-* tree support powerpc POWER7 with allmodconfig ?
>
> I met an issue, can we bear it (or I need additional trying) ?
>
>
> Compiling:
> make V=1 EXTRA_CFLAGS=-W ARCH=powerpc allmodconfig
> set cpu type POWER7 in menuconfig.
> set cross-compiler in menuconfig.
> unde
> From: Ian Munsie
>
> This patch adds a new line to /proc/interrupts to account for the
> doorbell interrupts that each hardware thread has received. The total
> interrupt count in /proc/stat will now also include doorbells.
It's probably worth noting in the comment that these are not being
acc
completions.
This is great, thanks a lot.
If you want this to be picked up by the maintainer, you'll need to add
your signed-off-by.
The signed-off-by is to indicate that your happy for it to be included
and that you're legally allowed to do so. See
http://gerrit.googlecode.com/svn/docu
; but still not enough (still content overflow bytes)
> >
> > additional trying:
> > after del CONFIG_VSX and CONFIG_PPC_970_NAP in allmodconfig,
> > (will reduce dozens bytes in the region .0x5500 -- .0x7000)
> > it can pass compilin
ternally decide the constraints.
Signed-off-by: Michael Neuling
diff --git a/Documentation/powerpc/ptrace.txt b/Documentation/powerpc/ptrace.txt
index f2a7a39..99c5ce8 100644
--- a/Documentation/powerpc/ptrace.txt
+++ b/Documentation/powerpc/ptrace.txt
@@ -40,6 +40,7 @@ features will have bits ind
Chen Gang wrote:
> On 2013年03月22日 06:54, Michael Neuling wrote:
> > This is great, thanks a lot.
> >
> > If you want this to be picked up by the maintainer, you'll need to add
> > your signed-off-by.
> >
> > The signed-off-by is to indicate that y
Stuart Yoder wrote:
> From: Stuart Yoder
>
> For 32-bit, CONFIG_EPAPR_PARAVIRT pulls in both epapr_paravirt.c
> and epapr_hcalls.c which contains the 32-bit paravirt idle loop.
>
> For 64-bit, the paravirt idle loop is in idle_book3e.S and that
> source file is included only if CONFIG_PPC_BOOK
Stephen Rothwell wrote:
> Hi all,
>
> On Mon, 25 Mar 2013 09:31:31 +0800 Chen Gang wrote:
> >
> > The FWNMI region is fixed at 0x7000 and the vector are now overflowing
> > that with allmodconfig. Fix that by moving slb_miss_realmode code out
> > of that region as it doesn't need to be th
S:323: Error: unsupported relocation against THREAD_VR0
etc.
The below fixes this with a sprinkling of #ifdefs.
This was found by mpe with kisskb:
http://kisskb.ellerman.id.au/kisskb/buildresult/8539442/
Signed-off-by: Michael Neuling
---
sfr: this would be nice to get in 3.9.
diff --git a/arch/po
() never fails and it is used in multiple places so it has not
> been changed by this patch.
>
> Signed-off-by: Alexey Kardashevskiy
FWIW:
Acked-by: Michael Neuling
> ---
> arch/powerpc/include/asm/ptrace.h |3 ++-
> arch/powerpc/kernel/ptrace.c | 29 +
powerpc/fsl-pci: Keep PCI SoC controller registers in pci_controller
Which changed definition of setup_pci_atmu() but didn't update one of
the callers. Below fixes this.
Signed-off-by: Michael Neuling
---
Kumar: this is for your next tree
diff --git a/arch/powerpc/sysdev/fsl_pci.c b
We are currently out of free bits in AT_HWCAP. With POWER8, we have
several hardware features that we need to advertise.
Tested on POWER and x86.
Signed-off-by: Michael Neuling
Signed-off-by: Nishanth Aravamudan
---
> Wouldn't it be safer to not emit AT_HWCAP2 unless it is define
akpm,
If you're happy with this, is it something you can take in your tree?
Mikey
Michael Neuling wrote:
> We are currently out of free bits in AT_HWCAP. With POWER8, we have
> several hardware features that we need to advertise.
>
> Tested on POWER and x86.
>
>
Michael Ellerman wrote:
> On Thu, Apr 18, 2013 at 05:56:12PM +0530, Anshuman Khandual wrote:
> > This patch adds new POWER8 instruction encoding for reading
> > the BHRB buffer entries and also clearing it. Encoding for
> > "clrbhrb" instruction is straight forward.
>
> Which is "clear branch hi
Michael Ellerman wrote:
> On Mon, Apr 22, 2013 at 11:13:43AM +1000, Michael Neuling wrote:
> > Michael Ellerman wrote:
> >
> > > On Thu, Apr 18, 2013 at 05:56:12PM +0530, Anshuman Khandual wrote:
> > > > This patch adds new POWER8 instruction encoding
This was already posted about a week back. Kumar can you please take
it?
http://patchwork.ozlabs.org/patch/236494/
Mikey
Roy Zang wrote:
> setup_pci_atmu() only has one parameter and remove the extra one, or
> build will fail due to un-match.
>
> Signed-off-by: Roy Zang
> ---
> arch/powerp
completed before any branching to the new instructions occurs.
Signed-off-by: Michael Neuling
cc: sta...@kernel.org
---
benh: we should get this in 3.9 ASAP.
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 0886ae6..b61363d 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b
Mike Qiu wrote:
> 于 2013/4/24 16:31, Michael Ellerman 写道:
> > On Wed, Apr 24, 2013 at 04:22:53PM +0800, Mike Qiu wrote:
> >> Hi all
> >>
> >> I get an error message when I compile the source code in Power7 platform
> >> use the newest upstream kernel.
> > Hi Mike,
> >
> > It depends on what your
> Considering that the bug has been there *forever* I don't think I have a
> real standing to try to shove it down Linus throat as a "regression
> fix" :-)
True, sorry.
> I'll put the fix in 3.10 and let it trickle down to stable.
Thanks
Mikey
___
Lin
restore.
Signed-off-by: Michael Neuling
diff --git a/arch/powerpc/kernel/cpu_setup_power.S
b/arch/powerpc/kernel/cpu_setup_power.S
index ea847ab..1167008 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -66,6 +66,7 @@ _GLOBAL(__restore_cpu_power8
Michael Neuling wrote:
> In __restore_cpu_power8 we determine if we are HV and if not, we return
> before setting HV only resources.
>
> Unfortunately we forgot to restore the link register from r11 before
> returning.
>
> This will happen on boot and with secondary C
Chen Gang wrote:
>
> When CONFIG_KVM_BOOK3S_64_PR is enabled,
> MASKABLE_EXCEPTION_PSERIES(0x900 ...) will includes __KVMTEST, it will
> exceed 0x980 which STD_EXCEPTION_HV(0x980 ...) will use, it will cause
> compiling issue.
>
> The related errors:
> arch/powerpc/kernel/exceptions-64s.S: Asse
Chen Gang wrote:
>
> When CONFIG_KVM_BOOK3S_64_PR is enabled,
> MASKABLE_EXCEPTION_PSERIES(0x900 ...) will includes __KVMTEST, it will
> exceed 0x980 which STD_EXCEPTION_HV(0x980 ...) will use, it will cause
> compiling issue.
>
> The related errors:
> arch/powerpc/kernel/exceptions-64s.S: Asse
The below fixes this to check CPU_FTR_HVMODE when patching the code at
0x4500.
Also we remove the check for CPU_FTR_ARCH_206 since relocation on IRQs
are only available in arch 2.07 and beyond.
Thanks to benh for helping find this.
Signed-off-by: Michael Neuling
cc: sta...@kernel.org
diff
Anshuman,
IIRC there are new bits in the FSCR and HFSCR you need to enable for the
PMU and BRHB. Can you please check these are enabled?
Mikey
Anshuman Khandual wrote:
> Branch History Rolling Buffer (BHRB) is a new PMU feaure in
> IBM
> POWER8 processor which records the bran
This patch series implements split core mode on POWER8. This enables up to 4
subcores per core which can each independently run guests (per guest SPRs like
SDR1, LPIDR etc are replicated per subcore). Lots more documentation on this
feature in the code and commit messages.
Most of this code is i
identical mechanism to block split core, rework the
secondary inhibit code to be a "HV KVM is active" check. We can then use
that in both the cpu hotplug code and the upcoming split core code.
Signed-off-by: Michael Ellerman
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/kvm_pp
deal
with the interrupt later.
Signed-off-by: Michael Ellerman
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/processor.h | 2 +-
arch/powerpc/kernel/idle_power7.S| 9 +
arch/powerpc/platforms/powernv/smp.c | 2 +-
3 files changed, 11 insertions(+), 2 deletions(-)
diff
a guest.
Unlike threads_per_core which is fixed at boot, threads_per_subcore can
change while the system is running. Most code will not want to use
threads_per_subcore.
Signed-off-by: Michael Ellerman
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/cputhreads.h | 7 +++
arch
to
online cpus which are not the primary thread within their *sub* core.
On POWER7 and other systems that do not support split core,
threads_per_subcore == threads_per_core and so the check is equivalent.
Signed-off-by: Michael Ellerman
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel
given the current split
core mode.
Although threads_per_subcore can change during the life of the system,
the commit that enables that will ensure that threads_per_subcore does
not change during the life of a KVM VM.
Signed-off-by: Michael Ellerman
Signed-off-by: Michael Neuling
---
arch
mpe.
Signed-off-by: Michael Ellerman
Signed-off-by: Michael Neuling
Signed-off-by: Srivatsa S. Bhat
Signed-off-by: Mahesh Salgaonkar
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/reg.h | 9 +
arch/powerpc/platforms/powernv/Makefile | 2 +-
arc
Joel Stanley wrote:
> Hi Mikey,
>
> On Thu, Apr 24, 2014 at 11:02 AM, Michael Neuling wrote:
> > +static DEVICE_ATTR(subcores_per_core, 0600,
> > + show_subcores_per_core, store_subcores_per_core);
>
> Can we make this 644, so users can query the st
here is some problem in the way thread->dscr
context
> > is saved away inside the TM section. Will look into this problem
further and
> > keep informed.
>
> Reason behind this inconsistent DSCR register value is because of the
following commit
> where the kernel reverts the DSC
That's not what that patch does. It shouldn't make any user visible changes
to DSCR or PPR.
Over syscall PPR and DSCR may change. Depending on your test case, that may
be your problem.
Mikey
On 29 Apr 2014 18:02, "Anshuman Khandual"
wrote:
> On 04/29/2014 12:36 PM
Anshuman Khandual wrote:
> On 04/29/2014 01:52 PM, Michael Neuling wrote:
> > That's not what that patch does. It shouldn't make any user visible changes
> > to DSCR or PPR.
>
> It may not when it runs uninterrupted but after the tracee process has
> stopped
> This patch series implements split core mode on POWER8. This enables up to 4
> subcores per core which can each independently run guests (per guest SPRs like
> SDR1, LPIDR etc are replicated per subcore). Lots more documentation on this
> feature in the code and commit messages.
>
> Most of th
Aneesh Kumar K.V wrote:
> Runtime disable transactional memory feature looking at pa-features
> device tree entry. This provides a mechanism to disable TM on P8
> systems.
What are we actually achieving with this?
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/kernel/prom.c | 5 +
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