Re: [PATCH V2] powerpc/irq: Enable some more exceptions in /proc/interrupts interface

What's the performance impact of this? If you run this test with --fp, --altivec or --vector what is the impact of adding this patch? http://ozlabs.org/~anton/junkcode/context_switch2.c eg ./context_switch2 --fp 0 0 Mikey On Thu, 2015-07-09 at 15:16 +0530, Anshuman Khandual wrote: > This p

Re: [PATCH] cxl: Remove use of macro DEFINE_PCI_DEVICE_TABLE

t performs this transformation > is as follows: > > @@ > identifier a; > declarer name DEFINE_PCI_DEVICE_TABLE; > initializer i; > @@ > - DEFINE_PCI_DEVICE_TABLE(a) > + const struct pci_device_id a[] > = i; > > Signed-off-by: Vaishali Thakkar Looks good, thanks! Ack

Re: [PATCH] Fix crash due to processing "memory-controller" nodes as "memory"

On Wed, 2015-07-22 at 08:39 +0800, jer...@ozlabs.au.ibm.com wrote: > Hi Anton, > > > [PATCH] Fix crash due to processing "memory-controller" nodes as "memory" > > Looks good to me. If you apply this to your kexec-lite repo, I'll update > op-build to use the new version, and send the merge request

Re: [PATCH 1/8] misc: cxl: clean up afu_read_config()

On Mon, 2015-07-27 at 00:18 +0300, Vladimir Zapolskiy wrote: > The sanity checks for overflow are not needed, because this is done on > caller side in fs/sysfs/file.c > > Signed-off-by: Vladimir Zapolskiy > Cc: linuxppc-dev@lists.ozlabs.org > Cc: Ian Munsie > Cc: Micha

Re: [PATCH] cxl: Don't ignore add_process_element result when attaching context

On Wed, 2015-07-29 at 14:40 +1000, Daniel Axtens wrote: > On Wed, 2015-07-29 at 14:25 +1000, Michael Ellerman wrote: > > On Wed, 2015-07-29 at 14:07 +1000, Daniel Axtens wrote: > > > Previously, when attaching a context in dedicated mode, we ignored > > > > Previously? You mean currently? Now is b

Re: [PATCH] cxl: Add alternate MMIO error handling

ffset after any reads to a read/write offset. > > Due to these constraints, this functionality must be explicitly > requested by userspace when starting the context by passing in the > CXL_START_WORK_ERR_FF flag. > > Signed-off-by: Ian Munsie Acked-by: Michael Neuling

Re: [PATCH 1/4] cxl: Compile with -Werror

On Fri, 2015-08-07 at 13:18 +1000, Daniel Axtens wrote: > It's a good idea, and it brings us in line with the rest of arch/powerpc. Do you need to put this patch last so that you don't break bisecting the series? Mikey > Signed-off-by: Daniel Axtens > --- > drivers/misc/cxl/Makefile | 2 ++ >

Re: [PATCH 1/4] cxl: Compile with -Werror

On Fri, 2015-08-07 at 13:18 +1000, Daniel Axtens wrote: > It's a good idea, and it brings us in line with the rest of arch/powerpc. > > Signed-off-by: Daniel Axtens Acked-by: Michael Neuling > --- > drivers/misc/cxl/Makefile | 2 ++ > 1 file changed, 2 insertions(+) &g

Re: [PATCH 3/4] cxl: sparse: Flag iomem pointers properly

vers/misc/cxl/vphb.c:220:23:expected void > [noderef] *cfg_data > /scratch/dja/linux-capi/drivers/misc/cxl/vphb.c:220:23:got void * > > Fix those by flagging __iomem in the relevant casts. > > Signed-off-by: Daniel Axtens Acked-by: Michael Neuling > --- > dr

Re: [PATCH 4/4] cxl: sparse: Silence iomem warning in debugfs file creation

arning: cast > removes address space of expression > > The address space marker is added back in the file operations > (fops_io_u64). > > Silence the warning with __force. > > Signed-off-by: Daniel Axtens Acked-by: Michael Neuling > --- > drivers/misc/cxl/debug

Re: [PATCH 2/4] cxl: sparse: Make declarations static

t; /scratch/dja/linux-capi/drivers/misc/cxl/file.c:399:30: warning: symbol > 'afu_master_fops' was not declared. Should it be static? > > Make them static. > > Signed-off-by: Daniel Axtens Acked-by: Michael Neuling > --- > drivers/misc/cxl/file.c | 4 ++-- > dri

Re: [PATCH] cxl: Allow release of contexts which have been OPENED but not STARTED

On Tue, 2015-08-18 at 19:19 +1000, Michael Ellerman wrote: > On Tue, 2015-08-18 at 16:30 +1000, Andrew Donnellan wrote: > > If we open a context but do not start it (either because we do not attempt > > to start it, or because it fails to start for some reason), we are left > > with a context in st

Re: [PATCH 63/63] powerpc: Add pseries_le_defconfig

Anton Blanchard wrote: > This is the pseries_defconfig with CONFIG_CPU_LITTLE_ENDIAN enabled > and CONFIG_VIRTUALIZATION disabled (required until we fix some > endian issues in KVM). The CONFIG_VIRTUALIZATION disabling should be done in the Kconfig not here. I'm not that keen on another defcon

[PATCH 1/4] powerpc/tm: Add checkpointed versions of some SPRs to thread_struct

Transactional memory will restore the TAR, PPR and DSCR on transaction failure. Add these to the thread_struct for use in the future Signed-off-by: Michael Neuling Cc: --- arch/powerpc/include/asm/processor.h | 4 arch/powerpc/kernel/asm-offsets.c| 3 +++ 2 files changed, 7

[PATCH 2/4] powerpc: Add new save_tar() register function.

Add save_tar() function to save the Target Address Register (TAR). This will be used in a future patch to save the TAR earlier than it currently is. Signed-off-by: Michael Neuling Cc: --- arch/powerpc/include/asm/switch_to.h | 5 + arch/powerpc/kernel/entry_64.S | 12

[PATCH 4/4] powerpc/tm: Save and restore checkpointed TAR, PPR and DSCR

Currently we don't save and restore the checkpointed TAR, PPR and DSCR. This adds the required save and restore to the treclaim and trechkpt code. Signed-off-by: Michael Neuling Cc: --- arch/powerpc/kernel/tm.S | 20 1 file changed, 20 insertions(+) diff --git a

[PATCH 3/4] powerpc: Save the TAR register earlier

This moves us to use the save_tar() function to save the Target Address Register (TAR) a lot earlier in __switch_to. We need to save the TAR earlier as we may overwrite it in the transactional memory reclaim/recheckpoint path. Signed-off-by: Michael Neuling Cc: --- arch/powerpc/kernel

Re: [PATCH 2/4] powerpc: Add new save_tar() register function.

> > +#ifdef CONFIG_PPC_BOOK3S_64 > > +_GLOBAL(_save_tar) > > + /* > > +* Back up the TAR across context switches. Note that the TAR is not > > +* available for use in the kernel. (To provide this, the TAR should > > +* be backed up/restored on exception entry/exit instead, and be in

[PATCH v2 1/4] powerpc/tm: Add checkpointed versions of some SPRs to thread_struct

Transactional memory will restore the TAR, PPR and DSCR on transaction failure. Add these to the thread_struct for use in the future Signed-off-by: Michael Neuling Cc: --- arch/powerpc/include/asm/processor.h | 4 arch/powerpc/kernel/asm-offsets.c| 3 +++ 2 files changed, 7

[PATCH v2 2/4] powerpc: Add new save_tar() register function.

Add save_tar() function to save the Target Address Register (TAR). This will be used in a future patch to save the TAR earlier than it currently is. Signed-off-by: Michael Neuling Cc: --- arch/powerpc/include/asm/switch_to.h | 9 + arch/powerpc/kernel/entry_64.S | 1 - 2 files

[PATCH v2 3/4] powerpc: Save the TAR register earlier

This moves us to use the save_tar() function to save the Target Address Register (TAR) a lot earlier in __switch_to. We need to save the TAR earlier as we may overwrite it in the transactional memory reclaim/recheckpoint path. Signed-off-by: Michael Neuling Cc: --- arch/powerpc/kernel

[PATCH v2 4/4] powerpc/tm: Save and restore checkpointed TAR, PPR and DSCR

Currently we don't save and restore the checkpointed TAR, PPR and DSCR. This adds the required save and restore to the treclaim and trechkpt code. Signed-off-by: Michael Neuling Cc: --- arch/powerpc/kernel/tm.S | 20 1 file changed, 20 insertions(+) diff --git a

Re: [PATCH 63/63] powerpc: Add pseries_le_defconfig

> > +CONFIG_SCHED_SMT=y > > +CONFIG_PPC_DENORMALISATION=y > > +CONFIG_HOTPLUG_PCI=m > Why the value "m" in the le_config file, when it is "y" in > pseries_defconfig. We are out of sync already!?!?! *sigh* ;-) > Also I do see a warning saying invalid value for this symbol. Mikey _

Re: [PATCH 63/63] powerpc: Add pseries_le_defconfig

Anton Blanchard wrote: > > Hi, > > > The CONFIG_VIRTUALIZATION disabling should be done in the Kconfig not > > here. > > > > I'm not that keen on another defconfig. benh is already talking about > > having a powernv defconfig. I'm worried we are going to fragment the > > defconfigs. If you

[PATCH v3 2/4] powerpc: Add new save_tar() register function.

powerpc: Add new save_tar() register function. Add save_tar() function to save the Target Address Register (TAR). This will be used in a future patch to save the TAR earlier than it currently is. Signed-off-by: Michael Neuling Cc: --- v3: remove whitespace screw age noticed by sfr diff --git

[PATCH v2 1/3] powerpc: Rework setting up H/FSCR bit definitions

, so reuse them. Signed-off-by: Michael Neuling --- v2: Fix bit numbers: -#define FSCR_TM_LG 6 -#define FSCR_PM_LG 5 -#define FSCR_BHRB_LG 4 +#define FSCR_TM_LG 5 +#define FSCR_PM_LG 4 +#define FSCR_BHRB_LG 3 diff --git a/arch/powerpc/include/asm/reg.h b/arch

[PATCH v3 3/3] powerpc: Correctly context switch DSCR on POWER8

rnel where we set thread.dscr_inherit in facility_unavailable_exception(). We also change _switch() so that we set or clear the H/FSCR DSCR bit based on the thread.dscr_inherit. Signed-off-by: Michael Neuling --- v3: remove unnecessary clearing of H/FSCR at boot. diff --git a/arch/powerpc/kerne

Re: [RFC] powerpc: put the common parts of the ppc64*defconfigs in a Kconfig file

Stephen Rothwell wrote: > We cannot put the unsetting of config options in the Kconfig file, nor > the integer or string options. > > I checked that after this we get the same .config files generated (except > for the addition of the new PPC64_DEFCONFIG* config options. > > Any thoughts? +1 M

[PATCH 2/5] powerpc: Rework setting up H/FSCR bit definitions

This reworks the Facility Status and Control Regsiter (FSCR) config bit definitions so that we can access the bit numbers. This is needed for a subsequent patch to fix the userspace DSCR handling. HFSCR and FSCR bit definitions are the same, so reuse them. Signed-off-by: Michael Neuling Cc

[PATCH 1/5] powerpc: Fix hypervisor facility unavaliable vector number

Below fixes this by duplication the required macros. Signed-off-by: Michael Neuling Cc: [v3.10] --- arch/powerpc/kernel/exceptions-64s.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 4e

[PATCH 3/5] powerpc: Fix context switch DSCR on POWER8

rnel where we set thread.dscr_inherit in facility_unavailable_exception(). We also change _switch() so that we set or clear the H/FSCR DSCR bit based on the thread.dscr_inherit. Signed-off-by: Michael Neuling Cc: [v3.10] --- arch/powerpc/kernel/entry_64.S | 27 +++- arch/powe

[PATCH 4/5] powerpc: Save the TAR register earlier

which will fix saving the TAR register when it's modified inside a transaction. Signed-off-by: Michael Neuling Cc: [v3.10] --- arch/powerpc/include/asm/switch_to.h | 9 + arch/powerpc/kernel/entry_64.S | 9 - arch/powerpc/kernel/process.c| 10 ++ 3

[PATCH 5/5] powerpc/tm: Fix context switching TAR, PPR and DSCR SPRs

Signed-off-by: Michael Neuling Cc: [v3.10] --- arch/powerpc/include/asm/processor.h | 4 arch/powerpc/kernel/asm-offsets.c| 3 +++ arch/powerpc/kernel/tm.S | 20 3 files changed, 27 insertions(+) diff --git a/arch/powerpc/include/asm/processor.h b/ar

[PATCH] powerpc: Avoid link stack corruption for MMU on exceptions

my userspace test with this patch. Signed-off-by: Michael Neuling diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index 07ca627..01ed463 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -48,17

[no subject]

ll be emulated by the kernel via the program check exception). On POWER8 and with CONFIG_RELOCATABLE=y, I get a ~10% performance improvement with my userspace test with this patch. Signed-off-by: Michael Neuling --- v2: fix comments as noticed by sfr diff --git a/arch/powerpc/include/asm/exc

[PATCH v2] powerpc: Avoid link stack corruption for MMU on exceptions

userspace test with this patch. Signed-off-by: Michael Neuling --- v2: fix comments as noticed by sfr Note to self, give emails a subject :-( diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index 07ca627..fe5e523 100644 --- a/arch/powerpc/include

Re: [PATCH] powerpc/powernv: Return secondary CPUs to firmware on kexec

> With OPAL v3 we can return secondary CPUs to firmware on kexec. This > allows firmware to do various cleanups making things generally more > reliable, and will enable the "new" kernel to call OPAL to perform > some reconfiguration tasks early on that can only be done while > all the CPUs are in f

Re: [PATCH] powerpc: Never handle VSX alignment exceptions from kernel

On Tue, Aug 20, 2013 at 4:05 PM, Anton Blanchard wrote: > > The VSX alignment handler needs to write out the existing VSX > state to memory before operating on it (flush_vsx_to_thread()). > If we take a VSX alignment exception in the kernel bad things > will happen. It looks like we could write th

Re: Detecting LD/ST instruction

> I am working on implementing the 'perf mem' command for Power > systems. This would for instance, let us know where in the memory > hierarchy (L1, L2, Local RAM etc) the data for a load/store > instruction was found (hit). > > On Power7, if the mcmcra[DCACHE_MISS] is clear _and_ the > instructio

Re: Detecting LD/ST instruction

Sukadev Bhattiprolu wrote: > Michael Neuling [mi...@neuling.org] wrote: > | > I am working on implementing the 'perf mem' command for Power > | > systems. This would for instance, let us know where in the memory > | > hierarchy (L1, L2, Local RAM etc) the data for

[PATCH] powerpc: DSCR FSCR cleanup

see no functional change from this but will get a minor speedup as they will trap into the kernel only once (rather than twice) when they first touch the DSCR. Also, this changes removes a bunch of ugly FTR_SECTION code. Signed-off-by: Michael Neuling -- arch/powerpc/kernel/entry_64.S | 31

Re: [PATCH] powerpc: Correct FSCR bit definitions

Paul Mackerras wrote: > Commit 74e400cee6 ("powerpc: Rework setting up H/FSCR bit definitions") > ended up with incorrect bit numbers for FSCR_PM_LG and FSCR_BHRB_LG. > This fixes them. > > Signed-off-by: Paul Mackerras Acked-by: Michael Neuling Sorry ab

Re: [PATCH] powerpc: net: filter: fix DIVWU instruction opcode

Vladimir Murzin wrote: > Currently DIVWU stands for *signed* divw opcode: > > 7d 2a 4b 96 divwu r9,r10,r9 > 7d 2a 4b d6 divwr9,r10,r9 > > Use the *unsigned* divw opcode for DIVWU. This looks like it's in only used in the BPF JIT code. Matt, any chance you an ACK/NACK this? Mikey

[PATCH] powerpc/tm: Switch out userspace PPR and DSCR sooner

m and trecheckpoint so that we run with user values for a much shorter period. More care is taken with the PPR as it's impact is greater than the DSCR. This is similar to user exceptions, where we run HTM_MEDIUM early to ensure that we don't run with a userspace PPR values in the kernel. Signed-

Re: Avoiding the dentry d_lock on final dput(), part deux: transactional memory

Ben, > On Mon, 2013-09-30 at 12:29 -0700, Linus Torvalds wrote: > > > > But I'm cc'ing the POWER people, because I don't know the POWER8 > > interfaces, and I don't want to necessarily call this "xbegin"/"xend" > > when I actually wrap it in some helper functions. > > The main problem with power

Re: Avoiding the dentry d_lock on final dput(), part deux: transactional memory

>> Well we don't have to, I think Mikey wasn't totally clear about that >> "making all registers volatile" business :-) This is just something we >> need to handle in assembly if we are going to reclaim the suspended >> transaction. Yeah, sorry. The slow path with all registers as volatile is onl

[PATCH 1/2] powerpc/tm: Remove interrupt disable in __switch_to()

We currently turn IRQs off in __switch_to(0 but this is unnecessary as it's already disabled in the caller. This removes the IRQ disable but adds a check to make sure it is really off in case this changes in future. Signed-off-by: Michael Neuling --- arch/powerpc/kernel/process.

[PATCH 2/2] powerpc/tm: Turn interrupts hard off in tm_reclaim()

We can't take IRQs in tm_reclaim as we might have a bogus r13 and r1. This turns IRQs hard off in this function. Signed-off-by: Michael Neuling --- arch/powerpc/kernel/tm.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/kernel/tm.S b/arch/powerpc/kernel/tm.S index 7b

Re: [PATCH 2/3] sched: Fix asymmetric scheduling for POWER7

of checking if the domain has an idle cpu, > because cpumask_first_and() will not yield any set bits if this domain > has no idle cpu. > > Hence, nr_busy check against group weight can be removed. > > Reported-by: Michael Neuling Tested-by: Michael Neuling Peter, I tested t

perf events ring buffer memory barrier on powerpc

Frederic, In the perf ring buffer code we have this in perf_output_get_handle(): if (!local_dec_and_test(&rb->nest)) goto out; /* * Publish the known good head. Rely on the full barrier implied * by atomic_dec_and_test() order the rb->head read a

Re: perf events ring buffer memory barrier on powerpc

> I would argue for: > > READ ->data_tailREAD ->data_head > smp_rmb() (A) smp_rmb() (C) > WRITE $data READ $data > smp_wmb() (B) smp_mb()(D) > STORE ->data_head WRITE -

Re: perf events ring buffer memory barrier on powerpc

ssued; but short of introducing more > conditional barrier primitives this is the best we can do. > > Cc: Mathieu Desnoyers > Cc: mich...@ellerman.id.au > Cc: Paul McKenney > Cc: Michael Neuling > Cc: Frederic Weisbecker > Cc: an...@samba.org > Cc: b...@kernel

Re: [PATCH] powerpc: memcpy optimization for 64bit LE

Philippe Bergheaud wrote: > Unaligned stores take alignment exceptions on POWER7 running in little-endian. > This is a dumb little-endian base memcpy that prevents unaligned stores. > It is replaced by the VMX memcpy at boot. Is this any faster than the generic version? Mikey > > Signed-off-b

Re: [PATCH] powerpc: memcpy optimization for 64bit LE

OK, can you add that and/or maybe antons description to the patch changelog? Mikey On Wed, Nov 6, 2013 at 9:21 PM, Philippe Bergheaud wrote: > Michael Neuling wrote: >> >> Philippe Bergheaud wrote: >> >> >>> Unaligned stores take alignment exceptions on

Re: [PATCH] powerpc: Remove a few lines of oops output

Anton Blanchard wrote: > > We waste quite a few lines in our oops output: > > ... > MSR: 80009032 CR: 28044024 XER: > SOFTE: 0 > CFAR: 9088 > DAR: 001c, DSISR: 4000 > > GPR00: c00c74f0 c0037cc1b010 c0d2bb30 >

Re: [RFC] Add IBM Blue Gene/Q Platform

> commit f6e3c1f706cb6922349d639a74ff6c50acc8b9f8 > Author: Jimi Xenidis > Date: Wed Dec 5 13:41:25 2012 -0500 > > powerpc: Remove unecessary VSX symbols > > The symbol THREAD_VSR0 is defined to be the same as THREAD_FPR0. Its > presence causes build issues with more complex c

Re: [RFC] Add IBM Blue Gene/Q Platform

> commit 279c0615917b959a652e81f4ad0d886e2d426d85 > Author: Jimi Xenidis > Date: Wed Dec 5 13:43:22 2012 -0500 > > powerpc/book3e: IBM Blue Gene/Q Quad Processing eXtention (QPX) > > This enables kernel support for the QPX extention and is intended for > processors that support

Re: [RFC] Add IBM Blue Gene/Q Platform

Michael Neuling wrote: > > commit 279c0615917b959a652e81f4ad0d886e2d426d85 > > Author: Jimi Xenidis > > Date: Wed Dec 5 13:43:22 2012 -0500 > > > > powerpc/book3e: IBM Blue Gene/Q Quad Processing eXtention (QPX) > > > > This enables k

Re: [RFC] Add IBM Blue Gene/Q Platform

Jimi Xenidis wrote: > Rather than flood the mailing list with the patches, I've arranged for a git > repo to hold the changesets. > You can find the repo here: > > > They are against GregKH's linux-stable.git long-term 3.4.y (y=22) branch. > The first 9 (6

Re: [RFC] Add IBM Blue Gene/Q Platform

Jimi Xenidis wrote: > > On Dec 6, 2012, at 11:41 PM, Michael Neuling wrote: > > >> commit f6e3c1f706cb6922349d639a74ff6c50acc8b9f8 > >> Author: Jimi Xenidis > >> Date: Wed Dec 5 13:41:25 2012 -0500 > >> > >>powerpc: Remove unecessa

Re: [RFC] Add IBM Blue Gene/Q Platform

Jimi Xenidis wrote: > > On Dec 6, 2012, at 11:54 PM, Michael Neuling wrote: > > >> commit 279c0615917b959a652e81f4ad0d886e2d426d85 > >> Author: Jimi Xenidis > >> Date: Wed Dec 5 13:43:22 2012 -0500 > >> > >>powerpc/

Re: [RFC] Add IBM Blue Gene/Q Platform

Jimi Xenidis wrote: > > On Dec 6, 2012, at 11:56 PM, Michael Neuling wrote: > > > Jimi Xenidis wrote: > > > >> Rather than flood the mailing list with the patches, I've arranged for a > >> git repo to hold the changesets. > >> You ca

Re: [RFC] Add IBM Blue Gene/Q Platform

Jimi Xenidis wrote: > > On Dec 7, 2012, at 7:38 AM, Jimi Xenidis wrote: > > > > > On Dec 6, 2012, at 11:54 PM, Michael Neuling wrote: > > > >>> commit 279c0615917b959a652e81f4ad0d886e2d426d85 > >>> Author: Jimi Xenidis > >>&g

Re: [RFC] Add IBM Blue Gene/Q Platform

Jimi Xenidis wrote: > > > On Dec 9, 2012, at 6:47 PM, Michael Neuling wrote: > > > Jimi Xenidis wrote: > > > >> > >> On Dec 7, 2012, at 7:38 AM, Jimi Xenidis wrote: > >> > >>> > >>>

[stable] [PATCH] powerpc/ptrace: Fix build with gcc 4.6

64-bit with and without VSX. commit e69b742a6793dc5bf16f6eedca534d4bc10d68b2 Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling cc: sta...@vger.kernel.org (for 3.0 only) --- Mr Stable: This seemed to miss 3.0 stable, please add... diff --git a/arch/powerpc/kernel/ptrace.c b/a

[PATCH 0/7] powerpc: add POWER8 DAWR support

Add support for the Data Address Watchpoint Register (DAWR) as found in POWER8. This replaces the DABR found in POWER7 and earlier and allows for wider watchpoint areas. -- 1.7.10.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://li

[PATCH 1/7] powerpc: Remove extra zeros from 32 bit CPU features definitions

These are 32 bit, so no need to have a bunch of wasted 0s. The 0s saved here can be put to better use elsewhere, like at the end of my pay check. Signed-off-by: Michael Neuling --- arch/powerpc/include/asm/cputable.h | 62 +-- 1 file changed, 31 insertions

[PATCH 2/7] powerpc: Repack 64bit CPU features to remove holes

This frees up 7 bits for crazy new CPU features. Signed-off-by: Michael Neuling --- arch/powerpc/include/asm/cputable.h | 50 +-- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm

[PATCH 3/7] powerpc: Add helper functions set the DAWR and CIABR using set_mode

From: Ian Munsie These are just wrappers around the new set_mode HCALL. Signed-off-by: Ian Munsie Signed-off-by: Michael Neuling --- arch/powerpc/platforms/pseries/plpar_wrappers.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/platforms/pseries

[PATCH 4/7] powerpc: Add DAWR CPU feature bit definition

.. and add it to POWER8 cpu features. Signed-off-by: Michael Neuling --- arch/powerpc/include/asm/cputable.h |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index d1f5911..2134e26 100644 --- a

[PATCH 5/7] powerpc: Add DAWR/X SPR number definitions

Signed-off-by: Michael Neuling --- arch/powerpc/include/asm/reg.h |5 + 1 file changed, 5 insertions(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index ce7b50e..6cae32d 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h

[PATCH 6/7] powerpc: Hardware breakpoints rewrite to handle non DABR breakpoint registers

BR in from userspace. We keep this functionality, so that future changes (like the POWER8 DAWR), will still fake the DABR to userspace. Signed-off-by: Michael Neuling --- arch/powerpc/include/asm/debug.h | 15 --- arch/powerpc/include/asm/hw_breakpoint.h | 33 +++---

[PATCH 7/7] powerpc: Add the DAWR support to the set_break()

This adds DAWR supoprt to the set_break(). It does both bare metal and PAPR versions of setting the DAWR. There is still some work we can do to make full use of the watchpoint but that will come later. Signed-off-by: Michael Neuling --- arch/powerpc/include/asm/machdep.h |4 arch

[PATCH] powerpc/ptrace: make #defines for all request numbers hex

We have a mix of decimal and hex here, so lets make them consistently hex. Also, strace will print them in hex if it can't decode them, so having them in hex here makes it easier to match up. No functional change. Signed-off-by: Michael Neuling diff --git a/arch/powerpc/include/uap

[PATCH 6/7] powerpc: Hardware breakpoints rewrite to handle non DABR breakpoint registers

BR in from userspace. We keep this functionality, so that future changes (like the POWER8 DAWR), will still fake the DABR to userspace. Signed-off-by: Michael Neuling --- Resending to fix a problem with 8xx defconfigs. Noticed by benh. arch/powerpc/include/asm/debug.h | 15 +++---

[PATCH] powerpc: rename set_break to avoid naming conflict

set_break' arch/powerpc/include/asm/debug.h:49:5: note: previous declaration of 'set_break' was here This renames set_break to set_breakpoint to avoid this naming conflict Signed-off-by: Michael Neuling Reported-by: Fengguang Wu diff --git a/arch/powerpc/include/asm/debug.h

[PATCH] powerpc: Fix typo in breakpoint kgdb code.

only once for each function it appears in Fix the typo. Signed-off-by: Michael Neuling --- Stupid error. I guess my defconfigs didn't compile this code... sorry. diff --git a/arch/powerpc/kernel/kgdb.c b/arch/powerpc/kernel/kgdb.c index a05f0e4..8747447 100644 --- a/arch/powerpc/kernel/

Re: linux-next: build failure after merge of the final tree (powerpc tree related)

Stephen Rothwell wrote: > Hi all, > > After merging the final tree, today's linux-next build (powerpc > allyesconfig) failed like this: > > arch/powerpc/kernel/kgdb.c: In function 'kgdb_arch_exit': > arch/powerpc/kernel/kgdb.c:492:2: error: '__debugger_breakx_match' undeclared > (first use in

[PATCH 00/17] powerpc: Hardware transactional memory support for POWER8

POWER8 implements hardware transactional memory support. This patch series adds kernel support so that user programs can use this hardware transactional memory and the new state is properly context switched. It is not currently used by the kernel itself. This patch series was originally develope

[PATCH 01/17] powerpc: Add new CPU feature bit for transactional memory

Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- arch/powerpc/include/asm/cputable.h |7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 06f7fb9..71a498b 100644 --- a/arch/powerpc/include/asm

[PATCH 02/17] powerpc: Add new instructions for transactional memory

ns an abort reason. trecheckpoint allows us to inject into the checkpointed state as if it were at the tbegin. It does this by copying the current architected state into the checkpointed state. Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- arch/powerpc/include/asm/ppc-opcode.h |

[PATCH 03/17] powerpc: Add additional state needed for transactional memory to thread struct

Set of new archtected state for saving away on context switch. Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- arch/powerpc/include/asm/processor.h | 28 1 file changed, 28 insertions(+) diff --git a/arch/powerpc/include/asm/processor.h b/arch

[PATCH 04/17] powerpc: New macros for transactional memory support

This adds new macros for saving and restoring checkpointed architected state from and to the thread_struct. It also adds some debugging macros for when your brain explodes trying to debug your transactional memory enabled kernel. Signed-off-by: Matt Evans Signed-off-by: Michael Neuling

[PATCH 05/17] powerpc: Register defines for various transactional memory registers

Defines for MSR bits and transactional memory related SPRs TFIAR, TEXASR and TEXASRU. Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- arch/powerpc/include/asm/reg.h | 27 +++ 1 file changed, 27 insertions(+) diff --git a/arch/powerpc/include/asm/reg.h b

[PATCH 06/17] powerpc: Add transactional memory paca scratch register to show_regs

Add transactional memory paca scratch register to show_regs. This is useful for debugging. Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- arch/powerpc/include/asm/paca.h |1 + arch/powerpc/kernel/asm-offsets.c |1 + arch/powerpc/kernel/entry_64.S|4 arch

[PATCH 07/17] powerpc: Add helper functions for transactional memory context switching

Here we add the helper functions to be used when context switching. These allow us to fully reclaim and recheckpoint a transaction. Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- arch/powerpc/include/asm/reg.h |2 +- arch/powerpc/include/asm/tm.h | 20 +++ arch/powerpc

[PATCH 08/17] powerpc: Add FP/VSX and VMX register load functions for transactional memory

d for VMX registers. Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- arch/powerpc/kernel/fpu.S| 54 ++ arch/powerpc/kernel/vector.S | 51 +++ 2 files changed, 105 insertions(+) diff --git a/arch/po

[PATCH 09/17] powerpc: Add reclaim and recheckpoint functions for context switching transactional memory processes

Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- arch/powerpc/kernel/process.c | 112 + 1 file changed, 112 insertions(+) diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index cb11fed..14fabd1 100644 --- a/arch/powe

[PATCH 10/17] powerpc: Add transactional memory unavaliable execption handler

These should never happen since we always turn on MSR TM when in userspace. We don't do lazy TM. Hence if we hit this, we barf and kill the task as something's gone horribly wrong. Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- arch/powerpc/kernel/exceptions-64

[PATCH 11/17] powerpc: Assembler routines for FP/VSX/VMX unavailable during a transaction

P, VMX and VSX. It doesn't hook them into the rest of the code yet. Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- arch/powerpc/kernel/traps.c | 95 +++ 1 file changed, 95 insertions(+) diff --git a/arch/powerpc/kernel/traps.c b/arch

[PATCH 12/17] powerpc: Hook in new transactional memory code

This hooks the new transactional memory code into context switching, FP/VMX/VMX unavailable and exception return. Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- arch/powerpc/kernel/exceptions-64s.S | 48 -- arch/powerpc/kernel/fpu.S

[PATCH 13/17] powerpc: Add new transactional memory state to the signal context

This adds the new transactional memory archtected state to the signal context in both 32 and 64 bit. Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- arch/powerpc/include/asm/reg.h |1 + arch/powerpc/kernel/signal.h|8 + arch/powerpc/kernel/signal_32.c | 500

[PATCH 14/17] powerpc: Add transactional memory to POWER8 cpu features

Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- arch/powerpc/include/asm/cputable.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 71a498b..5ab77f4 100644 --- a/arch/powerpc

[PATCH 15/17] powerpc: Add config option for transactional memory

Kconfig option for transactional memory on powerpc. Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- arch/powerpc/Kconfig |8 1 file changed, 8 insertions(+) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 684fa64..349ed12 100644 --- a/arch/powerpc

[PATCH 16/17] powerpc: Add transactional memory to pseries and ppc64 defconfigs

Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- arch/powerpc/configs/ppc64_defconfig |2 ++ arch/powerpc/configs/pseries_defconfig |2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig index

[PATCH 17/17] powerpc: Documentation for transactional memory on powerpc

Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- Documentation/powerpc/transactional_memory.txt | 175 1 file changed, 175 insertions(+) create mode 100644 Documentation/powerpc/transactional_memory.txt diff --git a/Documentation/powerpc

[PATCH 1/2] powerpc: Add length setting to set_dawr

Currently we set the length field in the DAWR to 0 which defaults it to one double word (64bits) which is the same as the DABR. Change this so that we can set it to longer values as supported by the DAWR. Signed-off-by: Michael Neuling --- arch/powerpc/kernel/process.c | 10 +- 1

[PATCH 2/2] powerpc: Change hardware breakpoint to allow longer ranges

Change the hardware breakpoint code so that we can support wider ranged breakpoints. This means both ptrace and perf hardware breakpoints can use upto 512 byte long breakpoints when using the DAWR and only 8 byte when using the DABR. Signed-off-by: Michael Neuling --- arch/powerpc/include/asm

BOOKE KVM calling load_up_fpu from C?

Scott, I was looking at changing how load_up_fpu works and I found this in arch/powerpc/kvm/booke.h: static inline void kvmppc_load_guest_fp(struct kvm_vcpu *vcpu) { #ifdef CONFIG_PPC_FPU if (vcpu->fpu_active && !(current->thread.regs->msr & MSR_FP)) { load_up_fpu();

Re: BOOKE KVM calling load_up_fpu from C?

Bhushan Bharat-R65777 wrote: > > > > -Original Message- > > From: Linuxppc-dev [mailto:linuxppc-dev- > > bounces+bharat.bhushan=freescale@lists.ozlabs.org] On Behalf Of Michael > > Neuling > > Sent: Tuesday, February 12, 2013 8:59 AM > >

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