On 14 May 2013 11:09, "Stephen Rothwell" wrote:
>
> Hi Mikey,
>
> On Mon, 13 May 2013 17:09:59 +1000 Michael Neuling
wrote:
> >
> > This doesn't work for me but the below does:
> >
> > _GLOBAL(__bswapdi2)
> > rotlwi r9,r4,8
v3 changes:
Don't break 32 bit
v2 changes:
add __user to ptr to __get_user_inatomic()
Michael Neuling (3):
powerpc/perf: Move BHRB code into CONFIG_PPC64 region
powerpc/pmu: Fix order of interpreting BHRB target entries
powerpc/perf: Fix setting of "to" addresses
The new Branch History Rolling buffer (BHRB) code is only useful on 64bit
processors, so move it into the #ifdef CONFIG_PPC64 region.
This avoids code bloat on 32bit systems.
Signed-off-by: Michael Neuling
---
arch/powerpc/perf/core-book3s.c | 248 ---
1
This is a rewrite of the code to take this into account.
Signed-off-by: Michael Neuling
---
arch/powerpc/perf/core-book3s.c | 89 ---
1 file changed, 46 insertions(+), 43 deletions(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-boo
the offset of
a branch and calculate the target address.
This adds a function power_pmu_bhrb_to() to calculate the target/to address of
the corresponding I and B form branches. It handles branches in both user and
kernel spaces. It also plumbs this into the perf brhb reading code.
Signed-off-b
Peter Zijlstra wrote:
> On Wed, May 15, 2013 at 03:37:22PM +0200, Stephane Eranian wrote:
> > On Fri, May 3, 2013 at 2:11 PM, Peter Zijlstra
> > wrote:
> > > We should always have proper privileges when requesting kernel data.
> > >
> > > Cc: Andi Kleen
> > > Cc: eran...@google.com
> > > Signe
Peter Zijlstra wrote:
> On Wed, May 15, 2013 at 03:37:22PM +0200, Stephane Eranian wrote:
> > On Fri, May 3, 2013 at 2:11 PM, Peter Zijlstra
> > wrote:
> > > We should always have proper privileges when requesting kernel data.
> > >
> > > Cc: Andi Kleen
> > > Cc: eran...@google.com
> > > Signe
e dabrx.
Looking at the 970FX docs, it has the DABR but not DABRX. I didn't
realise that this config ever existed so I'm going to have to code
something up to fix it.
Meanwhile the below should get you going. Let me know if it works.
This patch is not for upstream.
Not-at-all-signed-
. We use
the top 64 bits for CPU FTR bits since only 64 bit CPUs have this.
Processors that don't have the DABRX will still work as they will fall
back to software filtering these breakpoints via perf_exclude_event().
Signed-off-by: Michael Neuling
Reported-by: "Gorelik, Jacob (335F)
Peter Zijlstra wrote:
> On Thu, May 16, 2013 at 05:36:11PM +0200, Stephane Eranian wrote:
> > On Thu, May 16, 2013 at 1:16 PM, Peter Zijlstra
> > wrote:
> > > On Thu, May 16, 2013 at 08:15:17PM +1000, Michael Neuling wrote:
> > >> Peter,
> > >>
&
Stephane Eranian wrote:
> On Fri, May 17, 2013 at 1:39 PM, Peter Zijlstra wrote:
> > On Fri, May 17, 2013 at 09:32:08PM +1000, Michael Neuling wrote:
> >> Peter Zijlstra wrote:
> >
> >> > Wouldn't it be mostly conditional branches that are the primar
Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> We need to use smb_rmb when looking at hpte slot array. Otherwise we could
> reorder the hpte_slot array load bfore even we marked the pmd trans huge.
Does this need to go back into the stable series?
Mikey
>
> Signed-off-by: Aneesh Kum
t the transaction go back to
userspace allowing the HW to roll back the transaction and tell the user of the
failure. This also adds new tm abort cause codes to report the reason of the
persistent error to the user.
Crappy test case here http://neuling.org/devel/junkcode/aligntm.c
Signed-off-by: Michael Ne
pec __initdata cpu_specs[] = {
> > .cpu_name = "POWER7+ (raw)",
> > .cpu_features = CPU_FTRS_POWER7,
> > .cpu_user_features = COMMON_USER_POWER7,
> > + .cpu_user_features = COMMON_USER2_POWER7,
>
> ^ Oops h
t the transaction go back to
userspace allowing the HW to roll back the transaction and tell the user of the
failure. This also adds new tm abort cause codes to report the reason of the
persistent error to the user.
Crappy test case here http://neuling.org/devel/junkcode/aligntm.c
Signed-off-by: Michael Ne
Peter Zijlstra wrote:
> On Thu, May 16, 2013 at 05:36:11PM +0200, Stephane Eranian wrote:
> > On Thu, May 16, 2013 at 1:16 PM, Peter Zijlstra
> > wrote:
> > > On Thu, May 16, 2013 at 08:15:17PM +1000, Michael Neuling wrote:
> > >> Peter,
> > >>
&
Peter Zijlstra wrote:
> On Wed, May 22, 2013 at 11:52:38AM +0530, Anshuman Khandual wrote:
> > Enables conditional branch filter support for POWER8
> > utilizing MMCRA register based filter and also invalidates
> > a BHRB branch filter combination involving conditional
> > branches.
> >
> > Sign
Bunch of fixes for transactional memory.
Michael Neuling (5):
powerpc/tm: Make room for hypervisor in abort cause codes
powerpc/tm: Update cause codes documentation
powerpc/tm: Abort on emulation and alignment faults
powerpc/tm: Move TM abort cause codes to uapi
powerpc/tm: Fix
PAPR carves out 0xff-0xe0 for hypervisor use of transactional memory software
abort cause codes. Unfortunately we don't respect this currently.
Below fixes this to move our cause codes to below this region.
Signed-off-by: Michael Neuling
Cc: # 3.9 only
---
arch/powerpc/include/asm/
Signed-off-by: Michael Neuling
Cc: # 3.9 only
---
Documentation/powerpc/transactional_memory.txt |1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/powerpc/transactional_memory.txt
b/Documentation/powerpc/transactional_memory.txt
index c907be4..84e04a0 100644
--- a
t the transaction go back to
userspace allowing the HW to roll back the transaction and tell the user of the
failure. This also adds new tm abort cause codes to report the reason of the
persistent error to the user.
Crappy test case here http://neuling.org/devel/junkcode/aligntm.c
Signed-off-by: Michael Ne
These cause codes are usable by userspace, so let's export to uapi.
Signed-off-by: Michael Neuling
Cc: # v3.9
---
arch/powerpc/include/asm/reg.h | 14 --
arch/powerpc/include/asm/tm.h |2 ++
arch/powerpc/include/uapi/asm/tm.h | 18 ++
3
any memory written between the tbegin and the
signal will be rolled back anyway.
For signals taken in non-TM or suspended mode, we use the
normal/non-checkpointed stack pointer.
Tested with 64 and 32 bit signals
Signed-off-by: Michael Neuling
Cc: # v3.9
---
Documentation/powerpc/transactional_
These cause codes are usable by userspace, so let's export to uapi.
Signed-off-by: Michael Neuling
Cc: # v3.9
--
v2:
add uapi/tm.h to Kbuild so it gets exported correctly
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index d0528e0..4a9e408 100644
--- a
Anshuman Khandual wrote:
> On 05/22/2013 02:29 PM, Anshuman Khandual wrote:
> >>
> >> Your description from patch 0 should be here.
> > Does it sound better ?
> >
> >>
> >>> - if ((br_privilege != 7) && (br_privilege != 0))
> >>> - return -1;
> >>> +
> >>> + if (br_privilege)
> >>> +
On context switch, we should have no prefetch streams leak from one
userspace process to another. This frees up prefetch resources for the
next process.
Based on patch from Milton Miller.
Signed-off-by: Michael Neuling
diff --git a/arch/powerpc/include/asm/ppc_asm.h
b/arch/powerpc/include
No code changes, just documenting what's happening a little better.
Signed-off-by: Michael Neuling
diff --git a/arch/powerpc/lib/copypage_power7.S
b/arch/powerpc/lib/copypage_power7.S
index 0ef75bf..395c594 100644
--- a/arch/powerpc/lib/copypage_power7.S
+++ b/arch/powerpc/lib/copypage_p
The following simplifies the denorm code by using macros to generate the long
stream of almost identical instructions.
This patch results in no changes to the output binary, but removes a lot of
lines of code.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/exceptions-64s.S | 80
POWER8 can take a denormalisation exception on any VSX registers.
This does the extra 32 VSX registers we don't currently handle.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/exceptions-64s.S | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/k
Michael Ellerman wrote:
> On Thu, May 30, 2013 at 03:34:27PM +1000, Michael Neuling wrote:
> > On context switch, we should have no prefetch streams leak from one
> > userspace process to another. This frees up prefetch resources for the
> > next process.
> >
>
s the additional state to the ptregs so it can be restored.
Signed-off-by: Michael Neuling
cc: # 3.9 only
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index 201385c..0bc961b 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -14
Benh,
Can you take this for 3.10 also?
Mikey
Michael Neuling wrote:
> Some CPUs have a DABR but not DABRX. Configuration are:
> - No 32bit CPUs have DABRX but some have DABR.
> - POWER4+ and below have the DABR but no DABRX.
> - 970 and POWER5 and above have DABR and DABRX.
&g
Benh and Nish,
This breaks all perf HW events on POWER8.
Please revert this. It's
2ac6f427ad837a69561160b282eff80d9f0c2466 upstream.
Noticed by mpe.
Mikey
Nishanth Aravamudan wrote:
> Maynard informed me that neither the oprofile kernel module nor oprofile
> userspace has been updated to sup
In 2ac6f42 powerpc/cputable: Fix oprofile_cpu_type on power8
we broke all power8 hw events.
This reverts this change and uses oprofile_type instead. Perf now works
on POWER8 again and oprofile will revert to using timers on POWER8.
Kudos to mpe this fix.
Signed-off-by: Michael Neuling
In 2ac6f42 powerpc/cputable: Fix oprofile_cpu_type on power8
we broke all power8 hw events.
This reverts this change and uses oprofile_type instead. Perf now works
on POWER8 again and oprofile will revert to using timers on POWER8.
Kudos to mpe this fix.
Signed-off-by: Michael Neuling
---
tag
benh,
Hold off on taking this for now... I'm seeing a crash with it on power7.
Mikey
Michael Neuling wrote:
> Currently sys_sigreturn() is transactional memory unaware, hence if we take a
> 32 bit signal without SIGINFO (non RT) inside a transaction, we don't restore
&g
On Thu, May 23, 2013 at 7:07 AM, Andy Lutomirski wrote:
> MSG_CMSG_COMPAT is (AFAIK) not intended to be part of the API --
> it's a hack that steals a bit to indicate to other networking code
> that a compat entry was used. So don't allow it from a non-compat
> syscall.
Dave & Linus
This is cau
benh,
FWIW this is fixing a regression from:
4474ef0 powerpc: Rework set_dabr so it can take a DABRX value as well
Mikey
Michael Neuling wrote:
> Some CPUs have a DABR but not DABRX. Configuration are:
> - No 32bit CPUs have DABRX but some have DABR.
> - POWER4+ and below have
Anshuman Khandual wrote:
> Completely ignore BHRB privilege state filter request as we are
> already configuring that with privilege state filtering attribute
> for the accompanying PMU event. This would help achieve cleaner
> user space interaction for BHRB.
>
> This patch fixes a situation lik
Andy Lutomirski wrote:
> I broke them in this commit:
>
> commit 1be374a0518a288147c6a7398792583200a67261
> Author: Andy Lutomirski
> Date: Wed May 22 14:07:44 2013 -0700
>
> net: Block MSG_CMSG_COMPAT in send(m)msg and recv(m)msg
>
> This patch adds __sys_sendmsg and __
Anshuman Khandual wrote:
> On 06/06/2013 10:26 AM, Michael Neuling wrote:
> > Anshuman Khandual wrote:
> >
> >> Completely ignore BHRB privilege state filter request as we are
> >> already configuring that with privilege state filtering attribute
> >>
a non transactional process and hence the top MSR
bits can contain junk.
This updates the 32 bit signal handling code to always write something to the
top MSR bits so that users know if the process is transactional or not and the
kernel can use it on signal return.
Signed-off-by: Michael Neuling
---
s the additional state to ptregs so it can be restored.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/signal_32.c | 28 +++-
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index 5bc819f..5b
is removes the stripping of these MSR TM bits.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/signal_32.c |7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index 5b0fbe2..b8279b3 100644
--- a/ar
e signal return code to always restore both contexts on 64 bit
signal return. It also ensures that the MSR TM bits are properly restored from
the signal context which they are not currently.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/signal_64.c |8 +---
1 file changed, 5 i
e signal return code to always restore both contexts on 32 bit
rt signal return.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/signal_32.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index b
Guenter Roeck wrote:
> On Fri, Jun 07, 2013 at 12:58:16PM -0700, Greg KH wrote:
> > I'm announcing the release of the 3.9.5 kernel.
> >
> > All users of the 3.9 kernel series must upgrade.
> >
> > The updated 3.9.y git tree can be found at:
> > git://git.kernel.org/pub/scm/linux/kernel/git/
Benjamin Herrenschmidt wrote:
> On Fri, 2013-06-07 at 20:36 +1000, Michael Neuling wrote:
> > Currently we clear out the MSR TM bits on signal return assuming that the
> > signal should never return to an active transaction.
> >
> > This is bogus as the user may do
Benjamin Herrenschmidt wrote:
> On Fri, 2013-06-07 at 20:36 +1000, Michael Neuling wrote:
> > Currently sys_sigreturn() is TM unaware. Therefore, if we take a 32 bit
> > signal
> > without SIGINFO (non RT) inside a transaction, on signal return we don't
> > re
a non transactional process and hence the top MSR
bits can contain junk.
This updates the 32 bit signal handling code to always write something to the
top MSR bits so that users know if the process is transactional or not and the
kernel can use it on signal return.
Signed-off-by: Michael Neuling
cc
s the additional state to ptregs so it can be restored.
Signed-off-by: Michael Neuling
cc: sta...@vger.kernel.org (v3.9 only)
---
arch/powerpc/kernel/signal_32.c | 30 +-
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/po
on.
This pulls out both MSR TM bits from the user supplied context rather than just
setting TM suspend. We pull out only the bits needed to ensure the user can't
do anything dangerous to the MSR.
Signed-off-by: Michael Neuling
cc: sta...@vger.kernel.org (v3.9 only)
---
arch/powerpc/kerne
e signal return code to always restore both contexts on 32 bit
rt signal return.
Signed-off-by: Michael Neuling
cc: sta...@vger.kernel.org (v3.9 only)
---
arch/powerpc/kernel/signal_32.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/signal_32.c b/arch
e signal return code to always restore both contexts on 64 bit
signal return. It also ensures that the MSR TM bits are properly restored from
the signal context which they are not currently.
Signed-off-by: Michael Neuling
cc: sta...@vger.kernel.org (v3.9 only)
---
arch/powerpc/kernel/sig
Grant,
In next-20130617 we are getting the below crash on POWER7. Bisecting,
points to this patch (d39046ec72 in next)
Any clues?
Mikey
Using pSeries machine description
Page sizes from device-tree:
base_shift=12: shift=12, sllp=0x, avpnm=0x, tlbiel=1, penc=0
base_shift=24: shift=
Michael Neuling wrote:
> Grant,
>
> In next-20130617 we are getting the below crash on POWER7. Bisecting,
> points to this patch (d39046ec72 in next)
Also, reverting just d39046ec72 fixes the crash in next-20130617.
Mikey
>
> Any clues?
>
> Mikey
>
>
>
Grant Likely wrote:
> On Tue, 18 Jun 2013 10:05:31 +0100, Grant Likely
> wrote:
> > On Tue, Jun 18, 2013 at 2:25 AM, Michael Neuling wrote:
> > > Michael Neuling wrote:
> > >
> > >> Grant,
> > >>
> > >> In next-20130617 we a
Sukadev Bhattiprolu wrote:
> From 9f1a8a16e0ef36447e343d1cd4797c2b6a81225f Mon Sep 17 00:00:00 2001
> From: Sukadev Bhattiprolu
> Date: Fri, 7 Jun 2013 13:26:31 -0700
> Subject: [PATCH 2/2] perf: Add support for the mem_xlvl field.
>
> A follow-on patch to adding perf_mem_data_src support for P
Suka,
One of these two patches breaks pmac32_defconfig and I suspect all other
32 bit configs (against mainline)
arch/powerpc/perf/core-book3s.c: In function 'record_and_restart':
arch/powerpc/perf/core-book3s.c:1632:4: error: passing argument 1 of
'ppmu->get_mem_data_src' from incompatible poin
Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> Book3E uses the hugepd at PMD level and don't encode pte directly
> at the pmd level. So it will find the lower bits of pmd set
> and the pmd_bad check throws error. Infact the current code
> will never take the free_hugepd_range call at al
Aruna Balakrishnaiah wrote:
> Currently the kernel provides the contents of p-series NVRAM only as a
> simple stream of bytes via /dev/nvram, which must be interpreted in user
> space by the nvram command in the powerpc-utils package. This patch set
> exploits the pstore subsystem to expose each p
Aneesh Kumar K.V wrote:
> Michael Neuling writes:
>
> > Aneesh Kumar K.V wrote:
> >
> >> From: "Aneesh Kumar K.V"
> >>
> >> Book3E uses the hugepd at PMD level and don't encode pte directly
> >> at the pmd level. So it
Aruna Balakrishnaiah wrote:
> Hi Michael,
>
> On Wednesday 19 June 2013 11:45 AM, Michael Neuling wrote:
> > Aruna Balakrishnaiah wrote:
> >> Currently the kernel provides the contents of p-series NVRAM only as a
> >> simple stream of bytes via /dev/nvram,
Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> When we collapse normal pages to hugepage, we first clear the pmd, then
> invalidate all
> the PTE entries. The assumption here is that any low level page fault will
> see pmd as
> none and take the slow path that will wait on mmap_sem. B
Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> We can find pte that are splitting while walking page tables. Return
> None pte in that case.
Can you expand on this more please. There are a lot of details below
like removing a ldarx/stdcx loop that should be better described here.
>
Aneesh Kumar K.V wrote:
> Michael Neuling writes:
>
> > Aneesh Kumar K.V wrote:
> >
> >> From: "Aneesh Kumar K.V"
> >>
> >> When we collapse normal pages to hugepage, we first clear the pmd, then
> >> invalidate all
> >&
> >> --- a/arch/powerpc/include/asm/kvm_book3s_64.h
> >> +++ b/arch/powerpc/include/asm/kvm_book3s_64.h
> >> @@ -162,33 +162,40 @@ static inline int hpte_cache_flags_ok(unsigned long
> >> ptel, unsigned long io_type)
> >> * Lock and read a linux PTE. If it's present and writable, atomically
> >
> Enable PSTORE in pseries_defconfig
Please add a "why" to your changelogs eg. "Now we have pstore support for
nvram on pseries, enable it in the default config"
"Why" you are changing something is more important than "what", since
you can always determine "what" is being changed, by looking at t
t.
This correctly clears extraneous IRQ before possibly setting it.
Signed-off-by: Michael Neuling
Reported-by: Edjunior Barbosa Machado
Cc: sta...@vger.kernel.org
---
arch/powerpc/kernel/hw_breakpoint.c |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/hw_breakpoint.c
b/arch
, hence the
length should be 1.
This ensures that the kernel will filter out any exact mode hardware breakpoint
matches on any addresses other than the requested one.
Signed-off-by: Michael Neuling
Reported-by: Edjunior Barbosa Machado
Cc: sta...@vger.kernel.org
---
arch/powerpc/kernel/ptrace.c
Aruna Balakrishnaiah wrote:
> Since now we have pstore support for nvram in pseries, enable it
> in the default config. With this config option enabled, pstore
> infra-structure will be used to read/write the messages from/to nvram.
>
> Signed-off-by: Aruna Balakrishnaiah
Ac
perf record -j any -e branch-misses:k ls
> perf perf.data perf.data.old test-mmap-ring
> [ perf record: Woken up 1 times to write data ]
> [ perf record: Captured and wrote 0.002 MB perf.data (~102 samples)]
>
> Signed-off-by: Anshuman Khandual
Acked-by: Michael Neuling
&g
> Signed-off-by: Anshuman Khandual
benh you might want to fix the spelling mistakes above
strcuture -> structure
popullated -> populated
Otherwise:
Acked-by: Michael Neuling
> ---
> arch/powerpc/perf/core-book3s.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(
SR RI is larger than
required to avoid the need for an extra costly mtmsrd.
Thanks to Paulus for suggesting this change.
Signed-off-by: Michael Neuling
diff --git a/arch/powerpc/kernel/tm.S b/arch/powerpc/kernel/tm.S
index 2da67e7..51be8fb 100644
--- a/arch/powerpc/kernel/tm.S
+++ b/arch/po
this error.
Signed-off-by: Michael Neuling
Reported-by: Edjunior Barbosa Machado
Cc: sta...@vger.kernel.org # 3.9+
diff --git a/arch/powerpc/kernel/hw_breakpoint.c
b/arch/powerpc/kernel/hw_breakpoint.c
index 1150ae7..f0b47d1 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc
Alexander Graf wrote:
>
> On 04.07.2013, at 08:15, Bharat Bhushan wrote:
>
> > From: Bharat Bhushan
> >
> > This patchset moves the debug registers in a structure, which allows
> > kvm to use same structure for debug emulation.
> >
> > Note: Earilier a patchset
> > "https://lists.ozlabs.org
Bharat Bhushan wrote:
> Signed-off-by: Bharat Bhushan
Acked-by: Michael Neuling
> ---
> arch/powerpc/kernel/process.c |2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
> i
Bharat Bhushan wrote:
> This way we can use same data type struct with KVM and
> also help in using other debug related function.
>
> Signed-off-by: Bharat Bhushan
Acked-by: Michael Neuling
> ---
> arch/powerpc/include/asm/processor.h | 38 +
> arc
Alexander Graf wrote:
>
> On 09.07.2013, at 06:24, Michael Neuling wrote:
>
> > Alexander Graf wrote:
> >
> >>
> >> On 04.07.2013, at 08:15, Bharat Bhushan wrote:
> >>
> >>> From: Bharat Bhushan
> >>>
> >>&g
POWER8 comes with two different PVRs. This patch enables the additional
PVR in the cputable.
The existing entry (PVR=0x4b) is renamed to POWER8E and the new entry
(PVR=0x4d) is given POWER8.
Signed-off-by: Michael Neuling
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm
Anshuman Khandual wrote:
> On 07/18/2013 07:01 AM, Michael Neuling wrote:
> > POWER8 comes with two different PVRs. This patch enables the additional
> > PVR in the cputable.
> >
> > The existing entry (PVR=0x4b) is renamed to POWER8E and the new entry
> > (PV
l, please ack.
It's not really my area of expertise, but it applies and compiles for me
and it's relatively simple, so FWIW...
Acked-by: Michael Neuling
>
>
> Alex
>
> > ---
> > v5->v6
> > - switch_booke_debug_regs() not guarded by the compiler swi
Anton Blanchard wrote:
>
> We always use VMX loads and stores to manage the high 32
> VSRs. Remove these unused macros.
>
> Signed-off-by: Anton Blanchard
Acked-by: Michael Neuling
> ---
>
> Index: b/arch/power
Anton Blanchard wrote:
>
> We want PPC_DENORMALISATION enabled when POWERNV is enabled,
> so update the Kconfig.
>
> Signed-off-by: Anton Blanchard
Acked-by: Michael Neuling
> ---
>
> Index
Below fixes this by duplication the required macros.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/exceptions-64s.S | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index 4e00d22..90
This reworks the Facility Status and Control Regsiter (FSCR) config bit
definitions so that we can access the bit numbers. This will be useful when
looking at the status in the facility unavailable interrupt.
HFSCR and FSCR versions are the same, so reuse them.
Signed-off-by: Michael Neuling
rnel where we set thread.dscr_inherit in
facility_unavailable_exception().
We also change _switch() so that we set or clear the H/FSCR DSCR bit based on
the thread.dscr_inherit.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/cpu_setup_power.S | 8 --
arch/powerpc/kernel/entry_64.S
Stephen Rothwell wrote:
> [This time from a good email address :-)]
>
> Hi Mikey,
>
> On Mon, 5 Aug 2013 17:28:06 +1000 Michael Neuling
> wrote:
> >
> > +++ b/arch/powerpc/kernel/traps.c
> > @@ -1296,43 +1294,56 @@ void vsx_unavailable_excepti
> > > };
> > > - char *facility, *prefix;
> > > + char *facility;
> > > u64 value;
> > > + u8 status;
> > > + bool hv;
> > >
> > > if (regs->trap == 0xf60) {
> > > value = mfspr(SPRN_FSCR);
> > > - prefix = "";
> > > + hv = false;
> > > } else {
> > > v
rnel where we set thread.dscr_inherit in
facility_unavailable_exception().
We also change _switch() so that we set or clear the H/FSCR DSCR bit based on
the thread.dscr_inherit.
Signed-off-by: Michael Neuling
diff --git a/arch/powerpc/kernel/cpu_setup_power.S
b/arch/powerpc/kernel/cpu_setup_pow
SCSI tree until this new config option is merged via the powerpc
tree. Hence all trees will be bisectable at all times.
Signed-off-by: Michael Neuling
diff --git a/drivers/misc/cxl/Kconfig b/drivers/misc/cxl/Kconfig
index a990b39..b6db9eb 100644
--- a/drivers/misc/cxl/Kconfig
+++ b/driver
Fix typo in debug print. p1->p2. No functional change.
Signed-off-by: Michael Neuling
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 1ef0164..8515791 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -204,7 +204,7 @@ static void dump_cxl_config_sp
On Thu, 2015-06-18 at 15:57 +1000, Michael Ellerman wrote:
> On Thu, 2015-06-18 at 15:15 +1000, Michael Neuling wrote:
> > Fix typo in debug print. p1->p2. No functional change.
>
> That's not "no functional change", it changes the behaviour, unless p2_base
On Mon, 2015-06-29 at 16:05 +0530, Maninder Singh wrote:
> static Anlaysis detected below error:-
> (error) Possible null pointer dereference: phb
>
> So, Use phb after NULL check.
>
> Signed-off-by: Maninder Singh
Thanks, looks good.
Acked-By: Michael Neuling
> --
On Thu, 2015-07-02 at 15:55 +1000, Daniel Axtens wrote:
> Before freeing p2n, test p2n, not p1n.
>
> Signed-off-by: Daniel Axtens
Nice catch but can you resend with a CC stable?
Mikey
>
> ---
>
> While a potentially nasty bug, this is only hit (at the moment)
> in cxl_remove, so it's probabl
On Fri, 2015-07-03 at 10:23 +1000, Michael Neuling wrote:
> On Thu, 2015-07-02 at 15:55 +1000, Daniel Axtens wrote:
> > Before freeing p2n, test p2n, not p1n.
> >
> > Signed-off-by: Daniel Axtens
>
> Nice catch but can you resend with a CC stable?
Actually stable is
> context switch instead of tm_orig_msr, thus allowing us to drop it from
> thread_struct structure. This patch does that change.
>
> Signed-off-by: Anshuman Khandual
Acked-by: Michael Neuling
Thanks!
> ---
> This issue came up in the discussion regarding ptrace interface for TM
l API usage. This causes the AFU structures to be freed when
they are actually still in use.
This fixes some kref warnings we've been seeing and spurious ErrIVTE IRQs.
Signed-off-by: Michael Neuling
---
mpe: This is for 4.2 fixes
drivers/misc/cxl/api.c | 12 +---
1 file
> [PATCH] rtc/rtc-opal: Disable rtc-alarms when opal doesn't support tpo
I'd prefer to avoid the double negative and extra words. ie.
rtc/opal: Enable alarms only when opal supports tpo
But looks good other than that.
Acked-by: Michael Neuling
On Wed, 2015-06-03 at 10:21 +
s NULL.
> - Therefore our attempt to check afu->enabled will blow up.
>
> Therefore, check if afu is a null pointer before dereferencing it.
>
> cc: STABLE
FYI This needs to be (see Documentation/stable_kernel_rules.txt):
Cc: sta...@vger.kernel.org
Other than that, looks
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