063 ("cxl: Export library to support IBM XSL")
Cc: sta...@vger.kernel.org # 4.13+
Signed-off-by: Frederic Barrat
---
drivers/misc/cxl/cxllib.c | 85 ++-
1 file changed, 55 insertions(+), 30 deletions(-)
diff --git a/drivers/misc/cxl/cxll
Le 03/04/2018 à 16:06, Laurent Dufour a écrit :
On 03/04/2018 15:54, Frederic Barrat wrote:
cxllib_handle_fault() is called by an external driver when it needs to
have the host resolve page faults for a buffer. The buffer can cover
several pages and VMAs. The function iterates over all the
Le 03/04/2018 à 16:40, Aneesh Kumar K.V a écrit :
On 04/03/2018 03:13 PM, Frederic Barrat wrote:
cxllib_handle_fault() is called by an external driver when it needs to
have the host process page faults for a buffer which may cover several
pages. Currently the function holds the mm->mmap_
Le 03/04/2018 à 17:31, Aneesh Kumar K.V a écrit :
On 04/03/2018 08:10 PM, Aneesh Kumar K.V wrote:
On 04/03/2018 03:13 PM, Frederic Barrat wrote:
cxllib_handle_fault() is called by an external driver when it needs to
have the host process page faults for a buffer which may cover several
pages
Le 12/04/2018 à 13:06, Philippe Bergheaud a écrit :
Skiboot used to set the default Tunnel BAR register value when capi mode
was enabled. This approach was ok for the cxl driver, but prevented other
drivers from choosing different values.
Skiboot versions > 5.11 will not set the default value
Le 18/04/2018 à 03:08, Alastair D'Silva a écrit :
From: Alastair D'Silva
This patch adds a CPU feature bit to show whether the CPU has
the TIDR register available, enabling as_notify/wait in userspace.
Signed-off-by: Alastair D'Silva
---
arch/powerpc/include/asm/cputable.h | 3 ++-
arch/
Le 18/04/2018 à 03:08, Alastair D'Silva a écrit :
From: Alastair D'Silva
Switch the use of TIDR on it's CPU feature, rather than assuming it
is available based on architecture.
Signed-off-by: Alastair D'Silva
---
Reviewed-by: Frederic Barrat
arch/powerpc/
ent with the
above (at the minimum) :-)
With a comment:
Reviewed-by: Frederic Barrat
Fred
Signed-off-by: Alastair D'Silva
---
arch/powerpc/include/asm/switch_to.h | 1 -
arch/powerpc/kernel/process.c| 97 +---
2 files changed, 1 insertion(+),
Le 18/04/2018 à 03:08, Alastair D'Silva a écrit :
From: Alastair D'Silva
The function removes the process element from NPU cache.
Signed-off-by: Alastair D'Silva
---
Acked-by: Frederic Barrat
arch/powerpc/include/asm/pnv-ocxl.h | 2 +-
arch/powerpc/platforms/pow
Le 18/04/2018 à 03:08, Alastair D'Silva a écrit :
From: Alastair D'Silva
In order to successfully issue as_notify, an AFU needs to know the TID
to notify, which in turn means that this information should be
available in userspace so it can be communicated to the AFU.
Signed-off-by: Alastair
-
Intended?
Other than that,
Acked-by: Frederic Barrat
mmap
diff --git a/drivers/misc/ocxl/file.c b/drivers/misc/ocxl/file.c
index eb409a469f21..33ae46ce0a8a 100644
--- a/drivers/misc/ocxl/file.c
+++ b/drivers/misc/ocxl/file.c
@@ -168,12 +168,32 @@ static long afu_ioctl_enable
Le 18/04/2018 à 03:08, Alastair D'Silva a écrit :
From: Alastair D'Silva
Signed-off-by: Alastair D'Silva
---
Acked-by: Frederic Barrat
Fred
Documentation/accelerators/ocxl.rst | 11 +++
1 file changed, 11 insertions(+)
diff --git a/Documentation/accelerat
Le 11/05/2018 à 08:12, Alastair D'Silva a écrit :
From: Alastair D'Silva
This patch adds a CPU feature bit to show whether the CPU has
the TIDR register available, enabling as_notify/wait in userspace.
Signed-off-by: Alastair D'Silva
---
Reviewed-by: Frederic Barrat
Le 11/05/2018 à 08:12, Alastair D'Silva a écrit :
From: Alastair D'Silva
Switch the use of TIDR on it's CPU feature, rather than assuming it
is available based on architecture.
Signed-off-by: Alastair D'Silva
---
Reviewed-by: Frederic Barrat
arch/powerpc/
va
---
Thanks for adding the comment. It assumes the reader is aware that the
TIDR value is only used for the notification using the 'wait'
instruction, but that's likely to be the case.
Reviewed-by: Frederic Barrat
arch/powerpc/include/asm/switch_to.h | 1 -
arch/po
Le 11/05/2018 à 08:13, Alastair D'Silva a écrit :
From: Alastair D'Silva
The function removes the process element from NPU cache.
Signed-off-by: Alastair D'Silva
---
Acked-by: Frederic Barrat
arch/powerpc/include/asm/pnv-ocxl.h | 2 +-
arch/powerpc/platforms/pow
Le 11/05/2018 à 08:13, Alastair D'Silva a écrit :
From: Alastair D'Silva
In order to successfully issue as_notify, an AFU needs to know the TID
to notify, which in turn means that this information should be
available in userspace so it can be communicated to the AFU.
Signed-off-by: Alastair
Le 11/05/2018 à 08:13, Alastair D'Silva a écrit :
From: Alastair D'Silva
In order for a userspace AFU driver to call the POWER9 specific
OCXL_IOCTL_ENABLE_P9_WAIT, it needs to verify that it can actually
make that call.
Signed-off-by: Alastair D'Silva
---
Acked-by:
Le 11/05/2018 à 08:13, Alastair D'Silva a écrit :
From: Alastair D'Silva
Signed-off-by: Alastair D'Silva
---
Acked-by: Frederic Barrat
Documentation/accelerators/ocxl.rst | 11 +++
1 file changed, 11 insertions(+)
diff --git a/Documentation/accelerat
der
---
It looks ok, and it passed some basic testing.
Acked-by: Frederic Barrat
Fred
drivers/misc/cxl/context.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/misc/cxl/context.c b/drivers/misc/cxl/context.c
index 7ff315a..c6ec872 100644
--- a/dri
Le 11/05/2018 à 12:06, Alastair D'Silva a écrit :
-Original Message-
From: Frederic Barrat
Sent: Friday, 11 May 2018 7:25 PM
To: Alastair D'Silva ; linuxppc-dev@lists.ozlabs.org
Cc: linux-ker...@vger.kernel.org; linux-...@vger.kernel.org;
mi...@neuling
the
value already set) and new skiboot. Thanks!
Acked-by: Frederic Barrat
v2: Restrict tunnel bar setting to power9.
Do not fail cxl_configure_adapter() on tunnel bar setting error.
Log an info message instead, and continue configuring capi mode.
v3: No change.
---
drivers/misc/
Le 25/04/2018 à 13:08, Philippe Bergheaud a écrit :
Failure to synchronize the tunneled operations does not prevent
the initialization of the cxl card. This patch reports the tunneled
operations status via /sys.
Signed-off-by: Philippe Bergheaud
---
Good idea, but you'll have to also edit
D
documentation.
Acked-by: Frederic Barrat
v3: Added this patch to report the tunneled operations status.
v4: Updated Documentation/ABI/testing/sysfs-class-cxl.
---
Documentation/ABI/testing/sysfs-class-cxl | 8
drivers/misc/cxl/cxl.h| 1 +
drivers/misc/cxl/pci.c
ined.
Hence, since the prefaulting mechanism doesn't makes sense of
radix-mode, this patch updates prefault_mode_store() to not allow any
other value apart from CXL_PREFAULT_NONE when radix mode is enabled.
Cc:
Fixes: f24be42aab37 ("cxl: Add psl9 specific code")
Signed-off-by: Vai
Le 16/09/2016 à 06:28, Michael Neuling a écrit :
Fred has taken over the cxl maintenance I was doing. This updates the
MAINTAINERS file to reflect this.
It also removes a duplicate entry in the files covered.
Signed-off-by: Michael Neuling
Acked-by: Frederic Barrat
n the card, as the cache would likely get new dirty cache
lines immediately, but if resetting an idle adapter, it should avoid
any bad surprises from data left over from terminated Process Elements.
Signed-off-by: Frederic Barrat
---
drivers/misc/cxl/cxl.h| 6 +-
drivers/misc/cxl/native.c
Hi Vaibhav,
Le 04/10/2016 à 07:49, Vaibhav Jain a écrit :
Hi Fred,
Frederic Barrat writes:
+ /* the adapter is about to be reset, so ignore errors */
+ cxl_data_cache_flush(adapter);
+
Will be a good idea if we return error and not let the reset to proceed,
if
n the card, as the cache would likely get new dirty cache
lines immediately, but if resetting an idle adapter, it should avoid
any bad surprises from data left over from terminated Process Elements.
Signed-off-by: Frederic Barrat
---
Changelog:
v2:
- fix typo in commit message
- use ETIMEDOUT in
Hi Vaibhav,
A few comments below...
Le 10/10/2016 à 16:09, Vaibhav Jain a écrit :
This patch prevents resetting the cxl adapter via sysfs in presence of
one or more active cxl_context on it. This protects against an
unrecoverable error caused by PSL owning a dirty cache line even after
reset
ping? The patch still applies cleanly on recent trees.
Fred
Le 17/06/2016 à 18:53, Frederic Barrat a écrit :
If a cxl adapter faults on an invalid address for a kernel context, we
may enter copro_calculate_slb() with a NULL mm pointer (kernel
context) and an effective address which looks
Le 13/10/2016 à 12:51, Michael Ellerman a écrit :
Frederic Barrat writes:
ping? The patch still applies cleanly on recent trees.
Fell through the cracks :/
Fixes: ?
Nothing obvious. Current code was introduced by
73d16a6e0e51990cbe13f8d8f43bd5329bbab30a
but it was apparently moved
-ed out at that point.
Signed-off-by: Vaibhav Jain
Looks good to me, thanks! And sorry, I could have saved you an iteration.
Reviewed-by: Frederic Barrat
Actually, I guess I'm supposed to do that now:
Acked-by: Frederic Barrat
Fred
the error path.
Fixes: 7b8ad495("cxl: Fix DSI misses when the context owning task exits")
Cc: sta...@vger.kernel.org
Reviewed-by: Andrew Donnellan
Reported-by: Frederic Barrat
Signed-off-by: Vaibhav Jain
---
Thanks for taking care of it!
Acked-by: Frederic Barrat
Le 30/10/2016 à 22:34, Christophe JAILLET a écrit :
'cxl_dev_context_init()' returns an error pointer in case of error, not
NULL. So test it with IS_ERR.
Signed-off-by: Christophe JAILLET
Acked-by: Frederic Barrat
Le 30/10/2016 à 22:40, Christophe JAILLET a écrit :
'cxl_dev_context_init()' returns an error pointer in case of error, not
NULL. So test it with IS_ERR.
Signed-off-by: Christophe JAILLET
---
Thanks for the 3 patches!
Acked-by: Frederic Barrat
hile fixing it, simplify a bit the code.
Signed-off-by: Christophe JAILLET
---
Acked-by: Frederic Barrat
about to be
reset and context activation is error-ed out at that point.
Cc: sta...@vger.kernel.org
Fixes: 62fa19d4 ("cxl: Add ability to reset the card")
Acked-by: Frederic Barrat
Reviewed-by: Andrew Donnellan
Signed-off-by: Vaibhav Jain
When I inject an EEH error, this patch causes the foll
address_space. The pseudo filesystem
is only mounted on the first allocation of a file descriptor by
cxl_get_fd().
Tested with cxlflash.
Signed-off-by: Frederic Barrat
---
drivers/misc/cxl/api.c | 138 +
drivers/misc/cxl/context.c | 17 --
driv
address_space. The pseudo filesystem
is only mounted on the first allocation of a file descriptor by
cxl_get_fd().
Tested with cxlflash.
Signed-off-by: Frederic Barrat
---
Resending as many people apparently didn't receive it, though it shows
up in the list archiv
/irq.c:107:3-23: WARNING: Assignment of bool to 0/1
drivers/misc/cxl/native.c:57:2-3: Unneeded semicolon
drivers/misc/cxl/native.c:170:2-3: Unneeded semicolon
Signed-off-by: Andrew Donnellan
---
Thanks!
Acked-by: Frederic Barrat
term, we should consider opening up the cxl kernel
API to give access to the new pci API so that it can be tuned by the AFU
driver directly, since it would know better than cxl what the proper vpd
access timeout should be.
Acked-by: Frederic Barrat
Fred
Hi Ian,
diff --git a/drivers/misc/cxl/guest.c b/drivers/misc/cxl/guest.c
index c0cdf3c..04f6dff 100644
--- a/drivers/misc/cxl/guest.c
+++ b/drivers/misc/cxl/guest.c
@@ -552,6 +552,17 @@ static int attach_afu_directed(struct cxl_context *ctx,
u64 wed, u64 amr)
elem->common.sstp0 = cpu
Hi Ian,
The principle is fine, but the cxl_start_context2 API bothers me a bit.
Would something similar to this make sense, I think it would keep the
API cleaner:
/* new kernel-only API */
void cxl_set_translation_mode(struct cxl_context *ctx, bool real_mode)
For mlx5, the call sequence woul
l with -ENOMEM.
You're right, all is fine.
Reviewed-by: Frederic Barrat
Fred
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.
This will be used by the upcoming cxl support in the mlx5 driver.
Signed-off-by: Ian Munsie
Looks good to me.
Reviewed-by: Frederic Barrat
Fred
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: Frederic Barrat
Fred
---
drivers/misc/cxl/api.c| 12 +++-
drivers/misc/cxl/cxl.h| 1 +
drivers/misc/cxl/guest.c | 1 +
drivers/misc/cxl/native.c | 74 +--
4 files changed, 71 insertions(+), 17 deletions(-)
diff --git a/drivers/misc
Hi Ian,
It looks good, just one question:
+/* XSL registers (Mellanox CX4) */
+static const cxl_p1_reg_t CXL_XSL_Timebase = {0x0100};
+static const cxl_p1_reg_t CXL_XSL_TB_CTLSTAT = {0x0108};
+static const cxl_p1_reg_t CXL_XSL_FEC = {0x0158};
+static const cxl_p1_reg_t CXL_XSL_DSNCTL
Tested by cxlflash on bare-metal and powerVM.
Signed-off-by: Frederic Barrat
---
drivers/misc/cxl/vphb.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/misc/cxl/vphb.c b/drivers/misc/cxl/vphb.c
index cdc7723..012b6aa 100644
--- a/drivers/misc
lsvpd shows:
# lsvpd -l sg16
...
*YL U78C9.001.WZS09XA-P1-C7-B1-T0-L3
where C7 is the PCI slot of the cxl adapter.
On powerVM, the vPHB was already using the adapter device node, so
there's no change there.
Tested by cxlflash on bare-metal and powerVM.
Signed-off-by: Frede
eason to crash either. So return an error,
so that cxl can ack the interrupt with an address error.
Signed-off-by: Frederic Barrat
Cc:
---
arch/powerpc/mm/copro_fault.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/mm/copro_fault.c b/arch/powerpc/mm/copro_fault.c
index 65
), since their developers are less likely to have cared
about this value at all.
Signed-off-by: Ian Munsie
Reviewed-by: Frederic Barrat
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small enough to fit in one page.
Fix the algorithm to start the search at 1 page.
Signed-off-by: Ian Munsie
Reviewed-by: Frederic Barrat
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with an MMIO write if it is
still asserted after any AFU control operation.
Signed-off-by: Ian Munsie
OK, should be safe and valid even on non-xsl hardware.
Reviewed-by: Frederic Barrat
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Hi Ian,
-static int afu_control(struct cxl_afu *afu, u64 command,
+static int afu_control(struct cxl_afu *afu, u64 command, u64 clear,
u64 result, u64 mask, bool enabled)
I'm not a big fan of the new "clear" argument, which forces us to pass
an extra 0 most of the time.
Le 30/06/2016 17:32, Ian Munsie a écrit :
For dedicated mode, the CAIA recommends an explicit reset of the AFU
>(section 2.1.1).
True, I had forgotten that procedure was added to the document before it
was made public - I'll update the comment and resend.
Actually, my point was that for ded
It looks good to me. I can live with the extra 'clear' parameter,
because as you say, the approach I had suggested would require more
testing, so let's play safe for the time being.
And thanks for clarifying/fixing the deactivate paths.
Reviewed-by: Frederic Barrat
Fred
L
Salut Philippe,
Le 30/06/2016 13:45, Philippe Bergheaud a écrit :
+ if (cxl_slot_is_switched(dev)) {
+ dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring switched slot
device\n");
+ return -ENODEV;
+ }
I think it would be useful for the user who has insert
patch fixes Bz 142217.
Changes since v1:
- As suggested by Fred, tell user that CAPI adapter is misplaced
s/dev_dbg/dev_info/
Thanks!
Reviewed-by: Frederic Barrat
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Le 04/07/2016 17:07, Philippe Bergheaud a écrit :
Signed-off-by: Philippe Bergheaud
---
Changes since v1:
- Rebased on Ian's patch
"cxl: Abstract the differences between the PSL and XSL"
Thanks!
Reviewed-by: Frederic Barrat
_
-off-by: Ian Munsie
Reviewed-by: Frederic Barrat
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user of this API requires CAPP DMA mode.
Is it me or that last sentence is more complicated than it should? :-)
Anyway, I get it.
And the rest looks ok.
Reviewed-by: Frederic Barrat
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init flow.
Signed-off-by: Ian Munsie
Reviewed-by: Frederic Barrat
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initialised to make sure that it does not go away
during their lifetime.
Move the AFU refcount functions to base.c so they can be called from
the PHB code.
Signed-off-by: Ian Munsie
Reviewed-by: Frederic Barrat
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PHB code.
Signed-off-by: Ian Munsie
Reviewed-by: Frederic Barrat
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+ /* No special handling for cxl function: */
+ if (PCI_FUNC(dev->devfn) == 0)
+ return true;
I believe that is the first time we're getting a hint of the black magic
which is going to occur when the card is switched to cxl mode and the
appearance of a new pci func
Munsie
Reviewed-by: Frederic Barrat
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be used in a future patch.
Signed-off-by: Ian Munsie
Any way to add a check that the "set max" API is called before the
interrupts are allocated?
Reviewed-by: Frederic Barrat
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@@ -1572,6 +1575,9 @@ static pci_ers_result_t cxl_pci_error_detected(struct
pci_dev *pdev,
*/
for (i = 0; i < adapter->slices; i++) {
afu = adapter->afu[i];
+ /* Only participate in EEH if we are on a virtual PHB */
code, and to
reduce the number of APIs that need to be exported via base.c to allow
built in code to call.
Reviewed-by: Frederic Barrat
Just one typo below
diff --git a/include/misc/cxl.h b/include/misc/cxl.h
index fc07ed4..ed81a17 100644
--- a/include/misc/cxl.h
+++ b/include/misc/cxl.h
Le 04/07/2016 15:22, Ian Munsie a écrit :
From: Ian Munsie
The Mellanox CX4 in cxl mode uses a hybrid interrupt model, where
interrupts are routed from the networking hardware to the XSL using the
MSIX table, and from there will be transformed back into an MSIX
interrupt using the cxl style i
extending the XSL structure to include
a minimum PE to allocate. Although the bug is not in the XSL, it is the
easiest place to work around this limitation given that the CX4 is
currently the only card that uses an XSL.
Signed-off-by: Ian Munsie
Reviewed-by: Frederic Barrat
Le 04/07/2016 15:22, Ian Munsie a écrit :
From: Andrew Donnellan
Add a new API, cxl_check_and_switch_mode() to allow for switching of
bi-modal CAPI cards, such as the Mellanox CX-4 network card.
When a driver requests to switch a card to CAPI mode, use PCI hotplug
infrastructure to remove al
truct cxl_service_layer_ops to struct cxl so it's
accessible in both native and PowerVM environments. For the Mellanox CX-4,
set the min_pe value in set_sl_ops().
Fixes: f67a6722d650 ("cxl: Workaround PE=0 hardware limitation in Mellanox CX4")
Reported-by: Frederic Barrat
y: SF Markus Elfring
Reported-by: Julia Lawall
Signed-off-by: Andrew Donnellan
Thanks!
Reviewed-by: Frederic Barrat
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Le 29/07/2016 à 13:38, Michael Ellerman a écrit :
But who does keep a reference on the device_node? I can't see it anywhere. Which
means in theory the device_node can be freed out from under you.
You have a reference for afu_np as part of for_each_child_of_node(), but it's
dropped as soon as you
Switch the setting of psl_fir_cntl from debug to production
environment recommended value. It mostly affects the PSL behavior when
an error is raised in psl_fir1/2.
Tested with cxlflash.
Signed-off-by: Frederic Barrat
---
drivers/misc/cxl/pci.c | 9 ++---
1 file changed, 6 insertions(+), 3
's still doable since the API was
merged to 4.8 and the expected user (cxlflash) hasn't started using the
API yet.
Reviewed-by: Frederic Barrat
Fred
Le 09/08/2016 à 12:53, Michael Ellerman a écrit :
Frederic Barrat writes:
Switch the setting of psl_fir_cntl from debug to production
environment recommended value. It mostly affects the PSL behavior when
an error is raised in psl_fir1/2.
Tested with cxlflash.
Is this a fix you want in
Signed-off-by: Frederic Barrat
---
drivers/misc/cxl/pci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 6f0c4ac..cd922a8 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -1530,11 +1530,11 @@ s
- mark contexts used by XSL (cxllib) as needed global invalidation
RFC v2:
- address comments received
- rename MM_CONTEXT_GLOBAL_TLBI -> MM_GLOBAL_TLBIE
- add memory barriers to make sure the device doesn't miss any TLBI
- also add barrier for the hash implemention to fix the same is
U and CAPP/PSL. The NPU and the PSL keep their own translation cache
so they need to see all the TLBIs for those contexts.
Rename mm_is_thread_local() to mm_is_invalidation_local() to better
describe what it's doing.
Signed-off-by: Frederic Barrat
---
arch/powerpc/include/asm/book3
contexts actually used by the device.
So mark the contexts being attached to the cxl adapter as requiring
global TLBIs.
Signed-off-by: Frederic Barrat
---
drivers/misc/cxl/api.c| 12 ++--
drivers/misc/cxl/cxllib.c | 7 +++
drivers/misc/cxl/file.c | 12 ++--
3 files
xt to the device, therefore we are
exposed to re-ordering. It is highly unlikely as the use count for the
driver is incremented on open() and the attachment to the device
happens on a different system call (ioctl)
Signed-off-by: Frederic Barrat
---
include/misc/cxl-base.h | 22 +++-
guration magic is done on the
PHBs by skiboot.
Signed-off-by: Frederic Barrat
---
Requires skiboot patch:
700611a48025c5a556bb0aa011ac81bb5d1bcbc1
Changelog:
v4:
- resubmit with correct opal call IDs, now that the skiboot portion is merged
v3:
- move target reference count from skiboot to li
Le 24/07/2017 à 06:28, Benjamin Herrenschmidt a écrit :
Instead of comparing the whole CPU mask every time, let's
keep a counter of how many bits are set in the mask. Thus
testing for a local mm only requires testing if that counter
is 1 and the current CPU bit is set in the mask.
Signed-off-b
Hi Ben,
Le 24/07/2017 à 06:28, Benjamin Herrenschmidt a écrit :
Instead of comparing the whole CPU mask every time, let's
keep a counter of how many bits are set in the mask. Thus
testing for a local mm only requires testing if that counter
is 1 and the current CPU bit is set in the mask.
I'm
Le 21/08/2017 à 19:35, Benjamin Herrenschmidt a écrit :
On Mon, 2017-08-21 at 19:27 +0200, Frederic Barrat wrote:
Hi Ben,
Le 24/07/2017 à 06:28, Benjamin Herrenschmidt a écrit :
Instead of comparing the whole CPU mask every time, let's
keep a counter of how many bits are set in the
Le 21/08/2017 à 19:35, Benjamin Herrenschmidt a écrit :
On Mon, 2017-08-21 at 19:27 +0200, Frederic Barrat wrote:
Hi Ben,
Le 24/07/2017 à 06:28, Benjamin Herrenschmidt a écrit :
Instead of comparing the whole CPU mask every time, let's
keep a counter of how many bits are set in the
Le 24/08/2017 à 20:47, Benjamin Herrenschmidt a écrit :
On Thu, 2017-08-24 at 18:40 +0200, Frederic Barrat wrote:
The decrementing part is giving me troubles, and I think it makes sense:
if I decrement the counter when detaching the context from the capi
card, then the next TLBIs for the
Le 25/08/2017 à 09:44, Benjamin Herrenschmidt a écrit :
On Fri, 2017-08-25 at 06:53 +0200, Frederic Barrat wrote:
Le 24/08/2017 à 20:47, Benjamin Herrenschmidt a écrit :
On Thu, 2017-08-24 at 18:40 +0200, Frederic Barrat wrote:
The decrementing part is giving me troubles, and I think it
ented on
the detach path, so it makes more sense.
It affects only the user api. The kernel api is already doing The
Right Thing.
Signed-off-by: Frederic Barrat
Cc: sta...@vger.kernel.org # v4.2+
Fixes: 7bb5d91a4dda ("cxl: Rework context lifetimes")
---
drivers/misc/cxl/api.c | 4 +++
if possible and to avoid overflowing the
counter.
Signed-off-by: Frederic Barrat
diff --git a/arch/powerpc/include/asm/mmu_context.h
b/arch/powerpc/include/asm/mmu_context.h
index 309592589e30..6447c0df7ec4 100644
--- a/arch/powerpc/include/asm/mmu_context.h
+++ b/arch/powerpc/include/as
Le 28/08/2017 à 06:15, Vaibhav Jain a écrit :
Make sure to set the valid-bit in software-state field of the
populated PE. This was earlier missing for dedicated mode AFUs, hence
was causing a PSL freeze when the AFU was activated.
Signed-off-by: Vaibhav Jain
---
Acked-by: Frederic Barrat
Le 28/08/2017 à 14:03, Benjamin Herrenschmidt a écrit :
On Mon, 2017-08-28 at 10:47 +0200, Frederic Barrat wrote:
Signed-off-by: Frederic Barrat
diff --git a/arch/powerpc/include/asm/mmu_context.h
b/arch/powerpc/include/asm/mmu_context.h
index 309592589e30..6447c0df7ec4 100644
--- a
With the optimizations introduced by commit a46cc7a90fd8
("powerpc/mm/radix: Improve TLB/PWC flushes"), flush_tlb_mm() no
longer flushes the page walk cache with radix. This patch introduces
flush_all_mm(), which flushes everything, tlb and pwc, for a given mm.
Signed-off-by: Frede
ented on
the detach path, so it makes more sense.
It affects only the user api. The kernel api is already doing The
Right Thing.
Signed-off-by: Frederic Barrat
Cc: sta...@vger.kernel.org # v4.2+
Fixes: 7bb5d91a4dda ("cxl: Rework context lifetimes")
Acked-by: Andrew Donnellan
---
Cha
if possible and to avoid overflowing the
counter.
Signed-off-by: Frederic Barrat
---
Changelog:
v2: Replace flush_tlb_mm() by the new flush_all_mm() to flush the TLBs
and PWCs (thanks to Ben)
arch/powerpc/include/asm/mmu_context.h | 35 ++
arch/powerpc/m
I'm dropping this series, as there was a recent change done in the
memory context that I can reuse.
The follow up of the story is:
http://patchwork.ozlabs.org/patch/807570/
Fred
Le 02/08/2017 à 22:29, Frederic Barrat a écrit :
capi2 and opencapi require the TLB invalidations being sen
Le 30/08/2017 à 15:17, Michael Ellerman a écrit :
Frederic Barrat writes:
With the optimizations introduced by commit a46cc7a90fd8
("powerpc/mm/radix: Improve TLB/PWC flushes"), flush_tlb_mm() no
longer flushes the page walk cache with radix. This patch introduces
flush_all_m
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