Use M_TW instead of M_TWB for storing Level 1 table address as M_TWB requires
4k aligned tables, which is only the case with 4k pages.
Consequently, we have to calculate the level 1 table index by ourselves.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 48
This patch hiddes that SPR address needed for CPU6 ERRATA handling in the macro.
Then we don't have to worry about this address directly in the code.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 29 -
1 files changed, 16 insertions(+
Since coming 469d62be9263b92f2c3329540cbb1c076111f4f3, SPRG2 is used as a
scratch register just like SPRG0 and SPRG1. So Declare it as such and fix
the comment which is not valid anymore since that commit.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch
Exception InstructionAccess does not exist on MPC8xx. No need to branch there
from somewhere else.
Handling can be done directly in InstructionTLBError Exception.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- arch/powerpc/mm/fault.c uses the vector number, so
-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 104 --
1 files changed, 36 insertions(+), 68 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 1329c5a
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, r10 is not used anymore
after FixupDAR. There is therefore no need to set it up with the value of DAR.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |7 +++
1 files
This patchset:
1) provides several MMU TLB handling optimisation on MPC8xx.
2) adds support of 16k pages on MPC8xx.
All changes have been successfully tested on a custom board equipped with MPC885
Signed-off-by: Christophe Leroy
Tested-by: Christophe Leroy
---
Changes in v2:
- Patch number 10
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, dirty handling is not
handled here anymore. So we fix the comment.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |8 ++--
1 files changed, 2 insertions(+), 6
By XORing the upper part of the instruction code, we get a value that can
directly be verified with the second test and we can remove the first test.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |6 ++
1 files changed
DataAccess exception is never generated by MPC8xx so do the job directly where
it is used to avoid an unnecessary branching.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- arch/powerpc/mm/fault.c uses the vector number, so make sure it understands
the new ones
MD_TWC can only be used properly with 4k pages.
So lets calculate level 2 table index by ourselves.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- No need to save r11 in cr, we can do without modifying r11 in DataStoreTLBMiss
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 28
For PAGE size related operations, use PAGE size consts in order to be able to
use different page size in the futur.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 30 ++
1 files changed, 18
Branching takes two cycles on MPC8xx. Lets duplicate the two instructions
and avoid the branching.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch
Value 0x00f0 is used to force bits in TLB level 2 entry. This value is linked
to the page size and will vary when we change the page size. Lets define a const
for it in order to have it at only one place.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch
In DTLBError handler there is not need to restore r10, r11 and cr registers
after fixing DAR as they are saved again to the same place just after.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |4 ++--
1 files changed, 2
Use M_TW instead of M_TWB for storing Level 1 table address as M_TWB requires
4k aligned tables, which is only the case with 4k pages.
Consequently, we have to calculate the level 1 table index by ourselves.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch
r10 and r3 are only used inside FixupDAR function. So lets save them inside
that function only.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 27 +--
1 files changed, 13 insertions(+), 14 deletions
This patch activates the handling of 16k pages on the MPC8xx.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/Kconfig |2 +-
arch/powerpc/include/asm/mmu-8xx.h |2 ++
arch/powerpc/kernel/head_8xx.S |4
3 files
No need to re-set this bit at each TLB miss. Let's set it in the PTE.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- Removed PPC405 related macro from PPC8xx specific code
- PTE_NONE_MASK doesn't need PAGE_ACCESSED in Linux 2.6
arch/powerpc/include/a
There is not need to restore r10, r11 and cr registers at this end of ITLBmiss
handler as they are saved again to the same place in ITLBError handler we are
jumping to.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |8
When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit
during TLB loading is useless.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a
free the TLB as soon as
possible. This also has the advantage of removing some 8xx specific code from
fault.c
Signed-off-by: Christophe Leroy
---
Changes in v3:
- New
linux/arch/powerpc/kernel/head_8xx.S | 15 ++-
linux/arch/powerpc/mm/fault.c| 7 ---
2 files change
This patch hiddes that SPR address needed for CPU6 ERRATA handling in the macro.
Then we don't have to worry about this address directly in the code.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |
As we are not using anymore DAR to save registers, it is now available for
saving the r3 register used for CPU6 ERRATA handling. Therefore we can
remove the major hack which was to use memory location 0 to save r3.
Signed-off-by: Christophe Leroy
---
Changes in v3:
- New
linux/arch/powerpc
Le 17/09/2014 18:40, Scott Wood a écrit :
On Wed, 2014-09-17 at 18:36 +0200, Christophe Leroy wrote:
This patchset:
1) provides several MMU TLB handling optimisation on MPC8xx.
2) adds support of 16k pages on MPC8xx.
All changes have been successfully tested on a custom board equipped with
Le 18/09/2014 18:42, leroy christophe a écrit :
Le 18/09/2014 17:15, Joakim Tjernlund a écrit :
Christophe Leroy wrote on 2014/09/17 18:36:57:
Exception InstructionAccess does not exist on MPC8xx. No need to branch
there from somewhere else.
Handling can be done directly in
Le 18/09/2014 20:12, Joakim Tjernlund a écrit :
leroy christophe wrote on 2014/09/18 18:42:14:
Le 18/09/2014 17:15, Joakim Tjernlund a écrit :
Christophe Leroy wrote on 2014/09/17
18:36:57:
Exception InstructionAccess does not exist on MPC8xx. No need to
branch
there from somewhere
-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/kernel/head_8xx.S | 104 --
1 files changed, 36 insertions(+), 68 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel
This patchset:
1) provides several MMU TLB handling optimisation on MPC8xx.
2) adds support of 16k pages on MPC8xx.
All changes have been successfully tested on a custom board equipped with MPC885
Signed-off-by: Christophe Leroy
Tested-by: Christophe Leroy
---
Changes in v2:
- Patch number 10
Since coming 469d62be9263b92f2c3329540cbb1c076111f4f3, SPRG2 is used as a
scratch register just like SPRG0 and SPRG1. So Declare it as such and fix
the comment which is not valid anymore since that commit.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
Changes
Exception InstructionAccess does not exist on MPC8xx. No need to branch there
from somewhere else.
Handling can be done directly in InstructionTLBError Exception.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- arch/powerpc/mm/fault.c uses the vector number, so
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, r10 is not used anymore
after FixupDAR. There is therefore no need to set it up with the value of DAR.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/kernel/head_8xx.S
Branching takes two cycles on MPC8xx. Lets duplicate the two instructions
and avoid the branching.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/kernel/head_8xx.S |6 --
1 files changed, 4 insertions(+), 2
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, dirty handling is not
handled here anymore. So we fix the comment.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/kernel/head_8xx.S | 8 ++--
1 file changed, 2
DataAccess exception is never generated by MPC8xx so do the job directly where
it is used to avoid an unnecessary branching.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- arch/powerpc/mm/fault.c uses the vector number, so make sure it understands
the new ones
MD_TWC can only be used properly with 4k pages.
So lets calculate level 2 table index by ourselves.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- No need to save r11 in cr, we can do without modifying r11 in DataStoreTLBMiss
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc
Value 0x00f0 is used to force bits in TLB level 2 entry. This value is linked
to the page size and will vary when we change the page size. Lets define a const
for it in order to have it at only one place.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
Changes
There is not need to restore r10, r11 and cr registers at this end of ITLBmiss
handler as they are saved again to the same place in ITLBError handler we are
jumping to.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/kernel
free the TLB as soon as
possible. This also has the advantage of removing some 8xx specific code from
fault.c
Signed-off-by: Christophe Leroy
---
Changes in v3:
- New
Changes in v4:
- None (but impacted by changes in patch 3 and 7)
arch/powerpc/kernel/head_8xx.S | 15 ++-
arch/power
This patch hiddes that SPR address needed for CPU6 ERRATA handling in the macro.
Then we don't have to worry about this address directly in the code.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/kernel/head_8xx.S |
When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit
during TLB loading is useless.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/kernel/head_8xx.S |2 --
1 files changed, 0 insertions(+), 2
No need to re-set this bit at each TLB miss. Let's set it in the PTE.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- Removed PPC405 related macro from PPC8xx specific code
- PTE_NONE_MASK doesn't need PAGE_ACCESSED in Linux 2.6
Changes in v4:
- None
ar
As we are not using anymore DAR to save registers, it is now available for
saving the r3 register used for CPU6 ERRATA handling. Therefore we can
remove the major hack which was to use memory location 0 to save r3.
Signed-off-by: Christophe Leroy
---
Changes in v3:
- New
Changes in v4:
- Fixed
This patch activates the handling of 16k pages on the MPC8xx.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/Kconfig |2 +-
arch/powerpc/include/asm/mmu-8xx.h |2 ++
arch/powerpc/kernel/head_8xx.S
Use M_TW instead of M_TWB for storing Level 1 table address as M_TWB requires
4k aligned tables, which is only the case with 4k pages.
Consequently, we have to calculate the level 1 table index by ourselves.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
By XORing the upper part of the instruction code, we get a value that can
directly be verified with the second test and we can remove the first test.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/kernel/head_8xx.S |6
r10 and r3 are only used inside FixupDAR function. So lets save them inside
that function only.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/kernel/head_8xx.S | 27 +--
1 files changed, 13
In DTLBError handler there is not need to restore r10, r11 and cr registers
after fixing DAR as they are saved again to the same place just after.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/kernel/head_8xx.S |4
For PAGE size related operations, use PAGE size consts in order to be able to
use different page size in the futur.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/kernel/head_8xx.S | 30 ++
1
On PPC_8xx, lwz has a 2 cycles latency, and branching also takes 2 cycles.
As the size of the header is minimum 5 words, we can unroll the loop for the
first words to reduce number of branching, and we can re-order the instructions
to limit loading latency.
Signed-off-by: Christophe Leroy
This patchset provides a few optimisations related to IP checksum functions.
Signed-off-by: Christophe Leroy
Tested-by: Christophe Leroy
---
arch/powerpc/include/asm/checksum.h | 28
arch/powerpc/lib/checksum_32.S | 16
2 files changed, 28
csum_tcpudp_nofold()
function.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/checksum.h | 15 +++
arch/powerpc/lib/checksum_32.S | 16
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/checksum.h
b/arch/powerpc
include/net/checksum.h also offers the possibility to define an arch specific
function.
This patch provides a ppc32 specific csum_add() inline function.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/checksum.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch
This patchset:
1) Fix parameter ram offset setup for CPM1
2) Allow dynamic allocation of CPM1 parameter RAM
Tested on MPC885.
Signed-off-by: Christophe Leroy
---
linux/arch/powerpc/platforms/8xx/Kconfig | 11 +++
linux/drivers/spi/spi-fsl-cpm.c | 14 +-
2 files
that doesn't
set SPI_BASE, pram_ofs was not properly set. This patch fixes this confusion.
Signed-off-by: Christophe Leroy
---
drivers/spi/spi-fsl-cpm.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-fsl-cpm.c b/drivers/spi/spi-fsl-cpm.c
index 54
dynamically
allocated with cpm_muram_alloc().
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/8xx/Kconfig | 11 +++
drivers/spi/spi-fsl-cpm.c | 5 +
2 files changed, 16 insertions(+)
diff --git a/arch/powerpc/platforms/8xx/Kconfig
b/arch/powerpc/platforms/8xx
This patchset:
1) Fix parameter ram offset setup for CPM1
2) Allow dynamic allocation of CPM1 parameter RAM
Tested on MPC885.
Signed-off-by: Christophe Leroy
---
Changes from v1 to v2: using OF compatible instead of compile time option
drivers/spi/spi-fsl-cpm.c | 12 +++-
drivers
that doesn't
set SPI_BASE, pram_ofs was not properly set. This patch fixes this confusion.
Signed-off-by: Christophe Leroy
---
Changes from v1 to v2: none
drivers/spi/spi-fsl-cpm.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-fsl-cpm.c b/driver
spi" compatible is set in the
device tree, the parameter RAM for SPI is dynamically allocated
with cpm_muram_alloc().
Signed-off-by: Christophe Leroy
---
Changes from v1 to v2: using OF compatible instead of compile time option
drivers/spi/spi-fsl-cpm.c | 3 +++
drivers/spi/spi-fsl-lib
Le 03/10/2014 16:44, Mark Brown a écrit :
On Fri, Oct 03, 2014 at 02:56:09PM +0200, Christophe Leroy wrote:
+config CPM1_RELOCSPI
+ bool "Dynamic SPI relocation"
+ default n
+ help
+ On recent MPC8xx (at least MPC866 and MPC885) SPI can be relocated
+
Le 03/10/2014 21:51, Scott Wood a écrit :
On Fri, 2014-10-03 at 18:49 +0200, Christophe Leroy wrote:
On CPM1, the SPI parameter RAM has a default location. In order to use SPI while
using SCC2 with features like QMC or Ethernet, it is necessary to relocate SPI
parameter RAM in a free location
Le 03/10/2014 22:24, Scott Wood a écrit :
On Fri, 2014-10-03 at 22:15 +0200, christophe leroy wrote:
Le 03/10/2014 16:44, Mark Brown a écrit :
On Fri, Oct 03, 2014 at 02:56:09PM +0200, Christophe Leroy wrote:
+config CPM1_RELOCSPI
+ bool "Dynamic SPI relocation"
+
Le 03/10/2014 22:29, Scott Wood a écrit :
On Fri, 2014-10-03 at 18:49 +0200, Christophe Leroy wrote:
On CPM1, the SPI parameter RAM has a default location. In fsl_spi_cpm_get_pram()
there was a confusion between the SPI_BASE register and the base of the SPI
parameter RAM. Fortunatly, it was
d on MPC885 with FEC.
[PATCH 1/2] net: fs_enet: Remove non NAPI RX
[PATCH 2/2] net: fs_enet: Add NAPI TX
Signed-off-by: Christophe Leroy
---
.../net/ethernet/freescale/fs_enet/fs_enet-main.c | 211 ++---
.../net/ethernet/freescale/fs_enet/fs_enet.h | 9 +-
.../net/ethern
In the probe function, use_napi is inconditionnaly set to 1. This patch removes
all the code which is conditional to !use_napi, and removes use_napi which has
then become useless.
Signed-off-by: Christophe Leroy
---
.../net/ethernet/freescale/fs_enet/fs_enet-main.c | 164
toto pgs:/tmp
toto 100% 256MB 2.8MB/s 01:31
Performance with the patch:
[root@localhost tmp]# scp toto pgs:/tmp
toto 100% 256MB 3.4MB/s 01:16
Signed-off-by: Christophe Leroy
---
.../net/ethernet/freescale/fs_enet/
C, the SCC and FCC don't have a TXF
event (complete Frame transmitted) but only TXB (buffer transmitted).
Signed-off-by: Christophe Leroy
---
drivers/net/ethernet/freescale/fs_enet/mac-fcc.c | 2 +-
drivers/net/ethernet/freescale/fs_enet/mac-scc.c | 2 +-
2 files changed, 2 insertions(
same handling to mac-fec and mac-scc.
Tested with bridge function on MPC885 with FEC.
Reported-by: Germain Montoies
Signed-off-by: Christophe Leroy
---
drivers/net/ethernet/freescale/fs_enet/mac-fec.c | 3 +++
drivers/net/ethernet/freescale/fs_enet/mac-scc.c | 3 +++
2 files changed, 6 insertions(+)
Le 08/11/2014 01:08, Scott Wood a écrit :
OK, so the _PAGE_KERNEL_RO(X) stuff is because initially setting the PTE
doesn't go through pte_update().
I'll apply this, though it'd be cleaner to just have 8xx versions of the
relevant PTE accessor functions to maintain the PTE the way the hardware
ready partly done by the driver.
Reported-by: Patrick Vasseur
Signed-off-by: Christophe Leroy
Tested-by: Patrick Vasseur
---
drivers/spi/spi-fsl-cpm.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-fsl-cpm.c b/drivers/spi/spi-fsl-cpm.c
index 54b0637..da
include/linux/mm.h: In function 'is_vmalloc_addr':
include/linux/mm.h:367:14: warning: comparison between signed and unsigned
integer expressions [-Wsign-compare]
return addr >= VMALLOC_START && addr < VMALLOC_END;
^
Signed-off-by: Christophe Leroy
---
put_user(termios->c_line, &termio->c_line) < 0 ||
^
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/uaccess.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/uaccess.h
b/arch/powerpc/include/asm/uaccess.h
index 94
T+done, done, bl, PAGE_KERNEL_X);
^
In file included from arch/powerpc/mm/ppc_mmu_32.c:35:0:
arch/powerpc/mm/mmu_decl.h:98:13: note: expected 'int' but argument is of type
'pgprot_t'
extern void setbat(int index, unsigned long virt, phys_addr_t phys,
^
Signed-of
chrp_init_early lacks a __initdata
annotation or the annotation of boot_command_line is wrong.
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/chrp/setup.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/chrp/setup.c
b/arch/powerpc
The 8xx inverts _PAGE_RW. Lets to it in PTE accessors.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/pte-8xx.h | 1 +
arch/powerpc/kernel/head_8xx.S | 3 ---
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/pte-8xx.h
b/arch/powerpc
_PTE_HW_INVERTED into the pte-XXX.h file
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/page.h | 8 +++
arch/powerpc/include/asm/pgtable-ppc32.h | 37 +---
arch/powerpc/include/asm/pte-common.h| 3 +++
3 files changed, 32 insertions(+), 16
Some HW invert some PTE bits. In some case, __pte(0) is not 0 so the PTEs shall
be properly set prior to being used.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/pgtable_32.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc
pte_val() is not meant to be used as L value.
__pte() has to be used to assign value to pte_t.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/pgtable.h | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable.h
b/arch
-by: Christophe Leroy
Tested-by: Christophe Leroy
---
arch/powerpc/include/asm/page.h | 8 +++
arch/powerpc/include/asm/pgtable-ppc32.h | 37 +---
arch/powerpc/include/asm/pgtable.h | 17 ---
arch/powerpc/include/asm/pte-8xx.h
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index aa45225..b227902e 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch
Since commit 33fb845a6f01 ("powerpc/8xx: Don't use MD_TWC for walk"), MD_EPN and
MD_TWC are not writen anymore in FixupDAR so saving r3 has become useless.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 6 --
1 file changed, 6 deletions(-)
diff --git
When pages are not 4K, PGDIR table is allocated with kmalloc(). In order to
optimise TLB handlers, aligned memory is needed. kmalloc() doesn't provide
aligned memory blocks, so lets use a kmem_cache pool instead.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/pgtable-ppc32.h
11 - powerpc/8xx: Add support for TASK_SIZE greater than 0x8000
All changes have been successfully tested on MPC885
Signed-off-by: Christophe Leroy
Tested-by: Christophe Leroy
---
arch/powerpc/include/asm/page.h | 8 +++
arch/powerpc/include/asm/pgtable-ppc32.h | 37
Having a macro will help keep clear code.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index b227902e..b3f3cb5 100644
tries, remove all those
tests and let the 8xx handle it. This reduce the number of cycle when the
entries are valid which is the case most of the time, and doesn't significantly
increase the time for handling invalid entries.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_
All accessed to PGD entries are done via 0(r11).
By using lower part of swapper_pg_dir as load index to r11, we can remove the
ori instruction.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 22 ++
1 file changed, 10 insertions(+), 12 deletions
By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely
sufficient for most cases. However, kernel configuration allows to set TASK_SIZE
to another value, so the 8xx shall handle it.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 29
In order to be able to reduce scope during which CR is saved, we take
CR saving/restoring out of exception PROLOG and EPILOG
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel
We now have SPRG2 available as in it not used anymore for saving CR, so we don't
need to crash DAR anymore for saving r3 for CPU6 ERRATA handling.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --
e for saving CR
- Otherwise, we use r10, then we reload SRR0/MD_EPN into r10 when CR is restored
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 53 +-
1 file changed, 37 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/k
L1 base address is now aligned so we can insert L1 index into r11 directly and
then preserve r10
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 34 +++---
1 file changed, 15 insertions(+), 19 deletions(-)
diff --git a/arch/powerpc/kernel
been successfully tested on MPC885
Signed-off-by: Christophe Leroy
Tested-by: Christophe Leroy
---
v2 is a complete rework compared to v1
arch/powerpc/include/asm/pgtable-ppc32.h | 11 ++-
arch/powerpc/include/asm/pgtable.h | 10 +++---
arch/powerpc/include/asm/pte-8xx.h
On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages
and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW
Signed-off-by: Christophe Leroy
---
v2 is a complete rework compared to v1
arch/powerpc/include/asm/pte-8xx.h | 7 +++
arch/powerpc/kernel
Some powerpc like the 8xx don't have a RW bit in PTE bits but a RO (Read Only)
bit.
This patch implements the handling of a _PAGE_RO flag to be used in place of
_PAGE_RW
Signed-off-by: Christophe Leroy
---
v2 is a complete rework compared to v1
arch/powerpc/include/asm/pgtable-ppc32.h
been successfully tested on MPC885
Signed-off-by: Christophe Leroy
Tested-by: Christophe Leroy
---
v2 is a complete rework compared to v1
v3 takes into account comments from Scott on v2
arch/powerpc/include/asm/pgtable-ppc32.h | 12 +++-
arch/powerpc/include/asm/pgtable.h
Some powerpc like the 8xx don't have a RW bit in PTE bits but a RO (Read Only)
bit.
This patch implements the handling of a _PAGE_RO flag to be used in place of
_PAGE_RW
Signed-off-by: Christophe Leroy
---
v2 is a complete rework of v1
v3:
- cleared PTE can remain 0, no need of _PAGE_
On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages
and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW
Signed-off-by: Christophe Leroy
---
v2 is a complete rework compared to v1
v3: fixing pte_update() and comments
arch/powerpc/include/asm
.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/mmu_context_nohash.c | 44 +++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/mmu_context_nohash.c
b/arch/powerpc/mm/mmu_context_nohash.c
index 928ebe7..c648677 100644
--- a/arch
.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/mmu_context_nohash.c | 44 +++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/mmu_context_nohash.c
b/arch/powerpc/mm/mmu_context_nohash.c
index 928ebe7..c648677 100644
--- a/arch
I've got a MPC8323 RDB evaluation platform from freescale
kernel 4.0 doesn't boot
kernel 3.16 doesn't boot
kernel 3.15 boots ok
I disected the issue down to your commit "of/fdt: Convert FDT functions
to use libfdt" (e6a6928c3ea1d0195ed75a091e345696b916c09b)
Do you have an idea of what the issu
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