This patchset: 1) provides several MMU TLB handling optimisation on MPC8xx. 2) adds support of 16k pages on MPC8xx. All changes have been successfully tested on a custom board equipped with MPC885
Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr> Tested-by: Christophe Leroy <christophe.le...@c-s.fr> --- Changes in v2: - Patch number 10 removed, it was implementing a 16 bit alignment of the PGDIR. It is not worth potentially wasting up to 64k of memory just for removing one instruction (ori). - Preserve r11 while calculating the level 2 address, therefore no more need to save r11 into CR. Changes in v3: - Few fixes following review from Joachim Tjernlund - Removed the major hack which was saving resisters in memory for CPU6 errata - Invalidating non present TLB entries earlier (in head_8xx instead of fault.c) arch/powerpc/Kconfig | 2 +- arch/powerpc/include/asm/mmu-8xx.h | 2 + arch/powerpc/include/asm/pgtable-ppc32.h | 20 ++ arch/powerpc/include/asm/pte-8xx.h | 7 +- arch/powerpc/include/asm/reg.h | 3 +- arch/powerpc/kernel/head_8xx.S | 370 ++++++++++++------------- arch/powerpc/mm/fault.c | 9 +- 7 files changed, 203 insertions(+), 210 deletions(-) _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
