Pali Rohár writes:
> Since commit 63a72284b159 ("powerpc/pci: Assign fixed PHB number based on
> device-tree properties"), powerpc kernel always fallback to PCI domain
> assignment from OF / Device Tree 'reg' property of the PCI controller.
>
> PCI code for other Linux architectures use increasing
On Friday 10 June 2022 17:33:32 Michael Ellerman wrote:
> If you have scripts that are looking for certain devices they can use
> the vendor/device fields in sysfs to find the actual devices they want,
> not just whatever happens to be at :01:00.0.
This does not work if you have more cards wit
> On 10-Jun-2022, at 10:10 AM, Joel Stanley wrote:
>
> When booting on a machine that uses the compat pmu driver we see this:
>
> [0.071192] GENERIC_COMPAT performance monitor hardware support registered
>
> Which is a bit shouty. Give it a nicer name.
>
> Signed-off-by: Joel Stanley
>
o...@users.sourceforge.jp>, Linux-sh list , Fabio
Estevam , Helge Deller , Daniel Lezcano
, Jonathan Hunter , Mathieu
Desnoyers , Frederic Weisbecker
, Len Brown , "open list:TENSILICA XTENSA
PORT \(xtensa\)" , Sascha Hauer
, Vasily Gorbik , linux-arm-msm
, alpha ,
linux-m68k , Stafford Hor
Masahiro Yamada , Sami Tolvanen
, "Naveen N. Rao" , Marco
Elver , Kees Cook , Steven Rostedt
, Nathan Chancellor , Mark Brown
, Borislav Petkov , Alexander Egorenkov
, Thomas Bogendoerfer ,
linux-par...@vger.kernel.org, Nathaniel McCallum ,
Dmitry Torokhov , "David S. Miller"
, "Kirill A. S
Le 08/06/2022 à 01:59, Jarkko Sakkinen a écrit :
> [You don't often get email from jar...@profian.com. Learn why this is
> important at https://aka.ms/LearnAboutSenderIdentification ]
>
> Tracing with kprobes while running a monolithic kernel is currently
> impossible because CONFIG_KPROBES is
Le 08/06/2022 à 18:12, Song Liu a écrit :
> On Wed, Jun 8, 2022 at 7:21 AM Masami Hiramatsu wrote:
>>
>> Hi Jarkko,
>>
>> On Wed, 8 Jun 2022 08:25:38 +0300
>> Jarkko Sakkinen wrote:
>>
>>> On Wed, Jun 08, 2022 at 10:35:42AM +0800, Guo Ren wrote:
.
On Wed, Jun 8, 2022 at 8:02 AM J
o...@users.sourceforge.jp>, Linux-sh list , Fabio
Estevam , Helge Deller , Daniel Lezcano
, Jonathan Hunter , Mathieu
Desnoyers , Frederic Weisbecker
, Len Brown , "open list:TENSILICA XTENSA
PORT \(xtensa\)" , Sascha Hauer
, Vasily Gorbik , linux-arm-msm
, alpha ,
linux-m68k , Stafford Hor
o...@users.sourceforge.jp>, Linux-sh list , Will
Deacon , Helge Deller , Daniel Lezcano
, Jonathan Hunter , Mathieu
Desnoyers , Frederic Weisbecker
, Len Brown , "open list:TENSILICA XTENSA
PORT \(xtensa\)" , Sascha Hauer
, Vasily Gorbik , linux-arm-msm
, alpha ,
linux-m68k , Stafford Horne
li.kr...@googlemail.com, vgu...@kernel.org, linux-...@vger.kernel.org,
j...@joshtriplett.org, rost...@goodmis.org, r...@vger.kernel.org,
b...@alien8.de, bc...@quicinc.com, tsbog...@alpha.franken.de,
linux-par...@vger.kernel.org, sudeep.ho...@arm.com, shawn...@kernel.org,
da...@davemloft.net, da
This fixes the gdbserver issue on PPC32 described here:
Link:
https://linuxppc-dev.ozlabs.narkive.com/C46DRek4/debug-problems-on-ppc-83xx-target-due-to-changed-struct-task-struct
On PPC32, the user space code considers the floating point to be an
array of unsigned int (32 bits) - the index passed
Patch 1 exports the symbol ioremap_coherent which is used by the driver.
Patch 2 is the implementation of uio driver for freescale mpc85xx.
Wang Wenhu (2):
powerpc:mm: export symbol ioremap_coherent
uio:powerpc:mpc85xx: l2-cache-sram uio driver implementation
arch/powerpc/mm/ioremap.c
The function ioremap_coherent may be called by modules such as
fsl_85xx_cache_sram. So export it for access in other modules.
Signed-off-by: Wang Wenhu
---
arch/powerpc/mm/ioremap.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/mm/ioremap.c b/arch/powerpc/mm/ioremap.c
index 4f
The l2-cache could be optionally configured as SRAM partly or fully.
Users can make use of it as a block of independent memory that offers
special usage, such as for debuging or other cratical status info
storage which keeps consistently even when the whole system crashed.
The hardware related con
e>, ulli.kr...@googlemail.com, vgu...@kernel.org, linux-...@vger.kernel.org,
j...@joshtriplett.org, rost...@goodmis.org, r...@vger.kernel.org,
b...@alien8.de, bc...@quicinc.com, tsbog...@alpha.franken.de,
linux-par...@vger.kernel.org, sudeep.ho...@arm.com, shawn...@kernel.org,
da...@davemloft.n
>, Jarkko Sakkinen , Sami Tolvanen
>, "Naveen N. Rao" , Marco
>Elver , Kees Cook , Steven Rostedt
>, Nathan Chancellor , Mark Brown
>, Borislav Petkov , Alexander Egorenkov
>, Thomas Bogendoerfer ,
>linux-par...@vger.kernel.org, Nathaniel McCallum ,
>Dmitry Torokhov , "David S. Miller"
>, "
Alexei Starovoitov , Will Deacon , Masahiro
Yamada , Jarkko Sakkinen , Sami
Tolvanen , "Naveen N. Rao"
, Marco Elver , Kees Cook
, Steven Rostedt , Nathan
Chancellor , "Russell King \(Oracle\)"
, Mark Brown , Borislav Petkov
, Alexander Egorenkov , Thomas
Bogendoerfer , "linux-par...@vger.k
o...@kernel.org>, Jarkko Sakkinen , Sami Tolvanen
, "Naveen N. Rao" , Marco
Elver , Kees Cook , Steven Rostedt
, Nathan Chancellor , "Russell King
\(Oracle\)" , Mark Brown ,
Borislav Petkov , Alexander Egorenkov ,
Thomas Bogendoerfer , Parisc List
, Nathaniel McCallum ,
Dmitry Torokhov , "D
ada , Jarkko Sakkinen , Sami Tolvanen
, "Naveen N. Rao" , Marco
Elver , Kees Cook , Steven Rostedt
, Nathan Chancellor , "Russell King
\(Oracle\)" , Mark Brown ,
Borislav Petkov , Alexander Egorenkov ,
Thomas Bogendoerfer , Parisc List
, Nathaniel McCallum ,
Dmitry Torokhov , "David S. Mill
@kernel.org>, Masahiro Yamada , Jarkko Sakkinen
, Sami Tolvanen , "Naveen N. Rao"
, Marco Elver , Kees Cook
, Steven Rostedt , Nathan
Chancellor , "Russell King \(Oracle\)"
, Mark Brown , Borislav Petkov
, Alexander Egorenkov , Thomas
Bogendoerfer , Parisc List
, Nathaniel McCallum ,
Dmitr
l...@kernel.org>, Masahiro Yamada , Jarkko Sakkinen
, Sami Tolvanen , "Naveen N. Rao"
, Marco Elver , Kees Cook
, Steven Rostedt , Nathan
Chancellor , "Russell King \(Oracle\)"
, Mark Brown , Borislav Petkov
, Alexander Egorenkov , Thomas
Bogendoerfer , Parisc List
, Nathaniel McCallum ,
D
Le 09/06/2022 à 14:57, Jarkko Sakkinen a écrit :
> On Thu, Jun 09, 2022 at 08:30:12AM +, Christophe Leroy wrote:
>>
>>
>> Le 08/06/2022 à 01:59, Jarkko Sakkinen a écrit :
>>> [You don't often get email from jar...@profian.com. Learn why this is
>>> important at https://aka.ms/LearnAboutSende
, Jarkko Sakkinen , Sami Tolvanen
, "Naveen N. Rao" , Marco
Elver , Kees Cook , Steven Rostedt
, Nathan Chancellor , Mark Brown
, Borislav Petkov , Alexander Egorenkov
, Thomas Bogendoerfer ,
linux-par...@vger.kernel.org, Nathaniel McCallum ,
Dmitry Torokhov , "David S. Miller"
, "Kirill A.
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, Sami Tolvanen , "Naveen N. Rao"
, Marco Elver , Kees Cook
, Steven Rostedt , Nathan
Chancellor , "Russell King \(Oracle\)"
, Mark Brown , Borislav Petkov
, Alexander Egorenkov , Thomas
Bogendoerfer , Parisc List
, Nathaniel McCallum ,
Dmitry Torokh
k...@kernel.org" , "ebied...@xmission.com"
, "aneesh.ku...@linux.ibm.com"
, "bris...@redhat.com" ,
"wangkefeng.w...@huawei.com" , "ker...@esmil.dk"
, "jniet...@gmail.com" ,
"paul.walms...@sifive.com" , "a...@kernel.org"
, "w...@kernel.org" , "masahi...@kernel.org"
, "Sakkinen, Jarkko" ,
"sa
, Arnd Bergmann , ulli.kr...@googlemail.com, vgu...@kernel.org,
linux-...@vger.kernel.org, j...@joshtriplett.org, rost...@goodmis.org,
r...@vger.kernel.org, b...@alien8.de, bc...@quicinc.com,
tsbog...@alpha.franken.de, linux-par...@vger.kernel.org, sudeep.ho...@arm.com,
shawn...@kernel.org, da.
On PPC32, there are two indexes used for each FPR.
The last two indexes into the imaginary address space "USER area" are
used to access fpscr instead of the FPR registers. Fix the validation
condition so that the access of the FPR array doesn't overflow into
fpscr. Also split the access of fpscr
On PPC32, there are two indexes used for each FPR.
The last two indexes into the imaginary address space "USER area" are
used to access fpscr instead of the FPR registers. Fix the validation
condition so that the access of the FPR array doesn't overflow into
fpscr. Also split the access of fpscr
All of the DW PCIe core driver entities have names with the dw_ prefix in
order to easily distinguish local and common PCIe name spaces. All except
the pcie_port structure which contains the DW PCIe Root Port descriptor.
For historical reason the structure has retained the original name since
commi
On PPC32, there are two indexes used for each FPR.
The last two indexes into the imaginary address space "USER area" are
used to access fpscr instead of the FPR registers. Fix the validation
condition so that the access of the FPR array doesn't overflow into
fpscr. Also split the access of fpscr
On PPC32, there are two indexes used for each FPR.
The last two indexes into the imaginary address space "USER area" are
used to access fpscr instead of the FPR registers. Fix the validation
condition so that the access of the FPR array doesn't overflow into
fpscr. Also split the access of fpscr
From: Ariel Miculas
On PPC32, there are two indexes used for each FPR.
The last two indexes into the imaginary address space "USER area" are
used to access fpscr instead of the FPR registers. Fix the validation
condition so that the access of the FPR array doesn't overflow into
fpscr. Also spli
On PPC32, there are two indexes used for each FPR.
The last two indexes into the imaginary address space "USER area" are
used to access fpscr instead of the FPR registers. Fix the validation
condition so that the access of the FPR array doesn't overflow into
fpscr. Also split the access of fpscr
Commit 4c08d4bbc089 ("powerpc/papr_scm: Add perf interface support")
adds performance monitoring support for papr-scm nvdimm devices via
perf interface. It also adds one array in papr_scm_priv
structure called "nvdimm_events_map", to dynamically save the stat_id
for events specified in nvdimm drive
Patch series extends the perf interface selftests
to cover scenarios for event code checking,
group constraints, and also thresholding/branch related
interface tests in sampling area.
In this series, patches 1 to 14 adds additional tests under
"powerpc/sampling_tests". These adds support for handl
From: Kajol Jain
In power10, threshold compare field is not part of the raw
event code and provided via event attribute config1.
Hence add the mask and shift bits based on event attribute
config1, to extract the threshold compare value for power10
Also add a new function called get_thresh_cmp_va
The /proc/self/auxv contains information about "platform" on any
system. Also "base platform" which is an indication about platform
string corresponding to the real PVR. When systems are booted in
compat mode, say, power10 booted in power9 mode, "platform" will
point to power9 whereas base platform
From: Kajol Jain
The testcase uses event code 0x35340401e0 for load
only sampling, to verify the settings of thresh compare field
in Monitor Mode Control Register A (MMCRA: 9-18 bits for power9
and MMCRA: 8-18 bits for power10). Testcase checks if the thresh compare
field is programmed correctly
From: Kajol Jain
Add support for sample type as PERF_SAMPLE_BRANCH_STACK in sampling
tests. This change is a precursor/helper for sampling testcases, that
test branck stack feature in perf interface.
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/sampling_tests/misc.c | 21 +
From: Kajol Jain
The testcase uses "instructions" event to check if the
Instruction filtering mode(IFM) bits are programmed correctly
for indirect branch type. Testcase checks if IFM bits are
programmed correctly to Monitor Mode Control Register A (MMCRA)
via perf interface for ISA v3.1 platform.
From: Kajol Jain
The testcase uses "instructions" event to check if the
Instruction filtering mode(IFM) bits are programmed correctly
for type any branch. Testcase checks if IFM bits is
programmed correctly to Monitor Mode Control Register A (MMCRA)
via perf interface.
Signed-off-by: Kajol Jain
From: Kajol Jain
The testcase uses "instructions" event to check if the
Instruction filtering mode(IFM) bits are programmed correctly
for conditional branch type. Testcase checks if IFM bits is
programmed correctly to Monitor Mode Control Register A (MMCRA)
via perf interface for ISA v3.1 platfor
From: Kajol Jain
The testcase uses "instructions" event to generate the
samples and fetch Monitor Mode Control Register A (MMCRA)
when overflow. Branch History Rolling Buffer(bhrb) disable bit
is part of MMCRA which need to be verified by perf interface.
Testcase checks if the bhrb disable bit of
The platform check for selftest support "check_pvr_for_sampling_tests"
is specific to sampling tests which includes PVR check, presence of
PMU and extended regs support. Extended regs support is needed for
sampling tests which tests whether PMU registers are programmed
correctly. There could be oth
While enabling branch stack for an event, BHRB (Branch History
Rolling Buffer) filter is set using bhrb_filter_map() callback.
This callback is not defined for cases like generic_compat_pmu
or in case where there is no PMU registered. A fix was added
in kernel to address a crash issue observed whil
With sampling, --intr-regs option is used for capturing
interrupt regs. When --intr-regs option is used, PMU code
uses is_sier_available() function which uses PMU flags in
the code. In environment where platform specific PMU is
not registered, PMU flags is not defined. A fix was added
in kernel to
For PERF_SAMPLE_BRANCH_STACK sample type, different
branch_sample_type, ie branch filters are supported.
All the branch filters are not supported in powerpc.
Example, power10 platform supports any, ind_call and
cond branch filters. Whereas, it is different in power9.
Testcase checks event open for
The testcase uses event code "0x21c040" to verify
the settings for different fields in Monitor Mode Control
Register 1 (MMCR1). The fields include PMCxSEL, PMCXCOMB
PMCxUNIT, cache. Checks if these fields are translated
correctly via perf interface to MMCR1
Signed-off-by: Athira Rajeev
---
.../p
From: Kajol Jain
The testcase uses "instructions" event to generate the
samples and fetch Monitor Mode Control Register A (MMCRA)
when overflow. Branch History Rolling Buffer(bhrb) disable bit
is part of MMCRA which need to be verified by perf interface.
Incase sample is not of branch type, bhrb
Add new folder for enabling perf event code tests which
includes checking for group constraints, valid/invalid events,
also checks for event excludes, alternatives so on. A new folder
"event_code_tests", is created under "selftests/powerpc/pmu".
Also updates the corresponding Makefiles in "selftes
Events using Performance Monitor Counter 5 (PMC5) and
Performance Monitor Counter 6 (PMC6) can't have other fields in
event code like cache bits, thresholding or marked bit. PMC5 and PMC6
only supports base events: ie 500fa and 600f4. Other combinations
should fail. Testcase tries setting other bit
Events using Performance Monitor Counter 5 (PMC5) and
Performance Monitor Counter 6 (PMC6) should be excluded
from constraint check when scheduled along with group of
events. Example, combination of PMC5, PMC6, and an event
with cache bit will succeed to schedule though first two
events doesn't hav
Testcase for group constraint check for number of
counters in use. The number of programmable counters
is from PMC1 to PMC4. Testcase uses four events with PMC1
to PMC4 and 5th event without any PMC which is expected to fail
since it is exceeding the number of counters in use.
Signed-off-by: Athir
Testcase for group constraint check when using events
with same PMC. Multiple events in a group asking for
same PMC should fail. Testcase uses "0x22C040" on PMC2
as leader and also subling which is expected to fail.
Using PMC1 for sibling event should pass the test.
Signed-off-by: Athira Rajeev
-
Testcase for group constraint check for radix_scope_qual
field which is used to program Monitor Mode Control Register
(MMCR1) bit 18. All events in the group should match radix_scope_qual
bit, otherwise event_open for the group should fail. Testcase uses
"0x14242" (PM_DATA_RADIX_PROCESS_L2_PTE_FROM
Testcase for reserved bits in Monitor Mode Control
Register A (MMCRA) Random Sampling Mode (SM) value.
As per Instruction Set Architecture (ISA), the values
0x5, 0x9, 0xD, 0x19, 0x1D, 0x1A, 0x1E are reserved
for sampling mode field. Test that having these reserved
bit values should cause event_open
Events with different "sample" field values which is
used to program Monitor Mode Control Register A (MMCRA)
in a group will fail to schedule. Testcase uses event with
load only sampling mode as group leader and event with
store only sampling as sibling event. So that it can check
that using differ
Some of the bits in the event code is reserved
for specific platforms. Event code bits 52-59 are
reserved in power9, whereas in power10, these are used
for programming Monitor Mode Control Register 3 (MMCR3).
Bit 9 in event code is reserved in power9, whereas it
is used for programming "radix_scope
Testcase for reserved bits in Monitor Mode
Control Register A (MMCRA) thresh_ctl bits.
For MMCRA[48:51]/[52:55]) Threshold Start/Stop,
0b/0b is reserved.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../reserved_bits_mmcra_thresh_ctl_tes
Some of the events are blacklisted in power9. The list
of blacklisted events are noted in power9-events-list.h
When trying to do event open for any of these blacklisted
event will cause a failure. Testcase ensures that using
blacklisted events will cause event_open to fail in power9.
This test is o
Platform specific PMU supports alternative event for some
of the event codes. During perf_event_open, it any event
group doesn't match constraint check criteria, further lookup
is done to find alternative event. Code checks to see if
it is possible to schedule event as group using alternative
event
Platform specific PMU supports alternative event for some
of the event codes. During perf_event_open, it any event
group doesn't match constraint check criteria, further lookup
is done to find alternative event. Code checks to see if
it is possible to schedule event as group using alternative
event
Testcase to ensure that using invalid event in generic
event for PERF_TYPE_HARDWARE will fail. Invalid generic
events in power10 are:
- PERF_COUNT_HW_BUS_CYCLES
- PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
- PERF_COUNT_HW_STALLED_CYCLES_BACKEND
- PERF_COUNT_HW_REF_CPU_CYCLES
Invalid generic events in p
From: Kajol Jain
In power10, L2L3 select bits in the event code is used to
program l2l3_sel field in Monitor Mode Control Register 0
(MMCR0: 56-60). When scheduling events as a group,
all events in that group should match value in these bits.
Otherwise event open for the sibling events will fail.
From: Kajol Jain
Data and instruction cache qualifier bits in the event code is
used to program cache select field in Monitor Mode Control
Register 1 (MMCR1: 16-17). When scheduling events as a group, all
events in that group should match value in these bits. Otherwise
event open for the sibling
From: Kajol Jain
Thresh compare bits for a event is used to program thresh compare
field in Monitor Mode Control Register A (MMCRA: 9-18 bits for
power9 and MMCRA: 8-18 bits for power10). When scheduling events
as a group, all events in that group should match value in
thresh compare bits. Otherw
From: Kajol Jain
Unit and pmu bits in the event code is used to program unit and pmc
fields in Monitor Mode Control Register 1 (MMCR1). For power9 platform,
incase unit field value is within 6 to 9, one of the event in the group
should use PMC4. Otherwise event_open should fail for that group.
S
From: Kajol Jain
Thresh control bits in the event code is used to program thresh_ctl
field in Monitor Mode Control Register A (MMCRA: 48-55). When scheduling
events as a group, all events in that group should match value in these
bits. Otherwise event open for the sibling events will fail.
Testc
From: Kajol Jain
Thresh select bits in the event code is used to program thresh_sel
field in Monitor Mode Control Register A (MMCRA: 45-47). When scheduling
events as a group, all events in that group should match value in these
bits. Otherwise event open for the sibling events will fail.
Testca
From: Kajol Jain
The testcase checks if the transalation of a generic hardware cache
event is done properly via perf interface. The hardware cache events
has type as PERF_TYPE_HW_CACHE and each event points to raw event
code id.
Testcase checks different combination of cache level,
cache event o
commit cfd7092c31ae ("perf test session topology: Fix test to
skip the test in guest environment") added check to skip the
testcase if the socket_id can't be fetched from topology info.
But the condition check uses strncmp which should be changed to
!strncmp and to correctly match platform. Patch f
Hi!
On Fri, Jun 10, 2022 at 01:32:58PM +1000, Rohan McLure wrote:
> > On 2 Jun 2022, at 2:00 am, Segher Boessenkool
> > wrote:
> > This is for unary operations, not binary operations (there is only one
> > item on the RHS). You can in principle put a string "a,b" in the rhs
> > parameter, but i
When CONFIG_KASAN is selected, we expect prom_init to use __memset()
because it is too early to use memset().
But with CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL, the compiler adds calls
to memset() to clear objects on stack, hence the following failure:
PROMCHK arch/powerpc/kernel/prom_ini
This patchset adds atomic operations to the eBPF instruction set on
powerpc. The instructions that are added here can be summarised with
this list of kernel operations for ppc64:
* atomic[64]_[fetch_]add
* atomic[64]_[fetch_]and
* atomic[64]_[fetch_]or
* atomic[64]_[fetch_]xor
* atomic[64]_xchg
*
Adding instructions for ppc64 for
atomic[64]_and
atomic[64]_or
atomic[64]_xor
Signed-off-by: Hari Bathini
---
* No changes in v2.
arch/powerpc/net/bpf_jit_comp64.c | 57 ---
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/arch/powerpc/net/bpf_jit_c
Adding instructions for ppc64 for
atomic[64]_fetch_add
atomic[64]_fetch_and
atomic[64]_fetch_or
atomic[64]_fetch_xor
Signed-off-by: Hari Bathini
---
* No changes in v2.
arch/powerpc/net/bpf_jit_comp64.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/p
This adds two atomic opcodes BPF_XCHG and BPF_CMPXCHG on ppc64, both
of which include the BPF_FETCH flag. The kernel's atomic_cmpxchg
operation fundamentally has 3 operands, but we only have two register
fields. Therefore the operand we compare against (the kernel's API
calls it 'old') is hard-cod
Adding instructions for ppc32 for
atomic_and
atomic_or
atomic_xor
atomic_fetch_add
atomic_fetch_and
atomic_fetch_or
atomic_fetch_xor
Signed-off-by: Hari Bathini
---
Changes in v2:
* Used an additional register (BPF_REG_AX)
- to avoid clobbering src_reg.
- to keep the lwarx reservation a
This adds two atomic opcodes BPF_XCHG and BPF_CMPXCHG on ppc32, both
of which include the BPF_FETCH flag. The kernel's atomic_cmpxchg
operation fundamentally has 3 operands, but we only have two register
fields. Therefore the operand we compare against (the kernel's API
calls it 'old') is hard-cod
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
fixes-test
branch HEAD: 8e127846fc97778a5e5c99bca1ce0bbc5ec9 powerpc/32: Fix
overread/overwrite of thread_struct via ptrace
elapsed time: 1543m
configs tested: 64
configs skipped: 101
The following configs have
gkai Hu , "linux-arm-ker...@lists.infradead.org"
, Roy Zang , Jingoo Han
, "linuxppc-dev@lists.ozlabs.org"
, Heiko Stuebner ,
"linux-ker...@vger.kernel.org" , Serge Semin
, Krzysztof Kozlowski
, Masami Hiramatsu ,
Pengutronix Kernel Team , Gustavo Pimentel
, Shawn Guo , Lucas Stach
Errors
Hi Christoph,
On 6/8/22 10:05 PM, Christoph Hellwig wrote:
> All this really needs to be hidden under the hood.
>
Since this patch file has 200+ lines, would you please help clarify what does
'this' indicate?
The idea of this patch:
1. Convert the functions to initialize swiotlb into callee. T
commit 8e127846fc97778a5e5c99bca1ce0bbc5ec9 upstream.
The ptrace PEEKUSR/POKEUSR (aka PEEKUSER/POKEUSER) API allows a process
to read/write registers of another process.
To get/set a register, the API takes an index into an imaginary address
space called the "USER area", where the registers o
From: Ira Weiny
err was being used in test_pkey_alloc_exhaust() prior to being assigned.
errno is useful to know after a failed alloc_pkey() call.
Change err to errno in the debug print.
Cc: Dave Hansen
Cc: Aneesh Kumar K.V
Signed-off-by: Ira Weiny
---
tools/testing/selftests/vm/protection_
From: Ira Weiny
x86 is missing a hardware check for pkey support in pkey_free(). While
the net result is the same (-EINVAL returned), pkey_free() has well
defined behavior which will be easier to maintain in one place.
For powerpc the return code is -1 rather than -EINVAL. This changes
that be
From: Ira Weiny
It is more convenient to use command line options for debug and
iterations vs changing the code and recompiling.
Add command line options for debug level and number of iterations.
$ ./protection_keys_64 -h
Usage: ./protection_keys_64 [-h,-d,-i ]
--help,-h This help
From: Ira Weiny
While evaluating the possibility of defining a new type for pkeys within the
kernel I found a couple of minor bugs.
Because these patches clean up the return codes from system calls I'm sending
this out RFC hoping that users will speak up if anything breaks.
I'm not too concern
From: Ira Weiny
When pkeys are not available on the hardware pkey_alloc() has specific
behavior which was previously untested.
Add test for this.
Cc: Dave Hansen
Cc: Aneesh Kumar K.V
Signed-off-by: Ira Weiny
---
tools/testing/selftests/vm/protection_keys.c | 12
1 file changed,
From: Ira Weiny
pkey_alloc() is documented to return ENOSPC when the hardware does not
support pkeys. On x86, pkey_alloc() incorrectly returns EINVAL.
This is because mm_pkey_alloc() does not check for pkey support before
returning a key. Therefore, if the keys are not exhausted pkey_alloc()
c
From: Ira Weiny
Now that the pkey arch support is no longer checked in mm_pkey_free()
there is no reason to have it return int.
Change the return value to void.
Cc: Dave Hansen
Cc: Aneesh Kumar K.V
Suggested-by: Sohil Mehta
Signed-off-by: Ira Weiny
---
arch/powerpc/include/asm/pkeys.h | 4
commit 8e127846fc97778a5e5c99bca1ce0bbc5ec9 upstream.
The ptrace PEEKUSR/POKEUSR (aka PEEKUSER/POKEUSER) API allows a process
to read/write registers of another process.
To get/set a register, the API takes an index into an imaginary address
space called the "USER area", where the registers o
commit 8e127846fc97778a5e5c99bca1ce0bbc5ec9 upstream.
The ptrace PEEKUSR/POKEUSR (aka PEEKUSER/POKEUSER) API allows a process
to read/write registers of another process.
To get/set a register, the API takes an index into an imaginary address
space called the "USER area", where the registers o
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
merge
branch HEAD: 8582c0462f3d6c6067962623f1072daf25f6d560 Automatic merge of
'fixes' into merge (2022-06-10 00:07)
elapsed time: 2212m
configs tested: 83
configs skipped: 3
The following configs have been built s
commit 8e127846fc97778a5e5c99bca1ce0bbc5ec9 upstream.
The ptrace PEEKUSR/POKEUSR (aka PEEKUSER/POKEUSER) API allows a process
to read/write registers of another process.
To get/set a register, the API takes an index into an imaginary address
space called the "USER area", where the registers o
commit 8e127846fc97778a5e5c99bca1ce0bbc5ec9 upstream.
The ptrace PEEKUSR/POKEUSR (aka PEEKUSER/POKEUSER) API allows a process
to read/write registers of another process.
To get/set a register, the API takes an index into an imaginary address
space called the "USER area", where the registers o
Commit f9b3cd245784 ("Kconfig.debug: make DEBUG_INFO selectable from a
choice") broke the selection of CONFIG_DEBUG_INFO by powerpc defconfigs.
It is now necessary to select one of the three DEBUG_INFO_DWARF*
options to get DEBUG_INFO enabled.
Replace DEBUG_INFO=y by DEBUG_INFO_DWARF_TOOLCHAIN_DE
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